MICREL SY89876LMG

Precision Edge®
3.3V, 2.0GHz ANY DIFFERENTIAL IN-TO-LVDS
®
SY89876L
Precision Edge
PROGRAMMABLE CLOCK DIVIDER AND
1:2 FANOUT BUFFER W/ INTERNAL TERMINATION SY89876L
Micrel, Inc.
FEATURES
DESCRIPTION
„ Integrated programmable clock divider and 1:2
fanout buffer
„ Guaranteed AC performance over temperature and
voltage:
• >2.0GHz fMAX
• <190ps tr / tf
• <15ps within device skew
„ Low jitter design:
• <10psPP total jitter
• <1psRMS cycle-to-cycle jitter
„ Unique input termination and VT Pin for DC- and ACcoupled inputs; CML, PECL, LVDS and HSTL
„ LVDS-compatible outputs
„ TTL/CMOS inputs for select and reset
„ Parallel programming capability
„ Programmable divider ratios of 1, 2, 4, 8 and 16
„ Low voltage operation 3.3V
„ Output disable function
„ –40°C to 85°C industrial temperature range
„ Available in 16-pin (3mm x 3mm) MLF® package
This low-skew, low-jitter device is capable of accepting a
high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS
or HSTL clock input signal and dividing down the frequency
using a programmable divider ratio to create a lower speed
version of the input clock. Available divider ratios are 2, 4, 8
and 16, or straight pass-through.
The differential input buffer has a unique internal
termination design that allows access to the termination
network through a VT pin. This feature allows the device to
easily interface to different logic standards. A VREF-AC
reference is included for AC-coupled applications.
The /RESET input asynchronously resets the divider. In
the pass-through function (divide by 1) the /RESET
synchronously enables or disables the outputs on the next
falling edge of IN (rising edge of /IN).
TYPICAL PERFORMANCE
APPLICATIONS
„ SONET/SDH line cards
„ Transponders
„ High-end, multiprocessor servers
OC-12 to OC-3
Translator/Divider
CML/LVPECL/LVDS
622MHz
Clock In
FUNCTIONAL BLOCK DIAGRAM
LVDS
155.5MHz
Clock Out
Divide-by-4
S2
(TTL/CMOS)
/RESET
(TTL/CMOS)
622MHz In
Enable
FF
IN
Q0
Enable
MUX
/Q0
MUX
/IN
Q1
IN
Divided
by
2, 4, 8
or 16
50Ω
VT
50Ω
/IN
S1
(TTL/CMOS)
/Q1
Q0
155.5MHz Out
Decoder
S0
(TTL/CMOS)
/Q0
VREF_AC
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
M9999-082407
[email protected] or (408) 955-1690
Rev.: E
1
Amendment: /0
Issue Date: August 2007
Precision Edge®
SY89876L
Micrel, Inc.
S0
S1
VCC
GND
PACKAGE/ORDERING INFORMATION
16
15
14
13
Ordering Information(1)
Part Number
Package Operating
Type
Range
Package
Marking
Lead
Finish
876L
Sn-Pb
SY89876LMI
MLF-16
Industrial
VT
SY89876LMITR(2)
MLF-16
Industrial
876L
Sn-Pb
Q1
3
10
VREF-AC
SY89876LMG(3)
MLF-16
Industrial
/Q1
4
9
876L with
Pb-Free bar-line indicator
Pb-Free
NiPdAu
SY89876LMGTR(2, 3)
MLF-16
Industrial
876L with
Pb-Free bar-line indicator
Pb-Free
NiPdAu
5
6
7
8
VCC
IN
11
/RESET
12
2
S2
1
NC
Q0
/Q0
/IN
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
16-Pin MLF® (MLF-16)
PIN DESCRIPTION
Pin Number
Pin Name
12, 9
IN, /IN
Pin Function
1, 2, 3, 4
Q0, /Q0
Q1, /Q1
16, 15, 5
S0, S1, S2
6
NC
8
/RESET,
/DISABLE
LVTTL/CMOS Logic Levels: Internal 25ký pull-up resistor. Logic HIGH if left unconnected.
Apply LOW to reset the divider (divided by 2, 4, 8 or 16 mode). Also acts as a disable/enable
function. The reset and disable function occurs on the next high-to-low clock input transition.
Input threshold is VCC/2.
10
VREF-AC
Reference Voltage: Equal to VCC–1.4V (approx.). Used for AC-coupled applications only.
Decouple the VREF–AC pin with a 0.01µF capacitor. See “Input Interface Applications” section.
11
VT
7, 14
VCC
13
GND, Exposed
pad
Differential Input: Internal 50ý termination resistors to VT input. Flexible input accepts any
differential input. See “Input Interface Applications” section.
Differential Buffered LVDS Outputs: Divided by 1, 2, 4, 8 or 16. See “Truth Table.”
Unused output pairs must be terminated with 100ý across the different pair.
Select Pins: See “Truth Table.” LVTTL/CMOS logic levels. Internal 25ký pull-up resistor.
Logic HIGH if left unconnected (divided by 16 mode.) Input threshold is VCC/2.
No Connect.
Termination Center-Tap: For CML or LVDS inputs, leave this pin floating. Otherwise, See
Figures 4a to 4f “Input Interface Applications” section.
Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitor.
Ground. Exposed pad must be connected to the same potential as the GND pin.
TRUTH TABLE
/RESET(1)
S2
S1
S0
Outputs
1
0
X
X
Reference Clock (pass through)
1
1
0
0
Reference Clock ÷2
1
1
0
1
Reference Clock ÷4
1
1
1
0
Reference Clock ÷8
1
1
1
1
Reference Clock ÷16
0(1)
X
X
X
Q = LOW, /Q = HIGH
Clock Disable
Note:
1. Reset/Disable function is asserted on the next clock input (IN, /IN)
high-to-low transition.
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Precision Edge®
SY89876L
Micrel, Inc.
Absolute Maximum Ratings(Note 1)
Operating Ratings(Note 2)
Supply Voltage (VCC) ................................... –0.5V to +4.0V
Input Voltage (VIN) ................................... –0.5V to VCC+0.3
ECL Output Current (IOUT)
Continuous .......................................................... 50mA
Surge .................................................................100mA
Input Current IN, /IN (IIN) ......................................... ±50mA
VT Current (IVT) ...................................................... ±100mA
VREF-AC Sink/Source Current (IVREF-AC), Note 3 ...... ±2mA
Lead Temperature (soldering 20 sec.) ...................... 260°C
Storage Temperature (TS) ........................ –65°C to +150°C
Supply Voltage (VCC) ....................................... +3.3V ±10%
Ambient Temperature (TA) ......................... –40°C to +85°C
Package Thermal Resistance
MLF® (θJA)
Still-Air ............................................................. 60°C/W
500lfpm ........................................................... 54°C/W
MLF® (ψJB), Note 4
Junction-to-Board ............................................ 32°C/W
Note 1.
Note 2.
Note 3.
Note 4.
Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is
not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng
conditions for extended periods may affect device reliability.
The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
Due to the limited drive capability use for input of the same package only.
Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB.
DC ELECTRICAL CHARACTERISTICS(Notes 1, 2)
TA= –40°C to +85°C; Unless otherwise stated.
Symbol
Parameter
VCC
Power Supply
ICC
Power Supply Current
RIN
Differential Input Resistance
(IN-to-/IN)
VIH
Input High Voltage (IN, /IN)
VIL
Max
Units
3.6
V
75
100
mA
90
100
110
ý
Note 2
0.1
–
VCC+0.3
V
Input Low Voltage (IN, /IN)
Note 2
–0.3
–
VIH–0.1
V
VIN
Input Voltage Swing
Note 3
0.1
–
VCC
V
VDIFF_IN
Differential Input Voltage Swing
Note 4
0.2
–
|IIN|
Input Current (IN, /IN)
Note 2
–
–
VREF–AC
Reference Voltage
Note 5
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Condition
Min
Typ
3.0
No load, max. VCC
V
45
VCC–1.525 VCC–1.425 VCC–1.325
mA
V
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Specification for packaged product only.
Due to the internal termination (see Figure 2a) the input current depends on the applied voltages at IN, /IN and VT inputs. Do not apply a combination
of voltages that causes the input current to exceed the maximum limit!
See “Timing Diagram” for VIN definition. VIN (Max) is specified when VT is floating.
See “Typical Operating Characteristics” section for VDIFF definition.
Operating using VIN is limited to AC-coupled PECL or CML applications only. Connect directly to VT pin.
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Precision Edge®
SY89876L
Micrel, Inc.
LVDS DC ELECTRICAL CHARACTERISTICS(Notes 1, 2)
VCC = 3.3V ±10%; RL = 100ý across the outputs; TA = –40°C to +85°C; Unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
VOUT
Output Voltage Swing
Note 3, 4
350
400
mV
VOH
Output High Voltage
Note 3
1.475
V
VOL
Output Low Voltage
Note 3
0.925
VOCM
Output Common Mode Voltage
Note 4
1.125
1.375
V
∆VOCM
Change in Common Mode Voltage
–50
50
mV
Note 1.
Note 2.
Note 3.
Note 4.
250
V
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Specification for packaged product only.
Measured as per Figure 3a, 100ý across Q and /Q outputs.
Measured as per Figure 3b.
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS(Notes 1, 2)
VCC = 3.3V ±10%; TA = –40°C to +85°C; Unless otherwise stated.
Symbol
Parameter
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIH
Input HIGH Current
IIL
Input LOW Current
Note 1.
Note 2.
Condition
Min
Typ
Max
2.0
V
0.8
V
20
µA
–300
µA
–125
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Specification for packaged product only.
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Units
Precision Edge®
SY89876L
Micrel, Inc.
AC ELECTRICAL CHARACTERISTICS(Notes 1)
VCC = 3.3V ±10%; RL = 100ý across the outputs; TA = –40°C to +85°C; Unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
fMAX
Maximum Input Frequency
VOUT ž 200mV
2.0
2.5
tPD
Differential Propagation Delay
IN to Q
Input Swing < 400mV
590
690
870
ps
Input Swing ž 400mV
540
640
820
ps
5
15
ps
280
ps
tSKEW
Max
Units
GHz
Within-Device Skew (diff.)
Note 2
Part-to-Part Skew (diff.)
Note 2
tRR
Reset Recovery Time
Note 3
Tjitter
Cycle-to-Cycle Jitter
Note 4
1
psRMS
Total Jitter
Note 5
10
psPP
190
ps
tr,tf
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
600
Rise/Fall Time (20% to 80%)
60
ps
110
Measured with 400mV input signal, 50% duty cycle, all outputs loaded with 100ý across each output pair, unless otherwise stated.
Skew is measured between outputs under identical transitions.
See “Timing Diagram.”
Cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. Tjitter_cc = Tn–Tn+1,
where T is the time between rising edges of the output signal.
Total jitter definition: with an ideal clock input of frequency - fMAX, no more than one output edge in 1012 output edges will deviate by more
than the specified peak-to-peak jitter value.
TIMING DIAGRAM
/RESET
VCC/2
tRR
IN
VIN
/IN
VIN Swing
tPD
/Q
VOUT Swing
Q
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Precision Edge®
SY89876L
Micrel, Inc.
TYPICAL OPERATING CHARACTERISTICS
VCC = 3.3V, RL = 100ý across the output; TA = 25°C, unless otherwise stated.
Q Output Amplitude
vs. Frequency
700
PROPAGATION DELAY (ps)
350
Q AMPLITUDE (mV)
300
250
200
150
100
50
0
0
1 1.5 2 2.5 3
FREQUENCY (MHz)
675
650
625
600
100
3.5
IN to Q Propagation Delay
vs. Temperature
60
750
700
650
600
550
500
-60 -40 -20 0 20 40 60 80 100
TEMPERATURE (°C)
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300
500
700
900
1100
INPUT SWING (mV)
OUTPUT DUTY CYCLE (%)
PROPAGATION DELAY (ps)
800
0.5
IN to Q Propagation Delay
vs. Input Swing
55
50
45
40
0
6
Output Duty Cycle
vs. Frequency
500 1000 1500 2000 2500 3000
FREQUENCY (MHz)
Precision Edge®
SY89876L
Micrel, Inc.
TYPICAL OPERATING CHARACTERISTICS (Continued)
VCC = 3.3V, VIN = 100mV, RL = 100ý across the output; TA = 25°C, unless otherwise stated.
1.25GHz Output
Output Swing
(50mV/div.)
Output Swing
(50mV/div.)
622MHz Output
TIME (300ps/div.)
TIME (130ps/div.)
Output Swing
(50mV/div.)
2.5GHz Output
TIME (80ps/div.)
DEFINITION OF SINGLE-ENDED AND DIFFERENTIAL SWINGS
VDIFF_IN, VDIFF_OUT
700mV (typical)
VIN, VOUT
350mV
(typical)
Figure 1b. Differential Swing
Figure 1a. Single-Ended Swing
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Precision Edge®
SY89876L
Micrel, Inc.
INPUT INTERFACE APPLICATIONS
VCC
VCC
1.86k
1.86k
1.86k
25kΩ
R
S0
S1
S2
/RESET
1.86k
R
IN
50Ω
VT
50Ω
GND
GND
/IN
Figure 2b. Simplified TTL/CMOS Input Buffer
Figure 2a. Simplified Differential Input Buffer
LVDS OUTPUTS
LVDS (Low Voltage Differential Swing) specifies a small
swing of 350mV typical, on a nominal 1.25V common mode
above ground. The common mode voltage has tight limits
vOD
vOH, vOL
to permit large variations in ground between an LVDS driver
and receiver.
50Ω, ±1%
100Ω
–1%
50Ω, ±1%
vOH, vOL
GND
GND
Figure 3b. LVDS Common Mode Measurement
Figure 3a. LVDS Differential Measurement
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vOCM,
∆vOCM
8
Precision Edge®
SY89876L
Micrel, Inc.
INPUT INTERFACE APPLICATIONS
VCC
VCC
VCC
VCC
IN
IN
IN
CML
CML
PECL
/IN
/IN
NC
GND
VT
NC
/IN
VCC
SY89876L
SY89876L
GND
VCC
VCC
VT
VCC
VREF_AC
VREF_AC
SY89876L
GND
NC
Figure 4b. AC-Coupled CML
Input Interface
VCC
VCC
VCC
VCC
IN
PECL
VCC
VCC
HSTL
LVDS
/IN
/IN
Rpd
100Ω
VCC
GND
Figure 4c. DC-Coupled PECL
Input Interface
IN
IN
Rpd
100Ω
GND
VREF_AC
50Ω
0.01µF
Figure 4a. DC-Coupled CML
Input Interface
VT
Rb
0.01µF
/IN
SY89876L
SY89876L
SY89876L
GND
VT
VREF_AC
GND
NC
VT
NC
VREF_AC
NC
VREF_AC
GND
0.01µF
Figure 4d. AC-Coupled PECL
Input Interface
VT
Figure 4e. LVDS
Input Interface
Figure 4f. HSTL
Input Interface
RELATED PRODUCT AND SUPPORT DOCUMENTATION
Part Number
Function
Data Sheet Link
SY89873L
3.3V, 2.5GHz Any Diff. IN-to-LVDS
Programmable Clock Divider/Fanout Buffer
w/ Internal Termination
http://www.micrel.com/product-info/products/sy89873l.shtml
MLF® Application Note
http://www.amkor.com/products/notes_papers/mlf_appnote.pdf
New Products and Applications
http://www.micrel.com/product-info/products/solutions.shtml
HBW Solutions
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Precision Edge®
SY89876L
Micrel, Inc.
16-PIN MicroLeadFrame® (MLF-16)
Package
EP- Exposed Pad
Die
CompSide Island
Heat Dissipation
Heat Dissipation
VEE
Heavy Copper Plane
VEE
Heavy Copper Plane
PCB Thermal Consideration for 16-Pin MLF® Package
(Always solder, or equivalent, the exposed pad to the PCB)
Package Notes:
Note 1.
Note 2.
Package meets Level 2 moisture sensitivity classification, and are shipped in dry-pack form.
Exposed pads must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
http://www.micrel.com
The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2005 Micrel, Incorporated.
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