Writing a UART Device Driver for the Alchemy™ Au1000™ Processor from AMD Application Note Revision: 002 Issue Date: September 2001 © 2002 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. 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Contacts www.amd.com [email protected] Trademarks AMD, the AMD Arrow logo, and combinations thereof, and Au1000, Au1100, Au1500, and Alchemy are trademarks of Advanced Micro Devices, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Writing a UART Device Driver for the Au1000™ Processor Rev. 002 September 2001 Introduction The Au1000™ processor integrates four Universal Asynchronous Receiver/Transmitters, UART. Each of the four UARTs is very similar to the personal computer industry standard NS16550 UART[1]. This document outlines the differences in order to assist the device driver developer. When starting the development of the Au1000 UART device driver, it is best to start with an existing NS16550 driver, which virtually every operating system supports. After reading the remainder of this document, the developer can then decide to make modifications to the existing driver, or change the driver into a UART driver specific to the Au1000 processor. Register Set Differences The Au1000 UART register set is very similar to the NS16550. The differences are depicted in the table below. NS16550 Register Name Au1000™ Processor Offset Register Name Offset RBR 0 (rd) uart_rxdata 0 (0x0000) THR 0 (wr) uart_txdata 1 (0x0004) IER 1 (r/w) uart_inten 2 (0x0008) IIR 2 (rd) uart_intcause 3 (0x000C) FCR 2 (wr) uart_fifoctrl 4 (0x0010) LCR 3 (r/w) uart_linectrl 5 (0x0014) MCR 4 (r/w) uart_mdmctrl 6 (0x0018) LSR 5 (r/w) uart_linestat 7 (0x001C) MSR 6 (r/w) uart_mdmstat 8 (0x0020) SCR 7 (r/w) DLL/DLM 0/1 (DLAB=1) uart_clkdiv 10 (0x0028) uart_enable (0x0100) The register set differences are: • Each Au1000 UART register has a unique address. • Each Au1000 UART is 32-bits wide. The 8-bit value is in the least-significant byte of the register. • The Au1000 processor does not implement the NS16550 scratch register, SCR. Application Note 3 Writing a UART Device Driver for the Au1000™ Processor Rev. 002 September 2001 • The NS16550 baud rate clock divisor registers DLL/DLM are consolidated into a single uart_clkdiv register on the Au1000. • The LCR[DLAB] bit is not implemented (since it is not needed). • The MCR[AFE] bit is not implemented. Programming Considerations The operation of the Au1000 processor UART is very similar to that of the NS16550. The differences are outlined below. • Before the UART can be used, it must be enabled via the uart_enable register. • All register accesses must be 32-bits. Byte-wide accesses to the UART registers do not work. Furthermore, 32-bit register accesses works for both endian modes without the need for byte swapping. • The Au1000 UART baud rate clock is derived from the Au1000 processor PBUS frequency, not the personal computer industry standard 1.3xxMHz frequency used for the NS16550. The baud rate divider programmed into uart_clkdiv must be computed relative to the PBUS frequency of your system. • Only UART4 has the modem control signals available. As with all peripherals integrated into the Au1000 processor, all register accesses should be through the KSEG1 region. This region is un-mapped, and more importantly, non-cached. All non-cached accesses proceed through the write buffer, WB, where write-merging takes place. (Please see Au1000 Processor Data Book[2].) Write buffer write-merging combines successive writes to the same address into a single write. For peripheral register accesses, this is incorrect. For example, if two bytes are written to uart_txdata, only the second byte survives the write-merging stage, so the first byte is lost. As a result, accesses to the UART registers must flush the write buffer (before and/or) after a register write. Flushing the write buffer also guarantees that previous writes have been posted to the peripheral (as opposed to sitting indefinitely in the write buffer until a write buffer flush event occurs). The write buffer is flushed with a SYNC instruction rather than a non-cached read (since a read of a peripheral register can have unintended side-effects). References: [1] National Semiconductor, NS16550 Data Sheet. http://www.national.com/pf/PC/PC16550D.html [2] Au1000™ Processor Data Book. 4 Application Note