TCM29C23, TCM129C23 VARIABLE-FREQUENCY PCM OR DSP INTERFACE SCTS029A – AUGUST 1989 –REVISED JULY 1996 D D D D D D D D Combined ADC, DAC, and Filters Extended Variable Frequency Operation – Master Clock Up to 4.096 MHz – Sample Rates Up to 16 kHz – Passband Up to 6 kHz Reliable Silicon-Gate CMOS Technology Low Power Consumption – Operating Mode . . . 80 mW Typical – Power-Down Mode . . . 5 mW Typical Excellent Power-Supply Rejection Ratio Over Frequency Range of 0 to 50 kHz No External Components Needed for Sample, Hold, and Autozero Functions Precision Internal Voltage References µ-law and A-law Coding DW OR N PACKAGE (TOP VIEW) VBB PWRO + PWRO – GSR PDN CLKSEL DCLKR PCM IN FSR/TSRE DGTL GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC GSX ANLG IN – ANLG IN + ANLG GND SIGX/ASEL TSX/DCLKX PCM OUT FSX/TSXE CLKR/CLKX description The TCM29C23 and TCM129C23 are single-chip PCM codecs (pulse-code-modulated encoders and decoders) and PCM lines filters. These devices provide all the functions required to interface a full-duplex (4-wire) voice telephone circuit with a TDM (time-division-multiplexed) system. Primary applications include digital encryption systems, digital voice-band data storage systems, digital signal processing, and mobile telephones. These devices are designed to perform the transmit encoding (A/D conversion) and receive decoding (D/A conversion) as well as the transmit and receive filtering functions in a pulse-code-modulated system. They are intended to be used at the analog termination of a PCM line or trunk. The TCM29C23 and TCM129C23 provide the band-pass filtering of the analog signals prior to encoding and after decoding. These combination devices perform the encoding and decoding of voice and call progress tones as well as the signaling supervision information. The TCM29C23 is characterized for operation from 0°C to 70°C. The TCM129C23 is characterized for operation from – 40°C to 85°C. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Copyright 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TCM29C23, TCM129C23 VARIABLE-FREQUENCY PCM OR DSP INTERFACE SCTS029A – AUGUST 1989 –REVISED JULY 1996 functional block diagram Transmit Section Autozero 13 ANLG IN + ANLG IN – GSX 17 Filter Sample and Hold and DAC 18 Successive Approximation Comparator PCM OUT 14 TSX/DCLKX 15 SIGX/ASEL 19 Analogto-Digital Control Logic Reference 12 11 Control Logic Filter 4 Gain Set FSX/TSXE CLKR/CLKX Control Section Receive Section GSR Output Register Σ 6 5 CLKSEL PDN Buffer PWRO+ PWRO– 2 3 Reference 20 VCC 2 Digitalto-Analog Control Logic Sample and Hold and DAC 1 10 16 VBB DGTL GND ANLG GND POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 FSR/TSRE 8 Input Register 7 PCM IN DCLKR TCM29C23, TCM129C23 VARIABLE-FREQUENCY PCM OR DSP INTERFACE SCTS029A – AUGUST 1989 –REVISED JULY 1996 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. ANLG GND 16 ANLG IN + 17 I Noninverting analog input to uncommitted transmit operational amplifier. ANLG IN – 18 I Inverting analog input to uncommitted transmit operational amplifier. CLKR 11 I Receive master clock and data clock for the fixed-data-rate mode. Receive master clock only for variable-data-rate mode. CLKR and CLKX are internally connected together. 6 I Clock frequency selection. Input must be connected to VBB, VCC, or ground to reflect the master clock frequency. 11 I Transmit master clock and data clock for the fixed-data-rate mode. Transmit master clock only for variable-data-rate mode. CLKR and CLKX are internally connected. 7 I Selects fixed- or variable-data-rate operation. When connected to VBB, the device operates in the fixed-data-rate mode. When DCLKR is not connected to VBB, the device operates in the variable-data-rate mode and DCLKR becomes the receive data clock, which operates at frequencies from 64 kHz to 4.096 MHz. CLKSEL CLKX DCLKR Analog ground return for all internal voice circuits. Not internally connected to DGTL GND. DGTL GND 10 FSR/TSRE 9 I Frame-synchronization clock input/time-slot enable for receive channel. In the fixed-data-rate mode, FSR distinguishes between signaling and nonsignaling frames by a double- or single-length pulse, respectively. In the variable-data-rate mode, this signal must remain high for the duration of the slot. The receive channel enters the standby state when FSR is TTL low for 300 ms. FSX/TSXE 12 I Frame-synchronization clock input/time-slot enable for the transmit channel. Operates independently of, but in an analogous manner to, FSR/TSRE. The transmit channel enters the standby state when FSX is low for 300 ms. GSR 4 I Input to the gain-setting network on the output power amplifier. Transmission level can be adjusted over a 12-dB range depending upon the voltage at GSR. GSX 19 O Output terminal of internal uncommitted operational amplifier. Internally, this is the voice signal input to the transmit filter. 8 I Receive PCM input. PCM data is clocked in on this pin on eight consecutive negative transition of the receive data clock, which is CLKR in fixed-data-rate timing and DCLKR in variable-data-rate timing. 13 O Transmit PCM output. PCM data is clocked out of this output on eight consecutive positive transition of the transmit data clock, which is CLKX in fixed-data-rate timing and DCLKX in variable-data-rate timing. PDN 5 I Power-down select. This device is inactive with a TTL low-level input to this terminal and active with a TTL high-level input to this terminal. PWRO + 2 O Noninverting output of power amplifier. Can drive transformer hybrids or high-impedance loads directly in either a differential or single-ended configuration. PCM IN PCM OUT PWRO – Digital ground for all internal logic circuits. Not internally connected to ANLG GND. 3 O Inverting output of power amplifier; functionally identical to but complementary to PWRO +. SIGX/ASEL 15 I A-law and µ-law operation select. When connected to VBB, A-law is selected. When connected to VCC or ground, µ-law is selected. TSX/DCLKX 12 I/O Transmit channel time slot strobe (output) or data clock (input) for the transmit channel. In the fixed-data-rate mode, this is an open-drain output to be used as an enable signal for a 3-state output buffer. In the variable-data-rate mode, DCLKX becomes the transmit data clock, which operates at TTL levels from 64 kHz to 2.048 MHz. VBB VCC 16 1 Most negative supply voltage; input is – 5 V ± 5%. Most positive supply voltage; input is 5 V ± 5%. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TCM29C23, TCM129C23 VARIABLE-FREQUENCY PCM OR DSP INTERFACE SCTS029A – AUGUST 1989 –REVISED JULY 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 15 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 15 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 15 V Digital ground voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 15 V Operating free-air temperature range, TA: TCM29C23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to70°C TCM129C23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Voltage values for maximum ratings are with respect to VBB. recommended operating conditions (see Note 2) MIN VCC VBB Supply voltage (see Note 3) Supply voltage NOM 4.75 5 5.25 V –5 – 5.25 V 0 High-level input voltage, all inputs except CLKSEL For 2.048 MHz VBB 0 For 1.544 MHz For 1.536 Mhz RL Load resistance CL Load capacitance TA Operating free free-air air temperature V 2.2 Low-level input voltage, all inputs except CLKSEL CLKSEL input voltage UNIT – 4.75 DGTL GND voltage with respect to ANLG GND VIH VIL MAX VCC – 0.5 10 At GSX At PWRO + and/or PWRO – V 0.8 V VBB + 0.5 0.5 V VCC kΩ Ω 300 At GSX 50 At PWRO + and/or PWRO – TCM29C23 TCM129C23 100 0 70 – 40 85 pF °C NOTES: 2. To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device power-up sequence paragraphs later in this document should be followed. 3. Voltages at analog inputs and outputs, VCC and VBB, are with respect to ANLG GND. All other voltages are referenced to DGTL GND unless otherwise noted. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TCM29C23, TCM129C23 VARIABLE-FREQUENCY PCM OR DSP INTERFACE SCTS029A – AUGUST 1989 –REVISED JULY 1996 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) supply current, fDCLK = 4.096 MHz, outputs not loaded TEST CONDITIONS TCM29C23 MIN TYP† MAX 7 9 8 13 Standby FSX, or FSR at VIL after 300 ms 0.5 1 0.7 1.5 Power down PDN at VIL after 10 µs 0.3 0.8 0.4 1 –7 –9 –8 – 13 PARAMETER Operating ICC Supply S l currentt from f VCC Operating IBB Supply S l currentt from f VBB Standby FSX or FSR at VIL after 300 ms – 0.5 –1 – 0.7 – 1.5 Power down PDN at VIL after 10 µs – 0.3 – 0.8 – 0.4 –1 70 90 80 130 5 10 7 15 3 8 4 10 Operating PD Power dissipation TCM129C23 MIN TYP† MAX Standby FSX or FSR at VIL after 300 ms PDN at VIL after 10 µs † All typical values are at VBB = – 5 V, VCC = 5 V, and TA = 25°C. Power down UNIT mA mA mW digital interface TEST CONDITIONS PARAMETER PCM OUT 2.4 TMC129C23 TYP† MAX MIN 2.4 UNIT VOH High-level output voltage VOL Low-level output voltage at PCM OUT, TSX, SIG IOL = 3.2 mA 0.4 0.5 V IIH IIL High-level input current, any digital input VI = 2.2 V to VCC VI = 0 to 0.8 V 10 12 µA 10 12 µA Ci Input capacitance 10 pF Low-level input current, any digital input IOH = –9.6 mA TMC29C23 TYP† MAX MIN 5 Co Output capacitance † All typical values are at VBB = – 5 V, VCC = 5 V, and TA = 25°C. 10 V 5 5 5 pF transmit amplifier input PARAMETER TEST CONDITIONS MIN TYP† Input current at ANLG IN +, ANLG IN – VI = – 2.17 V to 2.17 V Input offset voltage at ANLG IN +, ANLG IN – Common-mode rejection at ANLG IN +, ANLG IN – MAX ± 200 nA ± 25 mV 55 Open-loop voltage amplification at GSX UNIT dB 5000 Open-loop unity-gain bandwidth at GSX 1 Input resistance at ANLG IN +, ANLG IN – † All typical values are at VBB = – 5 V, VCC = 5 V, and TA = 25°C. MHz 10 MΩ receive filter output PARAMETER TEST CONDITIONS Output offset voltage at PWRO +, PWRO – (single ended) Relative to ANLG GND Output resistance at PWRO +, PWRO – † All typical values are at VBB = – 5 V, VCC = 5 V, and TA = 25°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN TYP† MAX UNIT 80 mV 1 Ω 5 TCM29C23, TCM129C23 VARIABLE-FREQUENCY PCM OR DSP INTERFACE SCTS029A – AUGUST 1989 –REVISED JULY 1996 gain and dynamic range, VCC = 5 V, VBB = –5 V, TA = 25°C (unless otherwise noted) (see Notes 4, 5, and 6) PARAMETER TEST CONDITIONS Encoder milliwatt response (transmit gain tolerance) Signal input = 1.068 Vrms for A-law Encoder milliwatt response (nominal supplies and temperature) TA = 0°C to 70°C, Supply voltages = 5 V ± 5% Digital milliwatt response (receive tolerance gain) relative to zero-transmission level point Signal input per CCITT G.711, Output signal = 1 kHz Digital milliwatt response variation with temperature and supplies TA = 0°C to 70°C, Supply voltages = 5 V ± 5% µ-law Zero transmission level point, point transmit channel (0 dBm0) Zero-transmission-level A-law µ-law A-law µ-law Zero transmission level point, Zero-transmission-level point receive channel (0 dBm0) MIN Signal input = 1.064 Vrms for µ-law A-law µ-law A-law TYP MAX UNIT ± 0.5 0 5 ±1 dBm0 ± 0.15 ± 0.5 ±1 ± 0.15 dB dBm0 dB 2.76 RL = 600 Ω 2.79 dBm 1 RL = 900 Ω 1.03 5.76 RL = 600 Ω 5.79 dBm 4 RL = 900 Ω 4.03 NOTES: 4. Unless otherwise noted, the analog input is a 0-dBm0, 1020-Hz sine wave, where 0 dBm0 is defined as the zero-reference point of the channel under test. This corresponds to an analog signal input of 1.064 Vrms or an output of 1.503 Vrms. 5. The input amplifier is set for noninverting unity gain. The digital input is a PCM bit stream generated by passing a 0-dBm0, 1020-Hz sine wave through an ideal encoder. 6. Receive output is measured single ended in the maximum gain configuration. To set the output amplifier for maximum gain, GSR is connected to PWRO – and the output is taken at PWRO+. All output levels are (sin x)/x corrected. gain tracking over recommended ranges of supply voltage and operating free-air temperature, reference level = –10 dBm0 PARAMETER TEST CONDITIONS Transmit gain gain-tracking tracking error error, sinusoidal input Receive gain gain-tracking tracking error error, sinusoidal input MIN MAX 3 ≥ input level ≥ – 40 dBm0 ± 0.5 – 40 > input level ≥ – 50 dBm0 ± 1.5 3 ≥ input level ≥ – 40 dBm0 ± 0.5 – 40 > input level ≥ – 50 dBm0 ± 1.5 UNIT dB dB noise over recommended ranges of supply voltage and operating free-air temperature range PARAMETER TEST CONDITIONS MIN MAX UNIT Transmit noise, C-message weighted ANLG IN+ = ANLG GND, ANLG IN – = GSX 18 dBrnC0 Transmit noise, psophometrically weighted ANLG IN+ = ANLG GND, ANLG IN – = GSX – 72 dBm0p Receive noise, C-message-weighted quiet code PCM IN = 11111111 (µ-law), Measured at PWRO + PCM IN = 10101010 (A-law), 11 dBrnC0 Receive noise, psophometrically weighted PCM = lowest positive decode level – 79 dBm0p 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TCM29C23, TCM129C23 VARIABLE-FREQUENCY PCM OR DSP INTERFACE SCTS029A – AUGUST 1989 –REVISED JULY 1996 power-supply rejection and crosstalk attenuation over recommended ranges of supply voltage and operating free-air temperature PARAMETER VCC supply-voltage ratio,, y g rejection j transmit channel VBB supply-voltage y g rejection j ratio,, transmit channel y g rejection j VCC supply-voltage ratio,, receive channel (single ended) VBB supply-voltage ratio,, receive y g rejection j channel (single ended) TEST CONDITIONS 0 ≤ f < 30 kHz 30 ≤ f < 50 kHz 0 ≤ f < 30 kHz 30 ≤ f < 50 kHz 0 ≤ f < 30 kHz 30 ≤ f < 50 kHz 0 ≤ f < 30 kHz 30 ≤ f < 50 kHz MIN TYP† Idle channel, Supply signal = 200 mV peak to peak, peak f measured at PCM OUT – 30 Idle channel, Supply signal = 200 mV peak to peak, peak f measured at PCM OUT – 30 Idle channel, Supply signal = 200 mV peak to peak, peak f measured at PWRO + – 20 Idle channel, Supply signal = 200 mV peak to peak, peak Narrow-band, f measured at PWRO + – 20 MAX UNIT dB – 45 dB – 55 dB – 45 dB – 45 Crosstalk attenuation, transmit to receive (single ended) ANLG IN+ = 0 dBm0, f = 1.02 kHz, Unity gain, PCM IN = lowest decode level, Measured at PWRO + 68 dB Crosstalk attenuation, receive to transmit (single ended) PCM IN = 0 dBm0, Measured at PCM OUT 68 dB f = 1.02 kHz, † All typical values are at VBB = – 5 V, VCC = 5 V, and TA = 25°C. distortion over recommended ranges of supply voltage and operating free-air temperature PARAMETER TEST CONDITIONS Transmit T it signal-to-distortion i l t di t ti ratio, ti sinusoidal i id l iinputt (CCITT G.712 G 712 – Method 2) Receive R i signal-to-distortion i l t di t ti ratio, ti sinusoidal i id l iinputt (CCITT G.712 G 712 – Method 2) Transmit single-frequency distortion products MIN 0 ≥ ANLG IN+ ≥ – 30 dBm0 33 – 30 > ANLG IN+ ≥ – 40 dBm0 28 – 40 > ANLG IN+ ≥ – 45 dBm0 23 0 ≥ ANLG IN+ ≥ – 30 dBm0 33 – 30 > ANLG IN+ ≥ – 40 dBm0 28 – 40 > ANLG IN+ ≥ – 45 dBm0 23 TYP† MAX UNIT dB dB AT&T Advisory #64 (3.8), Input signal = 0 dBm0 – 40 dBm0 Receive single-frequency distortion products AT&T Advisory #64 (3.8), † All typical values are at VBB = – 5 V, VCC = 5 V, and TA = 25°C. Input signal = 0 dBm0 – 46 dBm0 transmit filter transfer over recommended ranges of supply voltage and operating free-air temperature, fDCLK = 4.096 MHz, FSX/FSR = 16 kHz (see Figure 1) PARAMETER TEST CONDITIONS 50 Hz 200 Hz Gain relative to gain at 1.02 kHz In ut am Input amplifier lifier set for unity gain, Noninverting maximum gain output, Input signal at ANLG IN + is 0 dBm0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN MAX – 10 0 –1 0.5 – 0.5 0.5 6.5 kHz –4 0.3 6.8 kHz –6 300 Hz to 6 kHz UNIT dB 0 8 kHz – 12 9 kHz and above – 30 7 TCM29C23, TCM129C23 VARIABLE-FREQUENCY PCM OR DSP INTERFACE SCTS029A – AUGUST 1989 –REVISED JULY 1996 receive filter transfer over recommended ranges of supply voltage and operating free-air temperature (see Figure 2) PARAMETER TEST CONDITIONS Below 200 Hz 200 Hz Input signal at PCM IN is 0 dBm0 MAX –2 0.5 –1 0.5 – 0.5 0.5 6.6 kHz –4 0.3 6.8 kHz –6 300 Hz to 6 kHz Gain relative to gain at 1.02 kHz MIN UNIT dB 0 8 kHz –12 9.2 kHz and above – 30 timing requirements clock timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figure 3) TYP† MIN tc(CLK) tr, tf Clock period, for CLKX, CLKR (2.048-MHz systems) tw(CLK) tw(DCLK) Pulse duration for CLKX and CLKR (see Note 7) MAX 244 Rise and fall times for CLKX and CLKR ns 5 20 110 Pulse duration, DCLK (fDCLK = 64 kHz to 2.048 MHz) (see Note 7) Clock duty cycle, [tw(CLK)/tc(CLK)] for CLKX and CLKR UNIT ns ns 110 ns 45% 50% 55% † All typical values are at VBB = – 5 V, VCC = 5 V, and TA = 25°C. NOTE 7: FSX CLK must be phase locked with CLKX. FSR CLK must be phase locked with CLKR. transmit timing requirements over recommended ranges of supply voltage and operating free-air temperature, fixed-data-rate mode (see Figure 3) PARAMETER td(FSX) MIN Frame-sync delay time 60 MAX UNIT tc(CLK) – 60 ns receive timing requirements over recommended ranges of supply voltages and operating free-air temperature, fixed-data-rate mode (see Figure 4) PARAMETER td(FSR) MIN Frame-sync delay time 60 MAX UNIT tc(CLK)– 60 ns transmit timing requirements over recommended ranges of supply voltage and operating free-air temperature, variable-data-rate mode (see Figure 5) PARAMETER MIN td(TSDX) td(FSX) Time-slot delay time from DCLKX Frame-sync delay time 60 tc(DCLKX) Clock period for DCLKX 244 8 60 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT td(DCLKX)– 60 tc(CLK)– 60 ns 15620 ns ns TCM29C23, TCM129C23 VARIABLE-FREQUENCY PCM OR DSP INTERFACE SCTS029A – AUGUST 1989 –REVISED JULY 1996 receive timing requirements over recommended ranges of supply voltages and operating free-air temperature, variable-data-rate mode (see Figure 6) PARAMETER MIN MAX UNIT td(DCLKR)–140 tc(CLK)– 60 ns td(TSDR) td(FSR) Time-slot delay time from DCLKR 60 Frame-sync delay time 60 tsu(PCM IN) th(PCM IN) Setup time before bit 7 falling edge 10 ns Hold time after bit 8 falling edge 60 ns tc(DCLKR) tSER Data clock frequency 244 Time-slot end receive time 15620 ns ns 0 ns switching characteristics propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode (see Figure 3) PARAMETER TEST CONDITIONS MIN MAX UNIT tpd1 From rising edge of transmit clock to bit 1 data valid at PCM OUT (data enable time on time-slot entry) (see Note 8) CL = 0 to 100 pF 0 90 ns tpd2 From rising edge of transmit clock bit n to bit data valid at PCM OUT (data valid time) CL = 0 to 100 pF 0 90 ns tpd3 From falling edge of transmit clock bit 8 to bit 8 Hi-Z at PCM OUT (data float time on time-slot exit) (see Note 8) CL = 0 60 215 ns tpd4 From rising edge of transmit clock bit 1 to TSX active (low) (time slot enable time) CL = 0 to 100 pF 0 90 ns tpd5 From falling edge of transmit clock bit 8 to TSX inactive (high) (time-slot disable time) (see Note 8) CL = 0 60 190 ns NOTE 8: Timing parameters tpd1, tpd3, and tpd5 are referenced to the high-impedance state. propagation delay times over recommended ranges of operating conditions, variable-data-rate mode (see Note 9 and Figure 5) PARAMETER TEST CONDITIONS tpd7 tpd8 Data delay time from DCLKX tpd9 tpd10 Data delay from time-slot disable to PCM OUT Data delay time from FSX Data delay from time-slot enable to PCM OUT CL = 0 to 100 pF td(TSDX) = 80 ns NOTE 9: Timing parameters tpd8 and tpd9 are referenced to the high-impedance state. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN MAX 0 90 UNIT ns 0 50 ns 0 80 ns 0 90 ns 9 TCM29C23, TCM129C23 VARIABLE-FREQUENCY PCM OR DSP INTERFACE SCTS029A – AUGUST 1989 –REVISED JULY 1996 PARAMETER MEASUREMENT INFORMATION CLK, CLKR, and CLKX selection requirements for DSP-based applications CLK, CLKR, and CLKX must be selected as follows: CLKSEL PIN CLK, CLKR, CLKX (BETWEEN 1 MHz to 3 MHz) –5 V = (256) × (frame-sync frequency) 0V = (193) × (frame-sync frequency) 5V = (192) × (frame-sync frequency) e.g., for frame-sync frequency = 16 kHz CLKSEL PIN 10 CLK, CLKR, CLKX (BETWEEN 1 MHz to 3 MHz) –5 V = 4.096 MHz 0V = 3.088 MHz 5V = 3.072 MHz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TCM29C23, TCM129C23 VARIABLE-FREQUENCY PCM OR DSP INTERFACE SCTS029A – AUGUST 1989 –REVISED JULY 1996 0.5 dB 200 Hz 0 dB 50 Hz 0.5 dB 6000 Hz 0.5 dB 300 Hz 0 0 – 1 dB 200 Hz – 0.5 dB 300 Hz – 0.5 dB 6000 Hz –5 Gain Relative to Gain at 1 kHz – dB 0 dB 6800 Hz Expanded Scale PARAMETER MEASUREMENT INFORMATION –5 – 1 dB 6800 Hz 0 dB 50 Hz 0 0 – 10 – 10 – 10 dB 50 Hz – 20 – 20 – 30 – 30 – 30 dB 9000 Hz – 40 – 40 – 50 – 50 – 60 10 50 100 1k – 60 10 k f – Frequency – Hz NOTE A: CLKR/CLKX = 4.096 MHz Figure 1. Transfer Characteristics of the Transmit Filter POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TCM29C23, TCM129C23 VARIABLE-FREQUENCY PCM OR DSP INTERFACE SCTS029A – AUGUST 1989 –REVISED JULY 1996 PARAMETER MEASUREMENT INFORMATION 0 dB 6800 Hz 0.3 dB 6800 Hz 0.5 dB 200 Hz 0.5 dB 300 Hz – 0.5 dB 6000 Hz 0 0 – 1 dB 200 Hz – 0.5 dB 6000 Hz – 0.5 dB 300 Hz – 4 dB 6600 Hz Gain Relative to Gain at 1 kHz – dB –5 –5 – 6 dB 6800 Hz 0 0 – 10 – 10 – 20 – 20 – 30 – 30 – 40 – 40 – 50 100 1k f – Frequency – Hz NOTE A: CLKR/CLKX = 4.096 MHz Figure 2. Transfer Characteristics of the Receive Filter 12 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 – 50 10 k Expanded Scale 5 TCM29C23, TCM129C23 VARIABLE-FREQUENCY PCM OR DSP INTERFACE SCTS029A – AUGUST 1989 –REVISED JULY 1996 PARAMETER MEASUREMENT INFORMATION Time-Slot 1 CLKX 1 2 td(FSX) 3 4 tf tw(CLK) tr td(FSX) FSX Input (nonsignaling frames) 5 6 7 8 tc(CLK) Time-Slot N 1 CLKX 2 tpd1 3 4 5 6 7 8 tpd3 tpd2 Bit 1† PCM OUT Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 8† Bit 7 tpd4 tpd5 TSX Output † Bit 1 = MSB = sign bit and locked in first on PCM IN or clocked out first on PCM OUT. Bit 8 = LSB = least significant bit and is clocked in last on PCM IN or is clocked out last on PCM OUT. NOTE A: Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V if the high level is indicated and 0.8 V if the low level is indicated. Figure 3. Transmit Timing (Fixed-Data Rate) Time-Slot 1 CLKR 1 2 td(FSR) 3 4 td(FSR) tr 5 tf 6 7 8 tw(CLK) tc(CLK) FSR Input (nonsignaling frames) Time-Slot N CLK 1 tsu(PCM IN) 2 3 4 5 6 7 8 th(PCM IN) PCM IN Bit 1† Valid Bit 2 Valid Bit 3 Valid Bit 4 Valid Bit 5 Valid Bit 6 Valid Bit 7 Valid Bit 8† Valid † Bit 1 = MSB = sign bit and locked in first on PCM IN or clocked out first on PCM OUT. Bit 8 = LSB = least significant bit and is clocked in last on PCM IN or is clocked out last on PCM OUT. NOTE A: Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V if the high level is indicated and 0.8 V if the low level is indicated. Figure 4. Receive Timing (Fixed-Data Rate) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TCM29C23, TCM129C23 VARIABLE-FREQUENCY PCM OR DSP INTERFACE SCTS029A – AUGUST 1989 –REVISED JULY 1996 PARAMETER MEASUREMENT INFORMATION Time Slot FSX td(TSDX) 1 DCLKX 2 3 4 5 6 7 8 td(FSX) CLKX tpd8 tpd10 Bit 1† PCM OUT tpd9 tpd7 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 8† Bit 7 † Bit 1 = MSB = sign bit and locked in first on the PCM IN or clocked out first on PCM OUT. Bit 8 = LSB = least significant bit and is clocked in last on PCM IN or is clocked out last on PCM OUT. NOTE A: IAll timing parameters referenced to VIH and VIL except tpd7 and tpd8, which reference the high-impedance state. Figure 5. Transmit Timing (Variable-Data-Rate) FSR td(TSDR) 1 DCLKR 2 3 4 5 6 7 8 t(SER) td(FSR) CLKR tsu(PCM IN) PCM IN th(PCM IN) Don’t Care Bit 1† Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8† † Bit 1 = MSB = sign bit and locked in first on the PCM IN or clocked out first on PCM OUT. Bit 8 = LSB = least significant bit and is clocked in last on PCM IN or is clocked out last on PCM OUT. NOTE A: All timing parameters referenced to VIH and VIL except tpd7 and tpd8, which reference the high-impedance state. Figure 6. Receive Timing (Variable-Data-Rate) 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TCM29C23, TCM129C23 VARIABLE-FREQUENCY PCM OR DSP INTERFACE SCTS029A – AUGUST 1989 –REVISED JULY 1996 PRINCIPLES OF OPERATION system reliability and design considerations TCM29C23, TCM129C23 system reliability and design considerations are described in the following paragraphs. latch-up Latch-up is possible in all CMOS devices. It is caused by the firing of a parasitic SCR that is present due to the inherent nature of CMOS. When a latch-up occurs, the device draws excessive amounts of current and will continue to draw heavy current until power is removed. Latch-up can result in permanent damage to the device if supply current to the device is not limited. Even though the TCM29C23 and TCM129C23 are heavily protected against latch-up, it is still possible to cause latch-up under certain conditions in which excess current is forced into or out of one or more terminals. Latch-up can occur when the positive supply voltage drops momentarily below ground, when the negative supply voltage rises momentarily above ground, or possibly if a signal is applied to a terminal after power has been applied but before the ground is connected. This can happen if the device is hot-inserted into a card with the power applied, or if the device is mounted on a card that has an edge connector and the card is hot-inserted into a system with the power on. To help ensure that latch-up does not occur, it is considered good design practice to connect a reverse-biased Schottky diode (with a forward voltage drop of less than or equal to 0.4 V – 1N5711 or equivalent) between the power supply and GND (see Figure 7). If it is possible that a TCM29C23- or TCM129C23-equipped card that has an edge connector could be hot-inserted into a powered-up system, it is also important to ensure that the ground edge connector traces are longer than the power and signal traces so that the card ground is always the first to make contact. device power-up sequence Latch-up can also occur if a signal source is connected without the device being properly grounded. A signal applied to one terminal could then find a ground through another signal terminal on the device. To ensure proper operation of the device and as a safeguard against this sort of latch-up, it is recommended that the following power-up sequence always be used: 1. Ensure that no signals are applied to the device before the power-up sequence is complete. 2. Connect GND. 3. Apply VBB (most negative voltage). 4. Apply VCC (most positive voltage). 5. Force a power down condition in the device. 6. Connect clocks. 7. Release the power down condition. 8. Apply FS synchronization pulses. 9. Apply the signal inputs. When powering down the device, this procedure should be followed in the reverse order. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TCM29C23, TCM129C23 VARIABLE-FREQUENCY PCM OR DSP INTERFACE SCTS029A – AUGUST 1989 –REVISED JULY 1996 PRINCIPLES OF OPERATION VCC DGND VBB Figure 7. Latch-Up Protection Diode Connection internal sequencing On the transmit channel, digital outputs PCM OUT and TSX are held in the high-impedance state for approximately four frames (500 µs) after power up or application of VBB or VCC. After this delay, PCM OUT, TSX, and signaling are functional and occur in the proper time slot. The analog circuits on the transmit side require approximately 60 ms to reach their equilibrium value due to the autozero circuit settling time. Thus valid digital information, such as on/off hook detection, is available almost immediately while analog information is available after some delay. To further enhance system reliability, PCM OUT and TSX are placed in the high-impedance state approximately 20 µs after an interruption of CLKX. power-down and standby operations To minimize power consumption, a power-down mode and three standby modes are provided. For power down, an external low signal is applied to PDN. In the absence of a signal, PDN is interally pulled up to a high logic level and the device remains active. In the power-down mode, the average power consumption is reduced to 5 mW. Three standby modes give the user the options of placing the entire device on standby, placing only the transmit channel on standby, or placing only the receive channel on standby. to place the entire device on standby, both FSX and FSR are held low. For transmit-only operation (receive channel on standby), FSX is high and FSR is held low. For receive-only operation (transmit section on standby), FSR is high and FSX is held low. When the entire device is in standby mode, power consumption is reduced to an average of 3 mW. See Table 1 for power-down and standby procedures. Table 1. Power-Down and Standby Procedures DEVICE STATUS Power down Entire device on standby Only transmit on standby Only receive on standby 16 PROCEDURE PDN low FSX and FSR are low FSX is low, FSR is high FSR is low, FSX is high TYPICAL POWER CONSUMPTION DIGITAL OUTPUT STATUS 3 mW TSX and PCM OUT are in the high-impedance state; SIGR goes to low within 10 µs. 3 mW TSX and PCM OUT are in the high-impedance state; SIGR goes to low within 300 ms. 40 mW TSX and PCM OUT are placed in the high-impedance state within 300 ms. 30 mW SIGR is placed in the high-impedance state within 300 ms. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TCM29C23, TCM129C23 VARIABLE-FREQUENCY PCM OR DSP INTERFACE SCTS029A – AUGUST 1989 –REVISED JULY 1996 PRINCIPLES OF OPERATION fixed-data-rate timing Fixed-data-rate timing is selected by connecting DCLKR to VBB. It uses master clocks CLKX and CLKR, framesynchronizer clocks FSX and FSR, and output TSX. FSX and FSR are inputs that set the sampling frequency. Data is transmitted on PCM OUT on the first eight positive transitions of CLKX following the rising edge of FSX. Data is received on PCM IN on the first eight falling edges of CLKR following FSX. A digital-to-analog (D/A) conversion is performed on the received digital word and the resulting analog sample is held on an internal sample-and-hold capacitor until transferred to the receive filter. variable-data-rate timing Variable-data-rate timing is selected by connecting DCLKR to the bit clock for the receive PCM highway rather than to VBB. It uses master clocks CLKX and CLKR, bit clocks DCLKX and DCLKR, and frame-synchronization clocks FSX and FSR. Variable-data-rate timing allows for a flexible data frequency. The frequency of the bit clocks can be varied from 64 kHz to 4.096 MHz. The bit clocks must be asynchronous. When the FSX/TSXE input is high, PCM data is transmitted from PCM OUT onto the highway on the next eight consecutive positive transitions of DCLKX. Similarly, while the FSR/TSRE input is high, the PCM word is received from the highway by PCM IN on the next eight consecutive negative transitions of DCLKR. The transmitted PCM word will be repeated in all remaining time slots in the frame as long as DCLKX is pulsed and FSX is held high. This feature, which allows the PCM word to be transmitted to the PCM highway more than once per frame if desired, is available only with variable-data-rate timing. Signaling is allowed only in the fixed-data-rate mode because the variable-data-rate mode provides no means with which to specify a signaling frame. asynchronous operation In order to avoid crosstalk problems associated with special interrupt circuits, the design includes separate digital-to-analog converters and voltage references on the transmit and receive sides to allow completely independent operation of the two channels. In either timing mode, the master clock, data clock, and time-slot strobe must be synchronized at the beginning of each frame. Specifically, in the variable-rate mode, the falling edge of CLKX must occur within td(FSX) ns after the rise of FSX and the falling edge of DCLKX must occur within tTSDX ns after the rise of FSX. CLKX and DCLKX are synchronized once per frame but may be of different frequencies. The receive channel operates in a similar manner and is completely independent of the transmit timing (see Figure 6). This approach requires the provision of two separate master clocks but avoids the use of a synchronizer, which can cause intermittent data conversion errors. precision voltage references Voltage references that determine the gain and dynamic range characteristics of the device are generated internally. No external components are required to provide the voltage references. A difference in subsurface charge density between two suitably implanted MOS devices is used to derive a temperature- and bias-stable reference voltage, which are calibrated during the manufacturing process. Separate references are supplied to the transmit and receive sections, and each is calibrated independently. Each reference value is then further trimmed in the gain-setting operational amplifiers to a final precision value. Manufacturing tolerances of typically ± 0.04 dB in absolute gain can be achieved for each half channel, providing the user a significant margin to compensate for error in other system components. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TCM29C23, TCM129C23 VARIABLE-FREQUENCY PCM OR DSP INTERFACE SCTS029A – AUGUST 1989 –REVISED JULY 1996 PRINCIPLES OF OPERATION conversion laws The TCM29C23 and TCM129C23 provide pin-selectable A-law or µ-law operation as specified by the CCITT G.711 recommendation. A-law operation is selected when ASEL is connected to VBB. Signaling is not allowed during A-law operation. µ-law operation is selected by connecting ASEL to VCC or GND. transmit operation transmit filter The input section provides gain adjustment in the pass band by means of an on-chip uncommitted operational amplifier. The load impedance to ground (ANLG GND) at the amplifier output (GSX) must be greater than 10 kΩ in parallel with less than 50 pF. The input signal on ANLG IN + can be either ac or dc coupled. The input operational amplifier can also be used in the inverting mode or differential amplifier mode. A low-pass antialiasing section is included on the device. This section provides 35-dB attenuation at the sampling frequency. No external components are required to provide the necessary antialiasing function for the switched-capacitor section of the transmit filter. encoding The encoder internally samples the output of the transmit filter and holds each sample on an internal sampleand-hold capacitor. The encoder performs an analog-to-digital conversion on a switched-capacitor array. Digital data representing the sample is transmitted on the first eight data clock bits of the next frame. The autozero circuit corrects for dc offset on the input signal to the encoder using the sign bit averaging technique. The sign bit from the encoder output is long-term averaged and subtracted from the input to the encoder. All dc offset is removed from the encoder input waveform. receive operation decoding The serial PCM word is received at PCM IN on the first eight data clock bits of the frame. Digital-to-analog conversion is performed, and the corresponding analog sample is held on an internal sample-and-hold capacitor. This sample is transferred to the receive filter. receive filter The receive section of the filter provides pass-band flatness and stop-band rejection that fulfills both the AT&T D3/D4 specification and CCITT recommendation G.712. The filter contains the required compensation for the (sin x)/x response of such decoders. receive output power amplifiers A balanced output amplifier is provided to allow maximum flexibility in output configuration. Either of the two outputs can be used single ended (i.e., referenced to ANLG GND) to drive single-ended loads. Alternatively, the differential output directly drives a bridged load. The output stage is capable of driving loads as low as 300 Ω single ended to a level of 12 dBm or 600 Ω differentially to a level of 15 dBm. The receive channel transmission level may be adjusted between specified limits by manipulating of the GSR input. GSR is internally connected to an analog gain-setting network. When GSR is connected to PWRO +, the level is minimum. The output transmission level between 0 and – 12 dB as GSR is adjusted (with an adjustable resistor) between PWRO + and PWRO –. Transmission levels are specified relative to the receive channel output under digital milliwatt conditions (i.e., when the digital input at PCM IN is the eight-code sequence specified in CCITT recommendation G.711). 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TCM29C23, TCM129C23 VARIABLE-FREQUENCY PCM OR DSP INTERFACE SCTS029A – AUGUST 1989 –REVISED JULY 1996 APPLICATION INFORMATION output gain-set design considerations (see Figure 7) PWRO+ and PWRO – are low-impedance complementary outputs. The voltages at the nodes are: VO + at PWRO + VO – at PWRO – VO = VO + – VO – (total differential response) R1 and R2 are a gain-setting resistor network with the center tap to the GSR input. A value greater than 10 kΩ and less than 100 kΩ for R1 + R2 is recommended because of the following: The parallel combination of R1 + R2 and RL sets the total loading. The total capacitance at the GSR input and the parallel combination of R1 and R2 define a time constant that has to be minimized to avoid inaccuracies. VAD represents the maximum available digital milliwatt output response (VA = 3.06 V rms). VOD = A • VAD 1 + (R1/R2) where A = 4 + (R1/R2) 2 VO + R1 4 VOD RL PWRO+ GSR TCM19C23 TCM129C23 R2 3 PWRO– PCM IN 8 VO – Digital Milliwatt Sequence Per CCITT G. 711 Figure 8. Gain-Setting Configuration POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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