DATA SHEET MOS INTEGRATED CIRCUIT µPD4382323, 4382363 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION DOUBLE CYCLE DESELECT Description The µPD4382323 is a 262,144-word by 32-bit and the µPD4382363 is a 262,144-word by 36-bit synchronous static RAM fabricated with advanced CMOS technology using N-channel four-transistor memory cell. The µPD4382323 and µPD4382363 integrates unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input (CLK). The µPD4382323 and µPD4382363 are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory. ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation. The µPD4382323 and µPD4382363 are packaged in 100-pin plastic LQFP with a 1.4 mm package thickness for high density and low capacitive loading. Features • 3.3 V power supply • Synchronous operation • Internally self-timed write control • Burst read / write : Interleaved burst and linear burst sequence • Fully registered inputs and outputs for pipelined operation • Double-Cycle deselect timing • All registers triggered off positive clock edge • 3.3 V LVTTL Compatible : All inputs and outputs • Fast clock access time : 3.8 ns (150 MHz), 4.0 ns (133 MHz) • Asynchronous output enable : /G • Burst sequence selectable : MODE • Sleep mode : ZZ (ZZ = Open or Low : Normal operation) • Separate byte write enable : /BW1 - /BW4, /BWE Global write enable : /GW • Three chip enables for easy depth expansion • Common I/O using three state outputs The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M15393EJ1V0DS00 (1st edition) Date Published February 2001 NS CP(K) Printed in Japan © 2001 µPD4382323, 4382363 Ordering Information Part number Access Clock Core Supply I/O Time Frequency Voltage Interface ns MHz V V µPD4382323GF-A67 3.8 150 3.3 ± 0.165 3.3 µPD4382323GF-A75 4.0 133 µPD4382363GF-A67 3.8 150 µPD4382363GF-A75 4.0 133 2 LVTTL Data Sheet M15393EJ1V0DS Package 100-PIN PLASTIC LQFP (14 x 20) µPD4382323, 4382363 Pin Configuration (Marking Side) /××× indicates active low signal. 100-PIN PLASTIC LQFP (14 x 20) A9 A8 /ADV /AP /AC /G /BWE /GW CLK VSS VDD /CE2 /BW1 /BW2 /BW3 /BW4 CE2 /CE A7 A6 [µPD4382323GF, µPD4382363GF] 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 I/OP3, NC 1 80 I/OP2, NC I/O17 2 79 I/O16 I/O18 3 78 I/O15 VDDQ 4 77 VDDQ VSSQ 5 76 VSSQ I/O19 6 75 I/O14 I/O20 7 74 I/O13 I/O21 8 73 I/O12 I/O22 9 72 I/O11 VSSQ 10 71 VSSQ VDDQ 11 70 VDDQ I/O23 12 69 I/O10 I/O24 13 68 I/O9 NC 14 67 VSS VDD 15 66 NC NC 16 65 VDD VSS 17 64 ZZ I/O25 18 63 I/O8 I/O26 19 62 I/O7 VDDQ 20 61 VDDQ VSSQ 21 60 VSSQ I/O27 22 59 I/O6 I/O28 23 58 I/O5 I/O29 24 57 I/O4 I/O30 25 56 I/O3 VSSQ 26 55 VSSQ VDDQ 27 54 VDDQ I/O31 28 53 I/O2 I/O32 29 52 I/O1 I/OP4, NC 30 51 I/OP1, NC A16 A15 A14 A13 A12 A11 A10 A17 NC VDD VSS NC NC A0 A1 A2 A3 A4 A5 MODE 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Remark Refer to Package Drawing for 1-pin index mark. Data Sheet M15393EJ1V0DS 3 µPD4382323, 4382363 Pin Identification Symbol Pin No. Description A0 - A17 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 43 Synchronous Address Input I/O1 - I/O32 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, Synchronous Data In, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, Synchronous / Asynchronous Data Out 24, 25, 28, 29 I/OP1, NC Note 51 Synchronous Data In (Parity), I/OP2, NC Note 80 Synchronous / Asynchronous Data Out (Parity) I/OP3, NC Note 1 I/OP4, NC Note 30 /ADV 83 Synchronous Burst Address Advance Input /AP 84 Synchronous Address Status Processor Input /AC 85 Synchronous Address Status Controller Input /CE, CE2, /CE2 98, 97, 92 Synchronous Chip Enable Input /BWE1 - /BWE4, /BWE 93, 94, 95, 96, 87 Synchronous Byte Write Enable Input /GW 88 Synchronous Global Write Input /G 86 Asynchronous Output Enable Input CLK 89 Clock Input MODE 31 Asynchronous Burst Sequence Select Input Do not change state during normal operation ZZ 64 Asynchronous Power Down State Input VDD 15, 41, 65, 91 Power Supply VSS 17, 40, 67, 90 Ground VDDQ 4, 11, 20, 27, 54, 61, 70, 77 Output Buffer Power Supply VSSQ 5, 10, 21, 26, 55, 60, 71, 76 Output Buffer Ground NC 14, 16, 38, 39, 42, 66 No Connection Note NC (No Connection) is used in the µPD4382323GF. I/OP1 - I/OP4 is used in the µPD4382363GF. 4 Data Sheet M15393EJ1V0DS µPD4382323, 4382363 Block Diagram 18 Address Registers A0 - A17 MODE /ADV CLK 16 18 A0, A1 A1’ Binary Q1 Counter and Logic A0’ CLR Q0 /AC /AP 8/9 Byte 1 Write Register /BW1 /BW2 Byte 2 Write Register /BW3 Byte 3 Write Register /BW4 /BWE Byte 4 Write Register Row and Column Decoders 8/9 8/9 8/9 Byte 1 Write Driver Byte 2 Write Driver Byte 3 Write Driver Byte 4 Write Driver 32/36 /GW Memory Matrix 1,024 rows 256 × 32 columns (8,388,608 bits) 256 × 36 columns (9,437,184 bits) 32/36 Output Registers Output Buffers Enable Register /CE CE2 /CE2 /G 4 Input Registers 32/36 I/O1 - I/O32 I/OP1 - I/OP4 Power Down Control ZZ Burst Sequence Interleaved Burst Sequence Table (MODE = Open or VDD) External Address A17 - A2, A1, A0 1st Burst Address A17 - A2, A1, /A0 2nd Burst Address A17 - A2, /A1, A0 3rd Burst Address A17 - A2, /A1, /A0 Linear Burst Sequence Table (MODE = VSS) External Address A17 - A2, 0, 0 A17 - A2, 0, 1 A17 - A2, 1, 0 A17 - A2, 1, 1 1st Burst Address A17 - A2, 0, 1 A17 - A2, 1, 0 A17 - A2, 1, 1 A17 - A2, 0, 0 2nd Burst Address A17 - A2, 1, 0 A17 - A2, 1, 1 A17 - A2, 0, 0 A17 - A2, 0, 1 3rd Burst Address A17 - A2, 1, 1 A17 - A2, 0, 0 A17 - A2, 0, 1 A17 - A2, 1, 0 Data Sheet M15393EJ1V0DS 5 µPD4382323, 4382363 Asynchronous Truth Table Operation /G I/O Read Cycle L Dout Read Cycle H Hi-Z Write Cycle × Hi-Z, Din Deselected × Hi-Z Remark × : don’t care Synchronous Truth Table Operation /CE CE2 /CE2 /AP /AC /ADV /WRITE CLK Address H × × × L × × L→H None L L × L × × × L→H None L × H L × × × L→H None L L × H L × × L→H None L × H H L × × L→H None Read Cycle / Begin Burst L H L L × × × L→H External Read Cycle / Begin Burst L H L H L × H L→H External Read Cycle / Continue Burst × × × H H L × L→H Next Read Cycle / Continue Burst H × × × H L × L→H Next Read Cycle / Suspend Burst × × × H H H × L→H Current Read Cycle / Suspend Burst H × × × H H × L→H Current Write Cycle / Begin Burst L H L H L × L L→H External Write Cycle / Continue Burst × × × H H L × L→H Next Write Cycle / Continue Burst H × × × H L × L→H Next Write Cycle / Suspend Burst × × × H H H × L→H Current Write Cycle / Suspend Burst H × × × H H × L→H Current Deselected Deselected Deselected Deselected Deselected Note Note Note Note Note Note Deselect status is held until new “Begin Burst” entry. Remarks 1. × : don’t care 2. /WRITE = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) and /BWE are LOW or /GW is LOW. /WRITE = H means the following two cases. (1) /BWE and /GW are HIGH. (2) /BW1, /BW2, /BW3, /BW4 and /GW are HIGH, and /BWE is LOW. 6 Data Sheet M15393EJ1V0DS µPD4382323, 4382363 Partial Truth Table for Write Enables Operation /GW /BWE /BW1 /BW2 /BW3 /BW4 Read Cycle H H × × × × Read Cycle H L H H H H Write Cycle / Byte 1 Only H L L H H H Write Cycle / All Bytes H L L L L L Write Cycle / All Bytes L × × × × × Remark × : don’t care Pass-Through Truth Table Previous Cycle Present Cycle Next Cycle Operation Add /WRITE I/O Operation Add /CEs /WRITE /G I/O Operation Write Cycle Ak L Dn(Ak) Read Cycle Am L H L Q1(Ak) Read Q1(Am) Deselected - H × × Hi-Z No Carry Over from Previous Cycle Remarks 1. × : don’t care 2. /WRITE = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) and /BWE are LOW or /GW is LOW. /WRITE = H means the following two cases. (1) /BWE and /GW are HIGH. (2) /BW1, /BW2, /BW3, /BW4 and /GW are HIGH, and /BWE is LOW. /CEs = L means /CE is LOW, /CE2 is LOW and CE2 is HIGH. /CEs = H means /CE is HIGH or /CE2 is HIGH or CE2 is LOW. ZZ (Sleep) Truth Table ZZ Chip Status ≤ 0.2 V Active Open Active ≥ VDD − 0.2 V Sleep Data Sheet M15393EJ1V0DS 7 µPD4382323, 4382363 Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Symbol Conditions MIN. TYP. MAX. Unit Note VDD –0.5 +4.0 V VDDQ –0.5 VDD V Input voltage VIN –0.5 VDD + 0.5 V 1, 2 Input / Output voltage VI/O –0.5 VDDQ + 0.5 V 1, 2 Operating ambient temperature TA 0 70 °C Storage temperature Tstg –55 +125 °C Output supply voltage Notes 1. –2.0 V (MIN.) (Pulse width : 2 ns) 2. VDDQ + 2.3 V (MAX.) (Pulse width : 2 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (TA = 0 to 70 °C) Parameter Supply voltage Output supply voltage High level input voltage Low level input voltage Symbol Conditions MIN. TYP. MAX. Unit VDD 3.135 3.3 3.465 V VDDQ 3.135 3.3 3.465 V VIH 2.0 VDDQ + 0.3 V +0.8 V VIL –0.3 Note Note –0.8 V (MIN.) (Pulse Width : 2 ns) Capacitance (TA = 25 °C, f = 1MHz) Parameter Symbol Test conditions MIN. TYP. MAX. Unit Input capacitance CIN VIN = 0 V 4 pF Input / Output capacitance CI/O VI/O = 0 V 7 pF Clock Input capacitance Cclk Vclk = 0 V 4 pF Remark These parameters are not 100% tested. 8 Data Sheet M15393EJ1V0DS µPD4382323, 4382363 DC Characteristics (TA = 0 to 70°C, VDD = 3.3 ± 0.165 V) Parameter Symbol Test condition MIN. TYP. MAX. Unit Input leakage current ILI VIN(except ZZ, MODE) = 0 V to VDD –2 +2 µA I/O leakage current ILO VI/O = 0 V to VDDQ, Outputs are disabled –2 +2 µA Operating supply current IDD Device selected, Cycle = MAX. -A67 440 mA VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA -A75 400 IDD1 Suspend cycle, Cycle = MAX. Note 170 /AC, /AP, /ADV, /GW, /BWEs ≥ VIH, VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA Standby supply current ISB Device deselected, Cycle = 0 MHz 30 mA VIN ≤ VIL or VIN ≥ VIH, All inputs are static ISB1 Device deselected, Cycle = 0 MHz 10 VIN ≤ 0.2 V or VIN ≥ VDD – 0.2 V, VI/O ≤ 0.2 V, All inputs are static ISB2 Device deselected, Cycle = MAX. 180 VIN ≤ VIL or VIN ≥ VIH Power down supply current ISBZZ ZZ ≥ VDD – 0.2 V, VI/O ≤ VDDQ + 0.2 V High level output voltage VOH IOH = –4.0 mA Low level output voltage VOL IOL = +8.0 mA Data Sheet M15393EJ1V0DS 10 2.4 mA V 0.4 V 9 µPD4382323, 4382363 AC Characteristics (TA = 0 to 70 °C, VDD = 3.3 ± 0.165 V) AC Test Conditions 3.3 V LVTTL Interface Input waveform (Rise / Fall time ≤ 3.0 ns) 3.0 V 1.5 V Test ponts 1.5 V 1.5 V Test points 1.5 V VSS Output waveform Output load condition CL : 30 pF 5 pF (TKHQX1, TKHQX2, TGLQX, TGHQZ, TKHQZ) Figure1 External load at test ZO = 50 Ω I/O (Output) 50 Ω CL VT = +1.5 V Remark CL includes capacitances of the probe and jig, and stray capacitances. 10 Data Sheet M15393EJ1V0DS µPD4382323, 4382363 Read and Write Cycle Parameter Symbol -A67 -A75 Unit (150 MHz) (133 MHz) Note Standard Alias MIN. MAX. MIN. MAX. Cycle time TKHKH TCYC 6.66 – 7.5 – ns Clock access time TKHQV TCD – 3.8 – 4.0 ns Output enable access time TGLQV TOE – 3.8 – 4.0 ns Clock high to output active TKHQX1 TDC1 0 – 0 – ns Clock high to output change TKHQX2 TDC2 1.5 – 1.5 – ns Output enable to output active TGLQX TOLZ 0 – 0 – ns Output disable to output high-Z TGHQZ TOHZ 0 3.5 0 3.5 ns Clock high to output high-Z TKHQZ TCZ 1.5 3.8 1.5 4.0 ns Clock high pulse width TKHKL TCH 2.0 – 2.0 – ns Clock low pulse width TKLKH TCL 2.0 – 2.0 – ns Setup times TAVKH TAS 2.0 – 2.0 – ns TADSVKH TSS Data in TDVKH TDS Write enable TWVKH TWS TADVVKH – Chip enable TEVKH – Address TKHAX TAH 0.5 – 0.5 – ns TKHADSX TSH Data in TKHDX TDH Write enable TKHWX TWH TKHADVX – TKHEX – Power down entry setup TZZES TZZES 5.0 – 5.0 – ns 1 Power down entry hold TZZEH TZZEH 1.0 – 1.0 – ns 1 Power down recovery setup TZZRS TZZRS 6.0 – 6.0 – ns 1 Power down recovery hold TZZRH TZZRH 0 – 0 – ns 1 Address Address status Address advance Hold times Address status Address advance Chip enable Note 1. Although ZZ signal input is asynchronous, the signal must meet specified setup and hold times in order to be recognized. Data Sheet M15393EJ1V0DS 11 12 READ CYCLE TKHKH CLK TADSVKH TKHKL TKHADSX TKLKH /AP TADSVKH TKHADSX /AC TAVKH TKHAX A1 Address A2 A3 TADVVKH TKHADVX Data Sheet M15393EJ1V0DS /ADV TWVKH TKHWX TWVKH TKHWX /BWE /BWs /GW TEVKH TKHEX /CEs Note1 /G TGLQV Data In Data Out Hi-Z TGHQZ TKHQX2 Q1(A1) Q1(A2) TKHQV TKHQZ Note2 Q2(A2) Q3(A2) Q4(A2) Q1(A2) Q1(A3) Notes 1. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. 2. Outputs are disabled within two clock cycles after deselect. Remark Qn(A2) refers to output from address A2. Q1-Q4 refer to outputs according to burst sequence. µPD4382323, 4382363 TGLQX WRITE CYCLE TKHKH CLK TADSVKH TKHADSX TKHKL TKLKH /AP TADSVKH TKHADSX /AC TAVKH Address TKHAX A1 A2 A3 Data Sheet M15393EJ1V0DS TADVVKH TKHADVX /ADV TWVKH TKHWX /BWENote1 /BWs TWVKH TKHWX TEVKH TKHEX /GWNote1 /CEsNote2 /G TDVKH D1(A1) TGHQZ Data Out D1(A2) TKHDX D2(A2) D2(A2) D3(A2) D4(A2) D1(A3) D2(A3) D3(A3) Hi-Z Notes 1. All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1-/BW4 LOW. 2. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. 13 µPD4382323, 4382363 Data In 14 READ / WRITE CYCLE TKHKH CLK TKLKH TKHKL TADSVKH TKHADSX /AP TADSVKH TKHADSX /AC TKHAX TAVKH A1 Address A2 A3 TADVVKH TKHADVX Data Sheet M15393EJ1V0DS /ADV TWVKH TKHWX TWVKH TKHWX /BWENote1 /BWs /GWNote1 TEVKH TKHEX /CEsNote2 /G TDVKH Data Out TGHQZ Hi-Z TKHQV TKHQX1 TGLQX Q1(A1) Q1(A2) Q1(A3) Q2(A3) Q3(A3) Q4(A3) Notes 1. All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1-/BW4 LOW. 2. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. µPD4382323, 4382363 Data In TKHDX D1(A2) SINGLE READ / WRITE CYCLE TKHKH CLK TKLKH TKHKL TADSVKH TKHADSX /AC TAVKH TKHAX Address A2 A1 A3 A5 A4 Data Sheet M15393EJ1V0DS TWVKH TKHWX TWVKH TKHWX A7 A6 A8 A9 /BWE Note1 /BWs /GW Note1 TEVKH TKHEX /CEs Note2 /G TDVKH TKHDX Data In D1(A5) Hi-Z Data Out TGLQV TGLQX Q1(A1) TGHQZ Q1(A2) Q1(A3) Q1(A4) D1(A6) D1(A7) TKHQZ TKHQV Note3 Q1(A7) Q1(A8) Remark /AP is HIGH and /ADV is don't care. 15 µPD4382323, 4382363 Notes 1. All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1-/BW4 LOW. 2. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. 3. Outputs are disabled within two clock cycles after deselect. Q1(A9) 16 POWER DOWN (ZZ) CYCLE TKHKH CLK TKHKL TKLKH /AP /AC Address A1 A2 Data Sheet M15393EJ1V0DS /ADV /BWE /BWs /GW /CEs /G Q1(A1) TZZEH Q1(A2) TZZES TZZRH ZZ Power Down (ISBZZ) State TZZRS µPD4382323, 4382363 Hi-Z Data Out STOP CLOCK CYCLE TKHKH CLK TKHKL TKLKH /AP /AC Address A1 A2 Data Sheet M15393EJ1V0DS /ADV /BWE /BWs /GW /CEs /G Data Out Hi-Z Q1(A1) Q1(A2) Power Down State (ISB1) Note Note VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V, VI/O ≤ 0.2 V 17 µPD4382323, 4382363 Data In µPD4382323, 4382363 Package Drawing 100-PIN PLASTIC LQFP (14x20) A B 80 81 51 50 detail of lead end S C D R Q 31 30 100 1 F G H I J M K P S N S L M NOTE ITEM Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 22.0±0.2 B 20.0±0.2 C 14.0±0.2 D 16.0±0.2 F 0.825 G 0.575 H 0.32 +0.08 −0.07 I J 0.13 0.65 (T.P.) K 1.0±0.2 L 0.5±0.2 M 0.17 +0.06 −0.05 N 0.10 P 1.4 Q 0.125±0.075 R 3° +7° −3° S 1.7 MAX. S100GF-65-8ET-1 18 Data Sheet M15393EJ1V0DS µPD4382323, 4382363 Recommended Soldering Condition Please consult with our sales offices for soldering conditions of the µPD4382323 and 4382363. Types of Surface Mount Devices µPD4382323GF : 100-PIN PLASTIC LQFP (14 x 20) µPD4382363GF : 100-PIN PLASTIC LQFP (14 x 20) Data Sheet M15393EJ1V0DS 19 µPD4382323, 4382363 [ MEMO ] 20 Data Sheet M15393EJ1V0DS µPD4382323, 4382363 [ MEMO ] Data Sheet M15393EJ1V0DS 21 µPD4382323, 4382363 [ MEMO ] 22 Data Sheet M15393EJ1V0DS µPD4382323, 4382363 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M15393EJ1V0DS 23 µPD4382323, 4382363 • The information in this document is current as of February, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4