PRELIMINARY CY7C1328F 256K x 18 Pipelined DCD Sync SRAM Features • Fully registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle chip deselect, depth expansion without wait state) • 256K × 18-bit common I/O architecture • 3.3V –5% and +10% core power supply • 2.5V or 3.3V I/O supply • Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 2.6 ns (for 225-MHz device) — 2.8 ns (for 200-MHz device) — 3.5 ns (for 166-MHz device) — 4.0 ns (for 133-MHz device) • • • • • • • — 4.5 ns (for 100-MHz device) Provide high-performance 3-1-1-1 access rate User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self-timed writes Asynchronous Output Enable JEDEC-standard 100-pin TQFP package and pinout “ZZ” Sleep Mode option Functional Description The CY7C1328F SRAM integrates 262,144x18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2 and CE2), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW0, BW1 and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and Burst Mode Control (MODE). The data outputs (Q), enabled by OE, are also asynchronous. Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle. Write cycles can be one to two bytes wide as controlled by the write control inputs. Individual byte write allows individual bytes to be written. BW0 controls DQ1–DQ8 and DQP1. BW1 controls DQ9–DQ16 and DQP2. BW0 and BW1 can be active only with BWE being LOW. GW being LOW causes all bytes to be written. Write pass-through capability allows written data available at the output for the immediately next Read cycle. This device also incorporates a pipelined enable circuit for easy depth expansion without penalizing system performance. The CY7C1328F operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible. The device is ideally suited for Pentium, 680x0, and PowerPC® systems and for systems that benefit from a wide synchronous data bus. Selection Guide -250 -225 -200 -166 -133 -100 Maximum Access Time 2.6 2.6 2.8 3.5 4.0 4.5 Maximum Operating Current 325 290 265 240 225 205 Maximum CMOS Standby Current 40 40 40 40 40 40 Shaded areas contain advance information. Cypress Semiconductor Corporation Document #: 38-05220 Rev. ** • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised December 19, 2002 PRELIMINARY CY7C1328F Functional Block Diagram—256Kx18[1] UPPER BYTE WRITE WEH# BWE# D Q LOWER BYTE WRITE D Q CE# lo byte write GW# ENABLE D CE2 Q D Q hi byte write WEL# CE2# ZZ Power Down Logic OE# ADSP# ADSC# CLR ADV# A1-A0 Binary Counter & Logic OUTPUT REGISTER D Q Output Buffers Address Register 256K x 9 x 2 SRAM Array A17-A2 Input Register DQ1DQ16, DQP1, DQP2 MODE Note: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information. Document #: 38-05220 Rev. ** Page 2 of 15 PRELIMINARY CY7C1328F Pin Configurations 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A6 A7 CE CE2 NC NC BW1 BW0 CE2 VCC VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 100-pin TQFP Top View NC NC NC CY7C1328F (256K x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A10 NC NC VDDQ VSSQ NC DQP1 DQ8 DQ7 VSSQ VDDQ DQ6 DQ5 VSS NC VDD ZZ DQ4 DQ3 VDDQ VSSQ DQ2 DQ1 NC NC VSSQ VDDQ NC NC NC MODE A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A15 A14 A13 A12 A11 A16 A17 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDDQ VSSQ NC NC DQ9 DQ10 VSSQ VDDQ DQ11 DQ12 NC VDD NC VSS DQ13 DQ14 VDDQ VSSQ DQ15 DQ16 DQP2 NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pin Descriptions Name (100TQFP) I/O Description A[17:0] InputAddress Inputs used to select one of the 256K address locations. Sampled at the rising edge Synchronous of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the two-bit counter. BW[1:0] InputByte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Synchronous Sampled on the rising edge of CLK. GW InputGlobal Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global Synchronous write is conducted (ALL bytes are written, regardless of the values on BW[1:0] and BWE). BWE InputByte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be Synchronous asserted LOW to conduct a byte write. CLK InputClock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. CE1 InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with Synchronous CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE2 InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with Synchronous CE1 and CE3 to select/deselect the device. CE3 InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with Synchronous CE1 and CE2 to select/deselect the device. OE InputOutput Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Document #: 38-05220 Rev. ** Page 3 of 15 PRELIMINARY CY7C1328F Pin Descriptions (continued) Name (100TQFP) I/O Description ADV InputAdvance Input signal, sampled on the rising edge of CLK. When asserted, it automatically Synchronous increments the address in a burst cycle. ADSP InputAddress Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, Synchronous A[17:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC InputAddress Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, Synchronous A[17:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ InputZZ “sleep” Input. This active-HIGH input places the device in a non-time-critical “sleep” condition Asynchronous with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. DQ[15:0] DP[1:0] I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ[15:0] and DP[1:0] are placed in a three-state condition. VDD Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power supply. VSS Ground Ground for the core of the device. Should be connected to ground of the system. VDDQ I/O Power Supply Power supply for the I/O circuitry. Should be connected to a 3.3V or 2.5V power supply. VSSQ I/O Ground Ground for the I/O circuitry. Should be connected to ground of the system. MODE InputStatic NC Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDDQ or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. No Connects. Burst Address Table (MODE = NC/VCC) First Address (external) Second Address (internal) Third Address (internal) A...A00 A...A01 A...A01 A...A00 A...A10 A...A11 Truth Table [2, 3, 4, 5, 6, 7, 8] Burst Address Table (MODE = GND) Fourth Address (internal) First Address (external) A...A10 A...A11 A...A11 A...A10 A...A11 A...A00 A...A01 A...A10 A...A01 A...A00 Operation Address Used CE Deselected Cycle, Power Down None H X X Deselected Cycle, Power Down None L X L Deselected Cycle, Power Down None L H Deselected Cycle, Power Down None L X Deselected Cycle, Power Down None L H Second Address (internal) Third Address (internal) A...A00 A...A01 A...A10 A...A11 A...A01 A...A10 A...A11 A...A00 A...A10 A...A11 A...A00 A...A01 A...A11 A...A00 A...A01 A...A10 CE2 CE2 ADSP Fourth Address (internal) ADSC ADV WRITE OE CLK DQ X L X X X L-H High-Z L X X X X L-H High-Z X L X X X X L-H High-Z L H L X X X L-H High-Z X H L X X X L-H High-Z Notes: 2. X = “Don’t Care.” H = logic HIGH. L = logic LOW. WRITE = L means [BWE + BWa*BWb]*GW equals LOW. WRITE = H means [BWE + BWa*BWb]*GW equals HIGH. 3. BWa enables write to DQa. BWb enables write to DQb. 4. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK. 5. Suspending burst generates wait cycle. 6. For a write operation following a read operation, OE must be HIGH before the input data required setup time plus High-Z time for OE and staying HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW along with chip being selected always initiates a Read cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for the CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification. Document #: 38-05220 Rev. ** Page 4 of 15 PRELIMINARY CY7C1328F Truth Table (continued)[2, 3, 4, 5, 6, 7, 8] Address Used CE Read Cycle, Begin Burst External L L H Read Cycle, Begin Burst External L L H Write Cycle, Begin Burst External L L Read Cycle, Begin Burst External L L Read Cycle, Begin Burst Operation CE2 CE2 ADSP ADSC ADV WRITE OE CLK DQ L X X X L L-H Q L X X X H L-H High-Z H H L X L X L-H D H H L X H L L-H Q External L L H H L X H H L-H High-Z Read Cycle, Continue Burst Next X X X H H L H L L-H Q Read Cycle, Continue Burst Next X X X H H L H H L-H High-Z Read Cycle, Continue Burst Next H X X X H L H L L-H Q Read Cycle, Continue Burst Next H X X X H L H H L-H High-Z Write Cycle, Continue Burst Next X X X H H L L X L-H D Write Cycle, Continue Burst Next H X X X H L L X L-H D Read Cycle, Suspend Burst Current X X X H H H H L L-H Q Read Cycle, Suspend Burst Current X X X H H H H H L-H High-Z Read Cycle, Suspend Burst Current H X X X H H H L L-H Q Read Cycle, Suspend Burst Current H X X X H H H H L-H High-Z Write Cycle, Suspend Burst Current X X X H H H L X L-H D Write Cycle, Suspend Burst Current H X X X H H L X L-H D Partial Truth Table for Read/Write Function GW BWE Read H H X X X X Read H L H H H H Write one byte H L L H H H Write all bytes H L L L L L Write all bytes L X X X X X Document #: 38-05220 Rev. ** BW1 BW2 BW3 BW4 Page 5 of 15 PRELIMINARY Maximum Ratings CY7C1328F Operating Range (Above which the useful life may be impaired. For user guidelines, not tested.) Voltage on VCC Supply Relative to VSS ......... –0.5V to +4.6V Range Com’l Ambient Temperature[9] Vdd 0°C to +70°C 3.3V −5%/+10% VIN .........................................................–0.5V to VCC + 0.5V Storage Temperature (plastic) ...................... –55°C to +150° Junction Temperature ..................................................+150° Power Dissipation ..........................................................1.0W Short Circuit Output Current ........................................50 mA Electrical Characteristics Over the Operating Range Parameter Description Min. Max. Unit 3.3V −5%/+10% 3.135 3.6 V I/O Supply Voltage 2.5V −5% to 3.3V +10% 2.375 3.6 V Output HIGH Voltage VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA 2.4 VDDQ = 2.5V, VDD = Min., IOH = –2.0 mA 2.0 VOL Output LOW Voltage VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA VIH Input HIGH Voltage VDDQ = 3.3V 2.0 VDDQ = 2.5V 1.7 VDD + 0.3V V VDDQ = 3.3V –0.3 0.8 V VDDQ = 2.5V VDD Power Supply Voltage VDDQ VOH Test Conditions VDDQ = 2.5V, VDD = Min., IOL = 2.0 mA V V 0.4 V 0.7 V VDD + 0.3V V VIL Input LOW Voltage[10] –0.3 0.7 V IX Input Load Current except ZZ and MODE GND ≤ VI ≤ VDDQ –5 5 µA Input Current of MODE Input = VSS –30 Input = VDDQ Input Current of ZZ 5 Input = VSS 30 µA 5 µA 4-ns cycle, 250 MHz 325 mA 4.4-ns cycle, 225 MHz 290 mA 5-ns cycle, 200 MHz 265 mA 6-ns cycle, 166 MHz 240 mA 7.5-ns cycle, 133 MHz 225 mA 10-ns cycle, 100MHz 205 mA 4-ns cycle, 250 MHz 120 mA 4.4-ns cycle, 225 MHz 115 mA 5-ns cycle, 200 MHz 110 mA 6-ns cycle, 166 MHz 100 mA 7.5-ns cycle, 133 MHz 90 mA 10-ns cycle, 100 MHz 80 mA GND ≤ VI ≤ VDDQ, Output Disabled Output Leakage Current IDD VDD Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC ISB1 Automatic CS Power-down Current—TTL Inputs Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = fMAX = 1/tCYC µA µA –5 Input = VDDQ IOZ µA –5 Notes: 9. TA is the case temperature. 10. Minimum voltage equals –2.0V for pulse durations of less than 20 ns. Document #: 38-05220 Rev. ** Page 6 of 15 PRELIMINARY CY7C1328F Electrical Characteristics Over the Operating Range Max. Unit ISB2 Parameter Automatic CS Power-down Current—CMOS Inputs Max. VDD, Device Deselected, VIN ≤ 0.3V or VIN > VDDQ – 0.3V, f = 0 All speeds 40 mA ISB3 Automatic CS Power-down Current—CMOS Inputs Max. VDD, Device Deselected, or VIN ≤ 0.3V or VIN > VDDQ – 0.3V, f = fMAX = 1/tCYC 4-ns cycle, 250 MHz 105 mA 4.4-ns cycle, 225 MHz 100 mA 5-ns cycle, 200 MHz 95 mA 6-ns cycle, 166 MHz 85 mA 7.5-ns cycle, 133 MHz 75 mA 10-ns cycle, 100 MHz 65 mA 45 mA ISB4 Description Automatic CS Power-down Current—TTL Inputs Test Conditions Min. Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = 0 Capacitance[11] Parameter Description CIN Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VDD = 3.3V. VDDQ = 3.3V Max. Unit 6 pF 8 pF 8 pF AC Test Loads and Waveforms 3.3/2.5V OUTPUT R = 317/1667Ω Z0 = 50Ω 10% (a) Document #: 38-05220 Rev. ** Including jig and scope (b) [12] 90% 10% 90% GND R = 351/1538Ω ≤ 1ns 5 pF VL = 1.5V for 3.3 VDDQ 1.25V for 2.5V VDDQ ALL INPUT PULSES VDD OUTPUT RL = 50Ω ≤ 1ns (c) Page 7 of 15 PRELIMINARY Switching Characteristics Over the Operating Range -250 Parameter Description CY7C1328F [13] -225 -200 -166 -133 -100 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit tCYC Clock Cycle Time 4.0 4.4 5.0 6.0 7.5 10 ns tCH Clock HIGH 1.7 2.0 2.0 2.5 3.0 3.5 ns tCL Clock LOW 1.7 2.0 2.0 2.5 3.0 3.5 ns tAS Address Set-up Before CLK Rise 0.8 1.2 1.2 1.5 1.5 1.5 ns tAH Address Hold After CLK Rise 0.4 tCO Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise 1.0 1.0 1.0 2.0 2.0 2.0 ns tCENS CEN Set-up Before CLK Rise 0.8 1.2 1.2 1.5 1.5 2.2 ns tCENH CEN Hold After CLK Rise 0.4 0.5 0.5 0.5 0.5 0.5 ns tWES GW, BWS[3:0] Set-up Before CLK Rise 0.8 1.2 1.2 1.5 1.5 1.5 ns tWEH GW, BWS[3:0] Hold After CLK Rise 0.4 0.5 0.5 0.5 0.5 0.5 ns tALS ADV/LD Set-up Before CLK Rise 0.8 1.2 1.2 1.5 1.5 1.5 ns tALH ADV/LD Hold After CLK Rise 0.4 0.5 0.5 0.5 0.5 0.5 ns tDS Data Input Set-up Before CLK Rise 0.8 1.2 1.2 1.5 1.5 1.5 ns tDH Data Input Hold After CLK Rise 0.4 0.5 0.5 0.5 0.5 0.5 ns tCES Chip Enable Set-Up Before CLK Rise 0.8 1.2 1.2 1.5 1.5 1.5 ns tCEH Chip Enable Hold After CLK Rise 0.4 0.5 0.5 0.5 0.5 0.5 ns tCHZ Clock to High-Z[13, 14, 15] tCLZ Clock to Low-Z[13, 14, 15] tEOHZ OE HIGH to Output High-Z[13, tEOLZ tEOV 0 OE LOW to Output Low-Z[13, 14, OE LOW to Output Valid[13] 0.5 2.6 2.6 0 0 0 0 0 4.5 0 4.0 0 3.5 ns 4.5 4.0 3.5 0 2.8 0.5 4.0 3.5 2.8 0 2.6 0.5 3.5 2.8 2.6 0 2.6 0.5 2.8 2.6 2.6 14, 15] 15] 0.5 2.6 ns ns 4.5 0 4.5 ns ns ns 4.5 ns Shaded area contains advance information. Notes: 11. Tested initially and after any design or process changes that may affect these parameters. 12. R1 = 1667Ω and R2 = 1538Ω for IOH/IOL = –4/8 mA, R1 = 521Ω and R2 = 481Ω for IOH/IOL=–2/2 mA. 13. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with A/C test conditions shown in (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 14. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 15. This parameter is sampled and not 100% tested. Document #: 38-05220 Rev. ** Page 8 of 15 PRELIMINARY CY7C1328F Switching Waveforms Read Timing[16, 17] Single Read tCYC Burst Read Unselected tCH Pipelined Read CLK tADH tADS tCL ADSP ignored with CE1 inactive ADSP tADS ADSC initiated read ADSC tADVS tADH Suspend Burst ADV tADVH tAS ADD RD1 RD3 RD2 tAH GW tWS tWS tWH BWE tCES tCEH tWH CE1 masks ADSP CE Unselected with CE2 CE2 tCES tCEH CE2 tCES OE tEOV tCEH tOEHZ tDOH Data Out tCO 1a 1a 2a Double-Cycle Deselect 2b 2c 2c tCLZ = DON’T CARE 2d 3a tCHZ = UNDEFINED Notes: 16. CE active in this timing diagram means that all chip enables CE, CE2, and CE2 are active. 17. For X18 product, there are only BW1 (i.e., WEL) and BW2 (i.e., WEH) for byte write control. Document #: 38-05220 Rev. ** Page 9 of 15 PRELIMINARY CY7C1328F Switching Waveforms (continued) Write Timing[16] CLK tS ADSP# tH ADSC# tS A1 ADDRESS A2 A3 tH BW1#, BW2#, BW3#, BW4#, BWE# GW# CE# tS ADV# tH OE# tKQX DQ Q tOEHZ D(A1) SINGLE WRITE Document #: 38-05220 Rev. ** D(A2) D(A2+1) D(A2+1) D(A2+2) BURST WRITE D(A2+3) D(A3) D(A3+1) D(A3+2) BURST WRITE Page 10 of 15 PRELIMINARY CY7C1328F Switching Waveforms (continued) Read/Write Timing[16] CLK tS ADSP# tH ADSC# tS ADDRESS A1 BW1#, BW2#, BW3#, BW4#, BWE#, GW# A2 A3 A4 A5 tH CE# ADV# OE# DQ Q(A1) Single Reads Document #: 38-05220 Rev. ** Q(A2) D(A3) Single Write Q(A4) Q(A4+1) Burst Read Q(A4+2) D(A5) D(A5+1) Burst Write Page 11 of 15 PRELIMINARY CY7C1328F Switching Waveforms (continued) tCYC tCH Pipeline Timing[18, 19] tCL CLK tAS ADD RD1 tADS RD2 RD3 WD1 RD4 WD2 WD3 WD4 tADH ADSC initiated Reads ADSC ADSP initiated Reads ADSP ADV tCEH tCES CE1 CE tWEH tWES WE ADSP ignored with CE1 HIGH OE tCLZ Data In/Out 1a Out 2a Out 3a Out 4a Out 1a In 2a In 3a In 4a D(C) In tCO Back to Back Reads = DON’T CARE tDOH tCHZ = UNDEFINED Notes: 18. Device originally deselected. 19. CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device. Document #: 38-05220 Rev. ** Page 12 of 15 PRELIMINARY CY7C1328F Switching Waveforms (continued) OE Switching Waveforms OE tEOV tEOHZ three-state I/Os tEOLZ Z Mode Timing [20, 21] CLK ADSP HIGH ADSC CE1 LOW CE2 HIGH CE3 ZZ tZZS IDD IDD(active) tZZREC IDDZZ I/Os Three-state Ordering Information Speed (MHz) Ordering Code Package Name Package Type Operating Range Commercial 250 CY7C1328F-250AC A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 225 CY7C1328F-225AC A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 200 CY7C1328F-200AC A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 166 CY7C1328F-166AC A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 133 CY7C1328F-133AC A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100 CY7C1328F-100AC A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Shaded area contains advance information. Notes: 20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 21. I/Os are in three-state when exiting ZZ sleep mode. Document #: 38-05220 Rev. ** Page 13 of 15 PRELIMINARY CY7C1328F Package Diagram 100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-A Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a registered trademark of International Business Machines, Incorporated. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05220 Rev. ** Page 14 of 15 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CY7C1328F Document History Page Document Title: CY7C1328F 256K x 18 Pipelined DCD Sync SRAM Document Number: 38-05220 REV. ECN NO. Issue Date Orig. of Change ** 119825 03/04/03 HGK Document #: 38-05220 Rev. ** Description of Change New Data Sheet Page 15 of 15