ETC W194-70G

W194
Frequency Multiplier and Zero Delay Buffer
Propagation Delay: ....................................................±350 ps
Propagation delay is affected by input rise time.
1W194
Features
Table 1. Configuration Options
• Two outputs
• Configuration options allow various multiplications of
the reference frequency—refer to Table 1 to determine
the specific option which meets your multiplication
needs
• Available in 8-pin SOIC package
Key Specifications
Operating Voltage: ............................ 3.3V ±5% or 5.0 ±10%
FBIN
FS0
FS1
OUT1
OUT2
OUT1
0
0
2 X REF
REF
OUT1
1
0
4 X REF
2 X REF
OUT1
0
1
REF
REF/2
OUT1
1
1
8 X REF
4 X REF
OUT2
0
0
4 X REF
2 X REF
Operating Range: .......................10 MHz < fOUT1 < 133 MHz
OUT2
1
0
8 X REF
4 X REF
Absolute Jitter: ......................................................... ±500 ps
OUT2
0
1
2 X REF
REF
Output to Output Skew: .............................................. 250 ps
OUT2
1
1
16 X REF
8 X REF
Block Diagram
Pin Configuration
SOIC
External feedback connection to
OUT1 or OUT2, not both
FBIN
FS0
FS1
IN
Reference
Input
÷Q
Phase
Detector
FBIN
1
8
OUT2
IN
2
7
VDD
GND
3
6
OUT1
FS0
4
5
FS1
Charge
Pump
Loop
Filter
Output
Buffer
OUT1
Output
Buffer
OUT2
VCO
÷2
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
March 16, 2001. Rev. *C
W194
Pin Definitions
Pin No.
Pin
Type
IN
2
I
Reference Input: The output signals will be synchronized to this signal.
FBIN
1
I
Feedback Input: This input must be fed by one of the outputs (OUT1 or OUT2) to ensure
proper functionality. If the trace between FBIN and the output pin being used for feedback
is equal in length to the traces between the outputs and the signal destinations, then the
signals received at the destinations will be synchronized to the REF signal input (IN).
OUT1
6
O
Output 1: The frequency of the signal provided by this pin is determined by the feedback
signal connected to FBIN, and the FS0:1 inputs (see Table 1).
OUT2
8
O
Output 2: The frequency of the signal provided by this pin is one-half of the frequency of
OUT1. See Table 1.
VDD
7
P
Power Connections: Connect to 3.3V or 5V. This pin should be bypassed with a 0.1-µF
decoupling capacitor. Use ferrite beads to help reduce noise for optimal jitter performance.
GND
3
P
Ground Connection: Connect all grounds to the common system ground plane.
FS0:1
4, 5
I
Function Select Inputs: Tie to VDD (HIGH, 1) or GND (LOW, 0) as desired per Table 1.
Pin Name
Pin Description
Overview
“How to Implement Zero Delay,” and “Inserting Other Devices
in Feedback Path.”
The W194-70 is a two-output zero delay buffer and frequency
multiplier. It provides an external feedback path allowing maximum flexibility when implementing the Zero Delay feature.
This is explained further in the sections of this data sheet titled
The W194-70 is a pin-compatible upgrade of the Cypress
W42C70-01. The W194-70 addresses some application dependent problems experienced by users of the older device.
Ferrite
Bead
CA
G
V+
10 µF
Power Supply Connection
C8
G
0.01 µF
OUT 2
FBIN
1
7
IN
OUTPUT 2
VDD
C9 = 0.1 µF
G
2
OUT 1
3
GND
FS0
22Ω
8
22Ω
OUTPUT 1
6
G
5
4
Figure 1. Schematic/Suggested Layout
2
FS1
W194
How to Implement Zero Delay
device (ASIC, multiple output clock buffer/driver, etc.) which is
put into the feedback path.
Typically, Zero Delay Buffers (ZDBs) are used because a designer wants to provide multiple copies of a clock signal in
phase with each other. The whole concept behind ZDBs is that
the signals at the destination chips are all going HIGH at the
same time as the input to the ZDB. In order to achieve this,
layout must compensate for trace length between the ZDB and
the target devices. The method of compensation is described
below.
Referring to Figure 2, if the traces between the ASIC/Buffer
and the destination of the clock signal(s) (A) are equal in length
to the trace between the buffer and the FBIN pin, the signals
at the destination(s) device will be driven HIGH at the same
time the Reference clock provided to the ZDB goes HIGH.
Synchronizing the other outputs of the ZDB to the outputs from
the ASIC/Buffer is more complex however, as any propagation
delay from the ZDB output to the ASIC/Buffer output must be
accounted for.
External feedback is the trait that allows for this compensation.
The PLL on the ZDB will cause the feedback signal to be in
phase with the reference signal. When laying out the board,
match the trace lengths between the output being used for
feedback and the FBIN input to the PLL.
Reference
Signal
If it is desirable to either add a little delay, or slightly precede
the input signal, this may also be affected by either making the
trace to the FBIN pin a little shorter or a little longer than the
traces to the devices being clocked.
Feedback
Input
Zero
Delay
Buffer
ASIC/
Buffer
A
Inserting Other Devices in Feedback Path
Figure 2. 6 Output Buffer in the Feedback Path
Another nice feature available due to the external feedback is
the ability to synchronize signals to the signal coming from
some other device. This implementation can be applied to any
3
W194
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.
.
Parameter
Description
Rating
Unit
VDD, VIN
Voltage on any pin with respect to GND
–0.5 to +7.0
V
TSTG
Storage Temperature
–65 to +150
°C
TA
Operating Temperature
0 to +70
°C
TB
Ambient Temperature under Bias
–55 to +125
°C
PD
Power Dissipation
0.5
W
DC Electrical Characteristics: TA = 0°C to 70°C or –40° to 85°C, VDD = 3.3V ±5%
Parameter
Description
Test Condition
Min.
IDD
Supply Current
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 12 mA
IOL = 8 mA
VOH
Output High Voltage
IOL = 12 mA
IOL = 8 mA
2.4
IIL
Input Low Current
VIN = 0V
–40
IIH
Input High Current
VIN = VDD
Unloaded, 100 MHz
Typ.
Max.
Unit
17
35
mA
0.8
V
2.0
V
0.4
V
V
5
µA
5
µA
Typ.
Max.
Unit
17
35
mA
0.8
V
DC Electrical Characteristics: TA = 0°C to 70°C or –40° to 85°C, VDD = 5V ±10%
Parameter
Description
Test Condition
Min.
IDD
Supply Current
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 12 mA
IOL = 8 mA
VOH
Output High Voltage
IOL = 12 mA
IOL = 8 mA
2.4
IIL
Input Low Current
VIN = 0V
–80
IIH
Input High Current
VIN = VDD
Unloaded, 100 MHz
2.0
V
0.4
4
V
V
5
µA
5
µA
W194
AC Electrical Characteristics: TA = 0°C to +70°C or –40° to 85°C, VDD = 3.3V ±5%
Parameter
Description
Test Condition
[1]
fIN
Input Frequency
OUT1 15-pF load
tR
Output Rise Time
tF
Output Fall Time
10
Unit
133
MHz
2.0V to 0.8V, 15-pF load
3.5
ns
2.0V to 0.8V, 15-pF load
2.5
ns
10
ns
10
ns
Input Clock Rise Time
FBIN to REF
tPD
[2]
[3]
Input Clock Fall
Max.
MHz
Output Frequency
tICLKF
Typ.
OUT2 = REF
fOUT
tICLKR
Min.
Time[3]
Skew[4, 5]
Measured at VDD/2
[6]
–2
0.6
2
ns
40
50
60
%
tD
Duty Cycle
15-pF load
tLOCK
PLL Lock Time
Power supply stable
1.0
ms
tJC
Jitter, Cycle-to-Cycle
FOUT >30 MHz
300
ps
tDC
Die out
Time[7]
100
Clock Cycles
AC Electrical Characteristics: TA = 0°C to +70°C or –40° to 85°C, VDD = 5.0V ±10%
Parameter
fIN
Description
Input
Test Condition
Frequency[1]
Min.
OUT2 = REF
load[2]
Typ.
Max.
Unit
5
133
MHz
10
133
MHz
fOUT
Output Frequency
OUT1 15-pF
tR
Output Rise Time
2.0V to 0.8V, 15-pF load
2.5
ns
tF
Output Fall Time
2.0V to 0.8V, 15-pF load
1.5
ns
10
ns
10
ns
tICLKR
tICLKF
Input Clock Rise
Input Clock Fall
FBIN to REF
tPD
Time[3]
Time[3]
Skew[4, 5]
Measured at VDD/2
load[6, 8]
–2
0.6
2
ns
40
50
60
%
tD
Duty Cycle
15-pF
tLOCK
PLL Lock Time
Power supply stable
1.0
ms
tJC
Jitter, Cycle-to-Cycle
FOUT > 30 MHz
200
ps
Ordering Information
Ordering Code
W194
Option
Package
Name
Package Type
-70
G
8-pin SOIC (150-mil)
Temperature Grade
Commerical (0o to 70o C)
I = Industrail (–40o to85oC)
Document #: 38-00794-*C
Notes:
1. Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration).
2. For the higher drive -11, the load is 20 pF.
3. Longer input rise and fall time will degrade skew and jitter performance.
4. All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V.
5. Skew is measured at 1.4V on rising edges.
6. Duty cycle is measured at 1.4V.
7. 33 MHz reference input suddenly stopped (0MHz). Number of cycles provided prior to output falling to <16 MHz.
8. Duty Cycle measured at 120 MHz. For 133 MHz, degrades to 35/65 worst case.
5
W194
Package Diagram
8-Pin Small Outlined Integrated Circuit (SOIC, 150-mil)
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.