THIS SPEC IS OBSOLETE Spec No: 38-07216 Spec Title: W132 Spread Aware(TM), Ten/Eleven Output Zero Delay Buffer Sunset Owner: RGL Replaced by: N/A 1W132 W132 Spread Awareª, Ten/Eleven Output Zero Delay Buffer Features Key Specifications • Spread Aware™—designed to work with SSFTG reference signals • Well suited to both 100- and 133-MHz designs • Ten (-09B) or Eleven (-10B) LVCMOS/LVTTL outputs • Single output enable pin for -10 version, dual pins on -09 devices allow shutting down a portion of the outputs. • 3.3V power supply • On board 25W damping resistors • Available in 24-pin TSSOP package Operating Voltage: ................................................ 3.3V±10% Operating Range: ........................25 MHz < fOUT < 140 MHz Cycle-to-Cycle Jitter: ................................................<150 ps Output to Output Skew: ............................................<100 ps Phase Error Jitter: .....................................................<125 ps Block Diagram FBIN CLK Pin Configurations FBOUT PLL 1 24 CLK VDD 2 23 AVDD Q0 3 22 VDD Q1 4 21 Q9 20 Q8 19 GND 18 GND Q1 Q2 OE0:4 Q3 Q4 OE Q5 OE5:8 W132-10B AGND Q0 Q2 5 GND 6 GND 7 Q3 8 17 Q7 Q4 9 16 Q6 Q6 VDD 10 15 Q5 Q7 OE 11 14 VDD Q8 FBOUT 12 13 FBIN AGND 1 24 CLK VDD 2 23 AVDD Q0 3 22 VDD Q1 4 21 Q8 Q2 5 20 Q7 GND 6 19 GND GND 7 18 GND Q3 8 17 Q6 Q4 9 16 Q5 VDD 10 15 VDD OE0:4 11 14 OE5:8 FBOUT 12 13 FBIN Q9 configuration of these blocks dependent upon specific option being used W132-09B Spread Aware is a trademark of Cypress Semiconductor Corporation. Cypress Semiconductor Corporation Document #: 38-07216 Rev. OBS • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 02, 2004 W132 Pin Definitions Pin Name Pin No. (-09B) Pin No. (-10B) Pin Type CLK 24 24 I Reference Input: Output signals Q0:9 will be synchronized to this signal. FBIN 13 13 I Feedback Input: This input must be fed by one of the outputs (typically FBOUT) to ensure proper functionality. If the trace between FBIN and FBOUT is equal in length to the traces between the outputs and the signal destinations, then the signals received at the destinations will be synchronized to the CLK signal input. Q0:8 3, 4, 5, 8, 9, 16, 17, 20, 21 3, 4, 5, 8, 9, 15, 16, 17, 20 O Integrated Series Resistor Outputs: The frequency and phase of the signals provided by these pins will be equal to the reference signal if properly laid out. Each output has a 25Ω series damping resistor integrated. Q9 n/a 21 O Integrated Series Resistor Output: The frequency and phase of the signal provided by this pin will be equal to the reference signal if properly laid out. This output has a 25Ω series damping resistor integrated. FBOUT 12 12 O Feedback Output: This output has a 25Ω series resistor integrated on chip. Typically it is connected directly to the FBIN input with a trace equal in length to the traces between outputs Q0:9 and the destination points of these output signals. AVDD 23 23 P Analog Power Connection: Connect to 3.3V. Use ferrite beads to help reduce noise for optimal jitter performance. AGND 1 1 G Analog Ground Connection: Connect to common system ground plane. VDD 2, 10, 15, 22 2, 10, 14, 22 P Power Connections: Connect to 3.3V. Use ferrite beads to help reduce noise for optimal jitter performance. GND 6, 7, 18, 19 6, 7, 18, 19 G Ground Connections: Connect to common system ground plane. OE n/a 11 I Output Enable Input: Tie to VDD (HIGH, 1) for normal operation. when brought to GND (LOW, 0) all outputs are disabled to a LOW state. OE0:4 11 n/a I Output Enable Input: Tie to VDD (HIGH, 1) for normal operation. when brought to GND (LOW, 0) outputs Q0:4 are disabled to a LOW state. OE5:8 14 n/a I Output Enable Input: Tie to VDD (HIGH, 1) for normal operation. when brought to GND (LOW, 0) outputs Q5:8 are disabled to a LOW state. Pin Description Overview The W132 is a PLL-based clock driver designed for use in dual inline memory modules. The clock driver has output frequencies of up to 133 MHz and output to output skews of less than 250 ps. The W132 provides minimum cycle-to-cycle and long term jitter, which is of significant importance to meet the tight input-to-input skew budget in DIMM applications. The current generation of 256 and 512 megabyte memory modules needs to support 100-MHz clocking speeds. Especially for cards configured in 16x4 or 8x8 format, the clock signal provided from the motherboard is generally not strong enough to meet all the requirements of the memory and logic Document #: 38-07216 Rev. OBS on the DIMM. The W132 takes in the signal from the motherboard and buffers out clock signals with enough drive to support all the DIMM board clocking needs. The W132 is also designed to meet the needs of new PC133 SDRAM designs, operating to 133 MHz. The W132 was specifically designed to accept SSFTG signals currently being used in motherboard designs to reduce EMI. Zero delay buffers which are not designed to pass this feature through may cause skewing failures. Output enable pins allow for shutdown of output when they are not being used. This reduces EMI and power consumption. Page 2 of 6 W132 VDD VDD 0.1µF 0.1µF GND 24 AVDD 23 Q0 VDD 22 4 Q1 Q9 21 5 Q2 Q8 20 6 GND GND 19 7 GND GND 18 8 Q3 Q7 17 9 Q4 Q6 16 10 VDD Q5 15 11 OE VDD 14 12 FBOUT FBIN 13 1 AGND 2 VDD 3 0.1µF 3.3V FB 10µF 0.1µF 10µF FB VDD 0.1µF VDD Figure 1. Schematic Spread Aware Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. Cypress has been one of the pioneers of SSFTG development, and we designed this product so as not to filter off the Spread Spectrum feature of the Reference input, assuming it exists. When a zero delay buffer is not designed to pass the SS feature through, the result is a significant amount of tracking skew which may cause problems in systems requiring synchronization. For more details on Spread Spectrum timing technology, please see the Cypress application note titled, ÒEMI Suppression Techniques with Spread Spectrum Frequency Timing Generator (SSFTG) ICs.Ó How to Implement Zero Delay Typically, zero delay buffers (ZDBs) are used because a designer wants to provide multiple copies of a clock signal in phase with each other. The whole concept behind ZDBs is that the signals at the destination chips are all going HIGH at the same time as the input to the ZDB. In order to achieve this, layout must compensate for trace length between the ZDB and the target devices. The method of compensation is described below. External feedback is the trait that allows for this compensation. The PLL on the ZDB will cause the feedback signal to be in phase with the reference signal. When laying out the board, match the trace lengths between the output being used for feed back and the FBIN input to the PLL. Document #: 38-07216 Rev. OBS If it is desirable to either add a little delay, or slightly precede the input signal, this may also be affected by either making the trace to the FBIN pin a little shorter or a little longer than the traces to the devices being clocked. Inserting Other Devices in Feedback Path Another nice feature available due to the external feedback is the ability to synchronize signals up to the signal coming from some other device. This implementation can be applied to any device (ASIC, multiple output clock buffer/driver, etc.) which is put into the feedback path. Referring to Figure 2, if the traces between the ASIC/buffer and the destination of the clock signal(s) (A) are equal in length to the trace between the buffer and the FBIN pin, the signals at the destination(s) device will be driven high at the same time the Reference clock provided to the ZDB goes high. Synchronizing the other outputs of the ZDB to the outputs form the ASIC/Buffer is more complex however, as any propagation delay in the ASIC/Buffer must be accounted for. Reference Signal Feedback Input Zero Delay Buffer ASIC/ Buffer A Figure 2. 6 Output Buffer in the Feedback Path Page 3 of 6 W132 Absolute Maximum Ratings[1] Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. . Parameter Description Rating Unit VDD, VIN Voltage on any pin with respect to GND Ð0.5 to +7.0 V TSTG Storage Temperature Ð65 to +150 ûC TA Operating Temperature 0 to +70 ûC TB Ambient Temperature under Bias Ð55 to +125 ûC PD Power Dissipation 0.5 W DC Electrical Characteristics: TA =0ûC to 70ûC, VDD = 3.3V ±10% Parameter Description Test Condition IDD Supply Current VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage IOH = Ð12 mA IIL Input Low Current IIH Input High Current Min Typ Unloaded, 100 MHz Max Unit 200 mA 0.8 V 2.0 V IOL = 12 mA 0.8 V VIN = 0V 50 µA VIN = VDD 50 µA Max Unit 140 MHz 2.1 V AC Electrical Characteristics: TA = 0ûC to +70ûC, VDD = 3.3V ±10% Parameter Description Test Condition Min load[5] 25 Typ fOUT Output Frequency 30-pF tR Output Rise Time 0.8V to 2.0V, 30-pF load 2.1 ns tF Output Fall Time 2.0V to 0.8V, 30-pF load 2.5 ns 4.5 ns 4.5 ns tICLKR tICLKF Input Clock Rise Time[2] [2] Input Clock Fall Time tPEJ CLK to FBIN Skew tSK Variation[3, 4] Measured at VDD/2 Ð350 0 350 ps Output to Output Skew All outputs loaded equally Ð100 0 100 ps tD Duty Cycle 30-pF load 43 50 58 % tLOCK PLL Lock Time Power supply stable 1.0 ms tJC Jitter, Cycle-to-Cycle 150 ps Notes: 1. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 2. Longer input rise and fall time will degrade skew and jitter performance. 3. Skew is measured at VDD/2 on rising edges. 4. Duty cycle is measured at VDD/2. 5. Production tests are run at 133 MHz. Ordering Information Ordering Code W132 Option -09B, -10B Document #: 38-07216 Rev. OBS Package Type X = 24-pin TSSOP Page 4 of 6 W132 Package Diagram 24-Pin Thin Shrink Small Outline Package (TSSOP) Document #: 38-07216 Rev. OBS Page 5 of 6 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. W132 Document Title: W132 Spread Awareª, Ten/Eleven Output Zero Delay Buffer Document Number: 38-07216 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 110481 12/15/01 SZV Change from Spec number: 38-00792 to 38-07216 *A 122835 12/22/02 RBI Add Power up Requirements to Maximum Ratings Information OBS 294835 See ECN RGL To Obsolete the DS Document #: 38-07216 Rev. OBS Page 6 of 6