CYPRESS W196

PRELIMINARY
W196
Spread Spectrum FTG for 440BX and VIA Apollo Pro-133
Features
CPU Cycle to Cycle Jitter: ..........................................250 ps
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• System frequency synthesizer for 440BX, 440ZX, and
VIA Apollo Pro-133
• I2C programmable to 155 MHz (32 selectable
frequencies)
• Two skew-controlled copies of CPU output
• Seven copies of PCI output (synchronous w/CPU output)
• One copy of 14.31818-MHz IOAPIC output
• One copy of 48-MHz USB output
• Selectable 24-/48-MHz clock is determined by resistor
straps on power up
• One high-drive output buffer that produces a copy of
the 14.318-MHz reference
• Isolated core VDD pin for noise reduction
CPU, PCI Output Edge Rate:......................................... ≥1 V/ns
CPU0:1 Output Skew: ................................................175 ps
PCI_F, PCI1:6 Output Skew: .......................................500 ps
CPU to PCI Skew: ........................ 1.5 to 4.0 ns (CPU Leads)
REF2X/SEL48#, SCLOCK, SDATA:............... 250-kΩ pull-up
FS1:........................................................... 250-kΩ pull-down
FS0:...................................................No pull-up or pull-down
Note: Internal pull-up or pull-down resistors should not be relied upon for setting I/O pins HIGH or LOW.
Table 1. Pin Selectable Frequency
Key Specifications
Supply Voltages: ....................................... VDDQ3 = 3.3V±5%
VDDQ2 = 2.5V±5%
Block Diagram
FS1
FS0
CPU(0:1)
PCI
1
1
133.3 MHz
33.3 MHz
1
0
105 MHz
35 MHz
0
1
100 MHz
33.3 MHz
0
0
66.8 MHz
33.3 MHz
Pin Configuration
VDDQ3
REF2X/SEL48#
GND
X1
X2
XTAL
OSC
VDDQ3
IOAPIC
PLL Ref Freq
VDDQ2
CPU0
CPU1
GND
FS1
FS0
PLL 1
÷2/÷3
VDDQ3
X1
X2
GND
PCI_F
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
PCI6
VDDQ3
48MHz
24_48MHz/FS1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GND
REF2X/SEL48#
VDDQ3
VDDQ2
IOAPIC
VDDQ2
CPU0
CPU1
VDDQ3
GND
SDATA
SCLOCK
FS0
GND
PCI_F
PCI1
PCI2
PCI3
PCI4
SDATA
SCLOCK
PCI5
2
I C
LOGIC
PCI6
GND
VDDQ3
48MHz
PLL2
24_48MHz/FS1
GND
Cypress Semiconductor Corporation
Document #: 38-07170 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 15, 2002
PRELIMINARY
W196
Pin Definitions
Pin
No.
Pin
Type
CPU0:1
22, 21
O
CPU Clock Outputs 0 through 1: These two CPU clocks run at a frequency set by
FS0:1 or the serial data interface. See Table 1 and Table 5. Output voltage swing is
set by the voltage applied to VDDQ2.
PCI1:6
PCI_F
5, 6, 7, 8, 10,
11, 4
O
PCI Bus Clock Outputs 1 through 6 and PCI_F: These seven PCI clock outputs
run synchronously to the CPU clock. Voltage swing is set by the power connection
to VDDQ3.
IOAPIC
24
O
I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage
swing is set by the power connection to VDDQ2.
48MHz
13
O
48-MHz Output: Fixed 48-MHz USB clock. Output voltage swing is controlled by
voltage applied to VDDQ3.
24_48MHz/FS1
14
I/O
24-MHz or 48-MHz Output/Frequency Select 1 Input: Frequency is set by the state
of pin 27 on power-up. This pin doubles as the select strap to determine device
operating frequency as described in Table 1.
REF2X/SEL48#
27
I/O
I/O Dual-Function REF2X and SEL48# Pin: Upon power-up, the state of SEL48#
is latched. The initial state is set by either a 10K resistor to GND or to VDD. A 10K
resistor to GND causes pin 14 to output 48 MHz. If the pin is strapped to VDD, pin
14 will output 2 4MHz. After 2 ms, the pin becomes a high-drive output that produces
a copy of 14.318 MHz.
FS0
16
I
Frequency Selection 0 Input: Selects CPU clock frequency as shown in Table 1
on page 1.
SDATA
18
I/O
I2C Data Pin: Data should be presented to this input as described in the I2C section
of this data sheet. Internal 250-kΩ pull-up resistor.
SCLOCK
17
I
I2C Clock Pin: The I2C Data clock should be presented to this input as described in
the I2C section of this data sheet.
X1
1
I
Crystal Connection or External Reference Frequency Input: Connect to either
a 14.318-MHz crystal or other reference signal.
X2
2
I
Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
VDDQ3
9, 12, 20, 26
P
Power Connection: Power supply for core logic and PLL circuitry, PCI, 48/24MHz,
and Reference output buffers. Connect to 3.3V supply.
VDDQ2
23, 25
P
Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to
2.5V supply.
3, 15, 19, 28
G
Ground Connections: Connect all ground pins to the common system ground
plane.
Pin Name
GND
Document #: 38-07170 Rev. *A
Pin Description
Page 2 of 12
PRELIMINARY
Functional Description
I/O Pin Operation
Pins 14 and 27 are dual-purpose l/O pins. Upon power-up
these pins act as logic inputs, allowing the determination of
assigned device functions. A short time after power-up, the
logic state of these pins is latched and the pins become clock
outputs. This feature reduces device pin count by combining
clock outputs with input select pins.
An external 10-kΩ “strapping” resistor is connected between
the l/O pin and ground or VDD. Connection to ground sets a
latch to “0”, connection to VDD sets a latch to “1.” Figure 1 and
Figure 2 show two suggested methods for strapping resistor
connections.
Upon W196 power-up, the first 2 ms of operation is used for
input logic selection. During this period, the REF2X and
24_48MHz clock output buffers are three-stated, allowing the
output strapping resistor on the l/O pin to pull the pin and its
associated capacitive clock load to either a logic HIGH or LOW
state. At the end of the 2-ms period, the established logic “0”
or “1” condition of the l/O pin is then latched. Next the output
W196
buffer is enabled, which converts the l/O pin into an operating
clock output. The 2-ms timer is started when VDD reaches
2.0V. The input bits can only be reset by turning VDD off and
then back on again.
It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of the clock output is 20Ω (nominal), which is minimally
affected by the 10-kΩ strap to ground or VDD. As with the series termination resistor, the output strapping resistor should
be placed as close to the l/O pin as possible in order to keep
the interconnecting trace short. The trace from the resistor to
ground or VDD should be kept less than two inches in length
to prevent system noise coupling during input logic sampling.
When the clock output is enabled following the 2-ms input period, a 14.318-MHz output frequency is delivered on the pin,
assuming that VDD has stabilized. If VDD has not yet reached
full value, output frequency initially may be below target but will
increase to target once VDD voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
VDD
Output Strapping Resistor
Series Termination Resistor
10 kΩ
(Load Option 1)
Clock Load
W196
Output
Buffer
Power-on
Reset
Timer
Hold
Output
Low
Output Three-state
Q
10 kΩ
(Load Option 0)
D
Data
Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Jumper Options
Output Strapping Resistor
VDD
Series Termination Resistor
10 kΩ
W196
Power-on
Reset
Timer
R
Output
Buffer
Hold
Output
Low
Output Three-state
Q
Clock Load
Resistor Value R
D
Data
Latch
Figure 2. Input Logic Selection Through Jumper Option
Document #: 38-07170 Rev. *A
Page 3 of 12
PRELIMINARY
Serial Data Interface
The W196 features a two-pin, serial data interface that can be
used to configure internal register settings that control particular device functions. Upon power-up, the W196 initializes
with default register settings. Therefore, the use of this serial
data interface is optional. The serial interface is write-only (to
the clock chip) and is the dedicated function of device pins
SDATA and SCLOCK. In motherboard applications, SDATA
and SCLOCK are typically driven by two logic outputs of the
W196
chipset. Clock device register changes are normally made
upon system initialization, if required. The interface can also
be used during system operation for power management functions. Table 2 summarizes the control functions of the serial
data interface.
Operation
Data is written to the W196 in ten bytes of eight bits each.
Bytes are written in the order shown in Table 3.
Table 2. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable
Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.
Unused outputs are disabled to reduce EMI and
system power. Examples are clock outputs to unused PCI slots.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections beyond
the selections that are provided by the FS0:1 pins.
Frequency is changed in a smooth and controlled
fashion.
For alternate microprocessors and power management options. Smooth frequency transition allows CPU frequency change under normal system
operation.
Output Three-state
Puts all clock outputs into a high-impedance state. Production PCB testing.
Test Mode
All clock outputs toggle in relation to X1 input, in- Production PCB testing.
ternal PLL is bypassed. Refer to Table 4.
(Reserved)
Reserved function for future device revision or pro- No user application. Register bit must be written
duction device testing.
as 0.
Table 3. Byte Writing Sequence
Byte
Sequence
Byte Name
1
Slave Address
11010010
Commands the W196 to accept the bits in Data Bytes 3–6 for internal
register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for
each potential receiver. The slave receiver address for the W196 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
2
Command
Code
Don’t Care
Unused by the W196, therefore bit values are ignored (“don’t care”). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed
slave receiver on the serial data bus.
3
Byte Count
Don’t Care
Unused by the W196, therefore bit values are ignored (“don’t care”). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave
receiver on the serial data bus.
4
Data Byte 0
Don’t Care
Refer to Cypress SDRAM drivers.
5
Data Byte 1
6
Data Byte 2
7
Data Byte 3
Refer to Table 4
8
Data Byte 4
The data bits in these bytes set internal W196 registers that control device
operation. The data bits are only accepted when the Address Byte bit
sequence is 11010010, as noted above. For description of bit control
functions, refer to Table 4, Data Byte Serial Configuration Map.
9
Data Byte 5
10
Data Byte 6
Document #: 38-07170 Rev. *A
Bit Sequence
Byte Description
Page 4 of 12
PRELIMINARY
Writing Data Bytes
Each bit in the data bytes control a particular device function
except for the “reserved” bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
7. Table 4 gives the bit formats for registers located in Data
Bytes 3–6.
W196
Table 5 details additional frequency selections that are available through the serial data interface.
Table 6 details the select functions for Byte 3, bits 1 and 0.
Table 4. Data Bytes 3–6 Serial Configuration Map
Affected Pin
Bit(s)
Pin No.
Pin Name
Data Byte 3
7
--6
--5
--4
--3
---
2
1–0
Data Byte 4
7
6
5
4
3
2
1
0
Data Byte 5
7
6
5
4
3
2
1
0
Data Byte 6
7
6
5
4
3
2
1
0
Bit Control
Control Function
SEL_3
SEL_2
SEL_1
SEL_0
Frequency Table
Selection
(Reserved)
Bit 1 Bit 0
0
0
0
1
1
0
1
1
0
1
Refer to Table 5
Refer to Table 5
Refer to Table 5
Refer to Table 5
Frequency Controlled Frequency Controlled
by external FS0:1 pins by BYT3 SEL_(3:0)
(Table 1)
Table 5
--Function (See Table 6 for function details)
Spread Spectrum Off
Test Mode
Spread Spectrum On (default)
All Outputs Three-stated
Default
0
0
0
0
0
---
---
0
10
-14
---21
-22
-24/48MHz
---CPU1
-CPU0
(Reserved)
Clock Output Disable
(Reserved)
(Reserved)
(Reserved)
Clock Output Disable
(Reserved)
Clock Output Disable
-Low
---Low
-Low
-Active
---Active
-Active
0
1
0
0
0
1
0
1
4
11
10
8
7
6
5
PCI_F
PCI6
PCI5
-PCI4
PCI3
PCI2
PCI1
Clock Output Disable
Clock Output Disable
Clock Output Disable
(Reserved)
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
Low
-Low
Low
Low
Low
Active
Active
Active
-Active
Active
Active
Active
1
1
1
0
1
1
1
1
--24
---27
27
--IOAPIC
---REF2X
REF2X
(Reserved)
(Reserved)
Clock Output Disable
(Reserved)
(Reserved)
(Reserved)
Clock Output Disable
Clock Output Disable
--Low
---Low
Low
--Active
---Active
Active
0
0
1
0
0
0
1[1]
1[1]
Note:
1. Bits 0 and 1 of Data Byte 6 in Table 4 must be programmed as the same value.
Document #: 38-07170 Rev. *A
Page 5 of 12
PRELIMINARY
W196
Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes
Input Conditions
Data Byte 3, Bit [7:4, 1:0]
Output Frequency
If Spread Is On
Bit [1:0]
Bit 7
SEL_3
Bit 6
SEL_2
Bit 5
SEL_1
Bit 4
SEL_0
CPU, SDRAM
Clocks (MHz)
PCI Clocks
(MHz)
Spread Percentage
00
0
0
0
0
78
39
OFF
00
0
0
0
1
81
40.5
OFF
00
0
0
1
0
113.5
37.8
OFF
00
0
0
1
1
66.8
33.4
OFF
00
0
1
0
0
117
39
OFF
00
0
1
0
1
118.5
39.5
OFF
00
0
1
1
0
122
37.3
OFF
00
0
1
1
1
100
33.3
OFF
00
1
0
0
0
126
31.5
OFF
00
1
0
0
1
135
33.75
OFF
00
1
0
1
0
137
34.25
OFF
00
1
0
1
1
138.5
34.62
OFF
00
1
1
0
0
142
35.5
OFF
00
1
1
0
1
144
36
OFF
00
1
1
1
0
155
38.75
OFF
00
1
1
1
1
133.3
33.3
OFF
10
0
0
0
0
124
41.3
±0.5% Center
10
0
0
0
1
75
37.5
±0.5% Center
10
0
0
1
0
83.3
41.65
±0.5% Center
10
0
0
1
1
66.8
33.4
±0.5% Center
10
0
1
0
0
90
30
±0.5% Center
10
0
1
0
1
112
37.3
±0.5% Center
10
0
1
1
0
95
31.67
±0.5% Center
10
0
1
1
1
100
33.3
±0.5% Center
10
1
0
0
0
120
40
±0.5% Center
10
1
0
0
1
115
38.3
±0.5% Center
10
1
0
1
0
110
36.67
±0.5% Center
10
1
0
1
1
105
35
±0.5% Center
10
1
1
0
0
140
35
±0.5% Center
10
1
1
0
1
150
37.5
±0.5% Center
10
1
1
1
0
124
31
±0.5% Center
10
1
1
1
1
133.3
33.3
±0.5% Center
Table 6. Select Function for Data Byte 3, Bits 0:1
Input Conditions
Output Conditions
Data Byte 3
Bit 1
Bit 0
CPU0:1
PCI_F, PCI1:6
REF2X,
IOAPIC
48MHZ
24MHZ
Spread Spectrum OFF
0
0
Note 2
Note 2
14.318 MHz
48 MHz
24 MHz
Test Mode
0
1
X1/2
CPU/2, 3, or 4
X1
X1/2
X1/4
Spread Spectrum ON (default)
1
0
±0.5%
±0.5%
14.318 MHz
48 MHz
24 MHz
Three-state
1
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Function
Note:
2. CPU and PCI frequency selections are listed in Table 1 and Table 5.
Document #: 38-07170 Rev. *A
Page 6 of 12
PRELIMINARY
W196
Absolute Maximum Ratings[3]
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
Parameter
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.
Description
Rating
Unit
V
VDD, VIN
Voltage on any pin with respect to GND
–0.5 to +7.0
–65 to +150
°C
0 to +70
°C
–55 to +125
°C
2 (min.)
kV
TSTG
Storage Temperature
TA
Operating Temperature
TB
Ambient Temperature under Bias
ESDPROT
Input ESD Protection
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Supply Current
IDDQ3
Combined 3.3V Supply Current
CPU0:1 =100 MHz
Outputs Loaded[4]
85
mA
IDDQ3
Combined 2.5V Supply Current
CPU0:1 =100 MHz
Outputs Loaded[4]
30
mA
Logic Inputs
VIL
Input Low Voltage
GND – 0.3
0.8
V
VIH
Input High Voltage
2.0
VDD + 0.3
V
[5]
–25
µA
[5]
10
µA
50
mV
IIL
IIH
Input Low Current
Input High Current
Clock Outputs
VOL
Output Low Voltage
VOH
Output High Voltage
VOH
Output High Voltage
IOL
Output Low Current
IOH
Output High Current
IOL = 1 mA
IOH = –1 mA
3.1
V
CPU0:1/IOAPIC
IOH = –1 mA
2.2
V
CPU0:1
VOL = 1.25V
45
60
80
mA
PCI_F, PCI1:6
VOL = 1.5V
85
110
140
mA
IOAPIC
VOL = 1.25V
65
90
140
mA
REF2X
VOL = 1.5V
110
140
170
mA
48MHz, 24MHz
VOL = 1.5V
50
70
90
mA
CPU0:1
VOL = 1.25V
35
50
80
mA
PCI_F, PCI1:6
VOL = 1.5V
60
95
130
mA
IOAPIC
VOL = 1.25V
45
87
140
mA
REF2X
VOL = 1.5V
100
130
150
mA
48MHz, 24MHz
VOL = 1.5V
50
70
90
mA
Crystal Oscillator
VTH
X1 Input Threshold Voltage[6]
CLOAD
Load Capacitance, as seen by
External Crystal[7]
CIN,X1
X1 Input Capacitance[8]
VDDQ3 = 3.3V
Pin X2 unconnected
1.65
V
14
pF
28
pF
Notes:
3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required
4. All clock outputs loaded with maximum lump capacitance test load specified in the AC Electrical Characteristics section.
5. W196 logic inputs have internal pull-up resistors, except SEL100/66# (pull-ups not full CMOS level).
6. X1 input threshold voltage (typical) is VDD/2.
7. The W196 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is
14 pF; this includes typical stray capacitance of short PCB traces to crystal.
8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
Document #: 38-07170 Rev. *A
Page 7 of 12
PRELIMINARY
W196
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5% (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
5
pF
Pin Capacitance/Inductance
CIN
Input Pin Capacitance
Except X1 and X2
COUT
Output Pin Capacitance
6
pF
LIN
Input Pin Inductance
7
nH
AC Electrical Characteristics
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%,VDDQ2 = 2.5V± 5%, fXTL = 14.31818 MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output; Spread Spectrum clocking is disabled.
CPU Clock Outputs, CPU0:1 (Lump Capacitance Test Load = 20 pF)
CPU = 66.8 MHz
Parameter
Description
Test Condition/Comments
CPU = 100 MHz
Min. Typ. Max. Min.
Period
Measured on rising edge at 1.25V
15
tH
High Time
Duration of clock cycle above 2.0V
5.2
3.0
ns
tL
Low Time
Duration of clock cycle below 0.4V
5.0
2.8
ns
tR
Output Rise Edge Rate Measured from 0.4V to 2.0V
1
4
1
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.0V to 0.4V
1
4
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at
1.25V
45
55
45
55
%
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.25V. Maximum difference of cycle time between
two adjacent cycles.
200
250
ps
tSK
Output Skew
Measured on rising edge at 1.25V
175
175
ps
fST
Frequency Stabilization from Power-up
(cold start)
Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
3
3
ms
Zo
AC Output Impedance
Average value during switching transition. Used for determining series termination value.
Document #: 38-07170 Rev. *A
15.5
Typ. Max. Unit
tP
20
10
10.5
20
ns
Ω
Page 8 of 12
PRELIMINARY
W196
PCI Clock Outputs, PCI1:6 and PCI_F (Lump Capacitance Test Load = 30 pF
CPU = 66.8/100 MHz
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
tP
Period
Measured on rising edge at 1.5V
30
ns
tH
High Time
Duration of clock cycle above 2.4V
12
ns
tL
Low Time
Duration of clock cycle below 0.4V
12
ns
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.
250
ps
tSK
Output Skew
Measured on rising edge at 1.5V
500
ps
tO
CPU to PCI Clock Skew
Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
4
ns
fST
Frequency Stabilization
Assumes full supply voltage reached within 1 ms
from Power-up (cold start) from power-up. Short cycles exist prior to frequency
stabilization.
3
ms
Zo
AC Output Impedance
1
Average value during switching transition. Used for
determining series termination value.
Ω
20
IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 66.8/100 MHz
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
14.31818
Unit
f
Frequency, Actual
Frequency generated by crystal oscillator
MHz
tR
Output Rise Edge Rate
Measured from 0.4V to 2.0V
1
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.0V to 0.4V
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.25V
45
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
55
%
1.5
ms
Ω
15
REF2X Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 66.8/100 MHz
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Frequency, Actual
Frequency generated by crystal oscillator
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
fST
Frequency Stabilization from
Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
3
ms
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Document #: 38-07170 Rev. *A
14.318
Unit
f
15
MHz
Ω
Page 9 of 12
PRELIMINARY
W196
48-MHZ and 24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min.
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
fD
Deviation from 48 MHz
(48.008 – 48)/48
m/n
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Typ.
Max.
Unit
48.008
24.004
MHz
+167
ppm
57/17, 57/34
2
V/ns
0.5
2
V/ns
45
55
%
3
ms
25
Ω
Ordering Information
Ordering Code
Package
Name
W196
Document #: 38-07170 Rev. *A
G
Package Type
28-pin SOIC (300 mils)
Page 10 of 12
PRELIMINARY
W196
Package Diagram
28-Pin Small Outline Integrated Circuit (SOIC, 300 mils)
Document #: 38-07170 Rev. *A
Page 11 of 12
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
W196
Document Title: W196 Spread Spectrum FTG for 440BX And VIA Apollo Pro-133
Document Number: 38-07170
Issue
Date
Orig. of
Change
110280
11/05/01
SZV
Change from Spec number: 38-00842 to 38-07170
122811
12/15/02
RBI
Add Power up Requirements to Maximum Ratings Information
REV.
ECN NO.
**
*A
Document #: 38-07170 Rev. *A
Description of Change
Page 12 of 12