ETC W528S08

W528XXX
ADPCM VOICE SYNTHESIZER
(Power Speech )TM
GENERAL DESCRIPTION
The W528xxx family are programmable speech synthesis ICs that utilize the ADPCM coding method
to generate all types of voice effects.
The W528xxx's LOAD and JUMP commands and four programmable registers provide powerful userprogrammable functions that make this chip suitable for an extremely wide range of speech IC
applications.
The W528xxx family includes 12 kinds of bodies which are the same except for the voice duration
shown below:
BODY
W528S03
W528S05
W528S08
W528S10
W528S12
W528S15
Second
3 Sec
5 Sec
8 Sec
10 Sec
12 Sec
15 Sec
BODY
W528S20
W528S25
W528S30
W528S40
W528S50
W528S60
Second
20 Sec
25 Sec
30 Sec
40 Sec
50 Sec
60 Sec
Note: The voice durations are estimated by 6.4KHz sampling rate.
FEATURES
•
Programmable speech synthesizer
•
Wide operating voltage range: 2.4 to 5.5 volts
•
4-bit ADPCM synthesis method
•
Provides 4 direct trigger inputs that can easily be extended to 8 or 12 matrix trigger inputs
•
Two trigger input debounce times (50 mS or 400 µS) can be set
•
Provides up to 2 LEDs and 3 STOP outputs
•
Every LED pin can drive 3 LEDs simultaneously
•
LED flash frequency: 3 Hz
•
AUD output current: 5 mA
•
Flexible functions programmable through the following:
− LD (load), JP (jump) commands
− Four registers: R0, EN, STOP, and MODE
− Conditional instructions
− Speech equation
− END instruction
− Global repeat (GR) setting
− Output frequency and LED flash type setting
•
Programmable power-on initialization (POI) (can be interrupted by trigger inputs)
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Publication Release Date: March 1999
Revision A1
W528XXX
•
•
POI delay time of 160 mS ensures stable voltage when chip is powered on
Can be programmed for the following functions:
− Interrupt or non-interrupt for rising or falling edge of each trigger pin (this feature determines
retriggerable, non-retriggerable, overwrite, and non-overwrite features of each trigger pin)
− Four playing modes:
One Shot (OS)
Level Hold (LH)
Single-cycle level hold (S_LH)
Complete-cycle level hold (C_LH)
•
•
•
•
− Stop output signal setting
− Serial, direct, or random trigger mode setting
Four frequency options (4/4.8/6/8 KHz) and LED On/Off control can be set independently in each
GO instruction of speech equation
Independent control of LED1 and LED2
Total of 256 voice group entries available for programming
Provides the following mask options:
− LED flash type: synchronous/alternate
− LED1 section-controlled: Yes/No
− LED2: section-controlled/STPC-controlled
− LED volume-controlled: No/Yes
PAD CONFIGURATIONS
W528S15-60
W528S03-12
TEST4
TEST
OSC
TG1
VDD
TG2
VSS
TG3
SPK
TG1
OSC
TG2
VDD
TG3
TEST3
VSS
TG4/LED2/STPC
TG4/LED2/STPC
LED1
LED1
STPB
STPA
STPB
-2-
STPA
TEST1 TEST2 SPK
W528XXX
PAD DESCRIPTION
PAD NAME
I/O
FUNCTION
TG1
I
Trigger Input 1
TG2
I
Trigger Input 2
TG3
I
Trigger Input 3
TG4/LED2/STPC
I/O
LED1
O
LED 1
STPB
O
Stop Signal B
STPA
O
Stop Signal A
SPK
O
Current Output for Speaker
VSS
-
Negative Power Supply
VDD
-
Positive Power Supply
OSC
I
Oscillation Frequency Control
*Test1
-
Test Pin
*Test2
-
Test Pin
*Test3
-
Test Pin
Test4
-
Test Pin
Trigger Input 4 or LED 2 or Stop Signal C
* These pads only exist in W528S15~60.
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Publication Release Date: March 1999
Revision A1
W528XXX
BLOCK DIAGRAM
OSC
TIMING
GENERATOR
DATA ROM
*TEST1
*TEST2
*TEST3
TEST4
TG1
CONTROLLER
COUNTER
& SHIFT
REGISTER
TG2
TG3
TG4/LED2/STPC
LED1
STPA
STPB
SHIFT
REGISTER
ADPCM
SYNTHESIZER
D/A
CONVERTER
VDD
SPK
VSS
* These pins only exist in W528S15~60.
FUNCTIONAL DESCRIPTION
The W528xxx family provides up to four direct trigger pins, which can be extended to eight or twelve
matrix trigger inputs, up to three stop signal output pins, an LED section control, and powerful
programmable features. The JUMP and LOAD commands and four programmable registers can be
used to program the desired playing mode, stop output signal form, LED flash type, and trigger pin
interrupt modes.
The chip's programmable features can also be used to develop new, customized functions for a wide
variety of innovative applications.
A. Instruction Set Description
This section describes three types of instructions:
•
Unconditional instructions, which are executed immediately after they are issued.
•
Conditional instructions, which are executed only when the conditions specified in the instructions
are satisfied.
•
END instruction, which is used to stop all device activity.
Instructions are programmed by writing LOAD and JUMP commands into the R0, EN, STOP, and
MODE registers.
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W528XXX
Unconditional Instructions:
1. LOAD (LD) Command:
LD R0, value:
This instruction is used to load a voice-group entry value into register R0. The voice-group entry
value may range from 0 to 255. The initial value of the R0 register is "00000000."
LD EN, operand:
This instruction is used to define the trigger interrupt settings by loading the operand message into
register EN. The initial value of the EN register is "11111111."
a. The operand is an 8-bit value that can be entered in decimal (default) or hexadecimal
(with "0x" as a prefix).
b. EN is an 8-bit register that is used to enable/disable the rising/falling edge of each of the four
trigger inputs.
The 8 bits correspond to the rising/falling edges of the triggers as shown below:
Bit:
7
6
5
4
3
2
1
0
TG:
4R
3R
2R
1R
4F
3F
2F
1F
where "nR/F" represents the rising/falling edge of the n-th trigger pin.
c. When any one of the eight bits is set to "1" (default), the corresponding trigger will interrupt the
current state at the edge indicated. When the bits are set to "0," the triggers will be disabled.
d. The voice group entry addresses correspond to the interrupt vectors as follows:
TG:
4R
3R
2R
1R
4F
3F
2F
1F
Group:
7
6
5
4
3
2
1
0
EXAMPLE:
The instruction "LD EN, 0x41" is programmed.
EXPLANATION:
a. "41" is a hexadecimal value equal to the binary value "0100 0001."
b. These 8 bits of data represent the following trigger interrupt settings:
4R,
3R,
2R,
1R,
4F,
3F,
2F,
1F








0
1
0
0
0
0
0
1
RESULT:
a. When the rising edge of TG3 (3R) is activated, the EN register will cause TG3 to interrupt the
current playing state and jump immediately to voice group 6, the voice group that corresponds
to 3R.
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Publication Release Date: March 1999
Revision A1
W528XXX
b. When the falling edge of TG1 goes active, the EN register will cause TG1 to interrupt the
current playing state and jump immediately to voice group 0, the voice group that corresponds
to 1F.
c. No action will be taken when the other trigger pins are pressed, because the corresponding bits
are set to "0."
LD STOP, operand:
This instruction loads the operand message into the STOP register to set the output levels of the stop
signals. The initial value of the STOP register is "XXXXX111."
a. This register is used to program the output levels of the three STOP signals, STPA, STPB,
and STPC. Only three of the bits in the register are used, as shown below (an "X" indicates
"Don't care"):
Bit:
7
6
5
4
3
2
1
0
Stop:
X
X
X
X
X
STPC
STPB
STPA
b. When a particular STOP bit is set to "1," The corresponding stop signal will be a high output;
when a bit is set to "0," the corresponding stop signal will be a low output.
EXAMPLE:
The instruction "LD STOP, 0x43" is programmed.
EXPLANATION:
a. "43" is a hexadecimal value equal to a binary value of "0100 0011."
b. These 8 bits of data represent the following settings:
X,

0
X,

1
X,

0
X,

0
X,

0
STPC,

0
STPB,

1
STPA

1
RESULT:
a. The STPA and STPB outputs will be high outputs.
b. The STPC signal will be a low output.
c. The sixth bit "1" is a "Don't Care" bit and so has no effect on the stop signal output
settings.
LD MODE, operand:
This instruction is used to select various operating modes. It loads an operand message into the
MODE register to select one mode from each of four pairs of modes, which correspond to bits 4
through 7 of the register (bits 0 to 3 are "Don't Care" bits). The four pairs of modes and the
corresponding bits are as follows:
Bit:
MODE:
7
Flash/DC
6
LED2/STPC
5
TG4/LED2_STPC
4
50 mS/400 µS
3
X
2
X
1
X
0
X
A "1" for one of these bits selects the first of the pair of modes indicated; a "0" selects the second of
the pair. The initial value of the mode register is "1111XXXX."
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W528XXX
EXAMPLE 1:
The four bits are programmed as "1111," so that the eight bits of the register are as follows (an "X"
indicates a "Don't Care" bit):
Flash/DC,
LED2/STPC,
TG4/LED2_STPC,
50 mS/400 µS,
X,
X,
X,
X








1
1
1
1
X
X
X
X
RESULT:
The mode settings are as follows:
a. Pin 4 (TG4/LED2_STPC) is configured as a trigger pin (TG4), and the LED2/STPC option will
be ignored.
b. The LED is set as a flash type, with a flash frequency of 3 Hz.
c. The debounce time of the trigger inputs is set to 50 mS.
EXAMPLE 2:
The four bits are programmed as "0000," so that the eight bits of the register are as follows (an "X"
indicates a "Don't Care" bit):
Flash/DC,
LED2/STPC,
TG4/LED2_STPC,
50 mS/400 µS,
X,
X,
X,
X








0
0
0
0
X
X
X
X
RESULT:
The mode settings are as follows:
a. Pin 4 (TG4/LED2_STPC) is configured as either the LED2 or STPC output (determined by bit 6,
LED2/STPC; see next item).
b. Pin 4 is configured as the STPC output pin.
c. LED will be lit constantly during operation.
d. The debounce time of the trigger inputs is set as 400 µS.
2. JUMP (JP) Command:
JP value: Instructs device to jump directly to the voice group corresponding to the value indicated.
The voice group value may range from 0 to 127 (direct jump).
JP R0: Instructs device to jump to whatever voice group is indicated by the value currently stored in
register R0, from 0 to 255 (indirect jump).
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Publication Release Date: March 1999
Revision A1
W528XXX
Conditional Instructions:
Conditional instructions are executed only when the conditions specified in the instructions hold. The
conditional instructions are listed below. An explanation of the notation used in the instructions
follows.
(Note: There are no conditional instructions for LD MODE.)
LD R0, VALUE @LAST: VALUE can be set from 0 to 255.
LD R0, VALUE @TGn_STATUS: VALUE can be set from 0 to 255.
LD EN, OPERAND @LAST: EN - 4R, 3R, 2R, 1R, 4F, 3F, 2F, 1F.
LD STOP, OPERAND @LAST: STOP - X, X, X, X, X, STPC, STPB, STPA.
JP VALUE @LAST: VALUE can be set from 0 to 127.
JP R0 @LAST
JP VALUE @TGn_STATUS: VALUE can be set from 0 to 127
JP R0 @TGn_STATUS
EXPLANATION:
@LAST: At last time of global repeat.
@TGn_STATUS: When the status of the trigger specified (TGn) is in the condition specified,
where the possible triggers and conditions are the following:
TG1_HIGH
TG1_LOW
TG2_HIGH
TG2_LOW
TG3_HIGH
TG3_LOW
TG4_HIGH
TG4_LOW
End Instruction:
END: This command instructs the chip to cease all activity immediately.
B. Program Structure Features and Execution Rules
1. There are eight hardware group entry points and 248 software group entry points, as follows:
Group
8 H/W entries:
TG1F:
0
TG2F:
1
TG3F:
2
TG4F:
3
TG1R:
4
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W528XXX
(Continued)
TG2R:
5
TG3R:
6
TG4R:
7
248 S/W entries:
8
9
.
.
.
POI:
32
33
.
.
.
254
255
2. Execution begins from group entry and is terminated by END instruction.
3. A H/W trigger interrupt stops the group currently being executed immediately and begins a new
group.
C. Mask Options
There are four mask options for the W528xxx family; the mask options are used to select features
that cannot be programmed through the chip's registers.
The options are the following:
LED flash type (synchronous/alternate)
LED volume-controlled: No/Yes
LED1 section-controlled: Yes/No
LED2: section-controlled/STPC-controlled
D. Speech Equation Description
The format of the speech equations for the W528xxx family is the same as that of the equations used
in the Winbond W52160, W525XX, and W527XX series speech ICs. The following is an example of
the speech equation format:
GR = N
H4+m1*SOUND1_FL+m2*SOUND2_FL+[1FFFF]+...+T4
END
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Publication Release Date: March 1999
Revision A1
W528XXX
where
GR = N defines the number of global repeats (from 1 to 16);
m1 and m2 define the number of local repeats (from 1 to 7);
SOUND1 and SOUND2 are the *.WAM files of ADPCM converted voice data;
_FL is the section control setting, for which the parameters F and L are as follows:
F: Voice output frequency setting:
0 = 4 KHz, 1 = 4.8 KHz, 2 = 6 KHz, 3 = 8 KHz;
L: LED output setting:
1: ON
0: OFF; and
[1FFFF] is a period of silence of length 1FFFF;
H4, T4: Represent head and tail ADPCM files, respectively.
E. Programmable Power-on Initialization
Whenever the W528xxx is powered on, the program contained in the 32nd voice group will be
executed after the power-on delay (about 160 mS), so the user can write a program into this group to
set the power-on initial state. If the user does not wish to execute a program at power-on, an "END"
instruction should be entered in group 32. The W528xxx power-on initialization process can be
interrupted by trigger inputs.
F. Progamming Examples
This section presents several examples of how the functions of the W528xxx may be programmed.
Customer programs should be written in ASCII code using a text editor; after compiling, the sound
effects resulting from the programs can be tested using a Winbond demo board.
EXAMPLE1: Four playing mode settings:
a. One-Shot Trigger Mode
0: LD EN, 0x01
; Enable TG1 falling edge input only.
H4 + sound1 + T4
END
The timing diagram for this example is shown below:
case 1:
case 2:
TG1:
TG1:
AUD:
Sound 1
AUD:
- 10 -
Sound 1
W528XXX
b.
Level-Hold Trigger Mode
0:
LD EN, 0x11
; Enable TG1 rising/falling edge input.
H4 + sound1 + T4
4:
JP 0
; Repeat sound1 until TG1 key released.
END
; As soon as TG1 key is released, execute this group entry.
The timing diagram is shown below:
case 2:
case 1:
TG1:
TG1:
AUD:
AUD:
Sound 1
Stop Immediately
c.
Complete-Cycle Level Hold
0:
LD EN, 0x01
Stop Immediately
; Enable TG1 falling edge only.
H4 + sound1 + T4
JP 0 @TG1_LOW
; If TG1 status is low level voltage (trigger is pressed), then j ump
to 0;
if not, execute next instruction (END).
END
The timing diagram is shown below:
case 1:
case 2:
TG1:
AUD:
TG1:
Sound 1
AUD:
d.
Single-Cycle Level Hold
0:
LD EN, 0x11
Sound 1
Sound 1
; Enable both falling and rising edge input of TG1.
H4 + sound1 + T4
END
•
•
•
4:
END
; As soon as TG1 is key released, execute this group entry.
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Publication Release Date: March 1999
Revision A1
W528XXX
The timing diagram is shown below:
case 2:
case 1:
TG1:
TG1:
AUD:
AUD:
Sound 1
Stop Immediately
EXAMPLE 2: Retriggerable and Non-retriggerable setting
a. Retriggerable:
0: LD EN, 0x01
; 0x01 = 00000001B, only TG1 falling edge interrupt is enabled.
END
•
•
•
END
The timing diagram is shown below:
TG1:
AUD:
Sound 1
Sound 1
Restart
Restart
b. Non-retriggerable:
0: LD EN, 0x00
; 0x00 = 00000000B, TG1 falling edge interrupt is disabled.
•
•
LD EN, 0x11
; Recover the TG1 falling and rising edge interrupt is enabled.
END
The timing diagram is shown below:
TG1:
AUD:
Sound 1
Sound 1
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W528XXX
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
CONDITIONS
RATED VALUE
UNIT
Power Supply
VDD−VSS
-
-0.3 to +7.0
V
Input Voltage
VIN
All Inputs
VSS -0.3 to VDD +0.3
V
Storage Temp.
TSTG
-
-55 to +150
°C
Operating Temp.
TOPR
-
0 to +70
°C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
ELECTRICAL CHARACTERISTICS
(TA = 25° C, VSS = 0 V)
PARAMETER
SYM.
CONDITIONS
LIMITS
UNIT
MIN.
TYP.
MAX.
Operating Voltage
VDD
-
2.4
3
5.5
V
Input Voltage
VIL
All Input Pins
VSS
-0.3
-
0.3
VDD
V
0.7 VDD
-
VDD
VIH
Standby Current
Operating Current
IDD1
VDD = 3V, No Playing
-
-
0.2
IDD2
VDD = 5V, No Playing
-
-
0.4
IOP1
VDD = 3V, No Load
-
-
400
µA
µA
IOP2
VDD = 5V, No Load
-
-
800
Input Current for TG1−TG4
IIN
VDD = 3V, VIN = 0V
-
-
-6
µA
SPK (D/A Full Scale)
IO1
VDD = 4.5V, RL = 100 Ω
-4.0
-5.0
-6.0
mA
Output Current of STPC
IOL
VDD = 3V, VOUT = 0.4V
1
-
-
mA
IOH
VDD = 3V, VOUT = 2.7V
-0.5
-
-
LED1
Output
LED2
Current
STPA
STPB
Oscillation Freq.
Oscillation Freq. Deviation
by Voltage Drop
Input Debounce Time
IO
VDD = 3V, VOUT = 1V
10
-
-
VDD = 4.5V, VOUT = 1V
15
-
-
IOL
VDD = 3V, VOUT = 0.4V
1
3
-
IOH
VDD = 3V, VOUT = 2.7V
-1
-3
-
FOSC
VDD = 3V, ROSC = Typ.
2.7
3
3.3
VDD = 4.5V, ROSC =
Typ.
2.7
3
3.3
0
4
7.5
%
mA
MHz
FOSC
F(3V) − F(2.4V)
F(3V)
TDEB1
FOSC = 3 MHz,
50
-
-
mS
TDEB2
SR = 6 KHz
400
-
-
µS
∆FOSC
Note: Rosc = 430K Ohm for all bodies in W528xxx besides W5280 (ROSC = 1.2M ohm).
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Publication Release Date: March 1999
Revision A1
W528XXX
TYPICAL APPLICATION CIRCUIT
V DD
TG1
Rosc
OSC
TG2
V DD
TG3
TG4/LED2/STPC
LED1
R
39/100 ohm
STPB
Speaker
8 ohm
1/4 watt
STPA
SPK
V SS
8050 D
C
Rs
Notes:
1. In principle, the playing speed determined by ROSC should correspond to the sampling rate during the coding phase.
The playing speed may be adjusted by varying ROSC, however.
2. Rs is an optional current-dividing resistor. If Rs is added, the resistance should be between 470 and 750Ω.
3. Cs is optional.
4. The DC current gain β of transistor 8050 ranges from 120 to 200.
5. All unused trigger pins can be left open because of their internal pull-high resistance.
6. R is used to limit the current on the LED. Case 1: VDD = 3V, R = 39Ω for 1/2/3 LEDs.
Case 2: VDD = 4.5V, R = 39Ω for 2/3 LEDs and R = 100Ω for 1 LED.
7. No warranty for production.
SUPPLEMENT
A. Power Bouncing
If an irregularity (such as bouncing) occurs in the power supply to VDD, as shown in the diagram, the
W528xxx may hang or the logic state machine may lock up. To return the chip to normal operation,
short VDD and VSS for the W528xxx and then release again.
Power bouncing
VDD
Power on
Power on reset
W528xxx
- 14 -
Battery
W528XXX
B. Trigger Pin Coupling Effect
The trigger pins (TG1−TG4) are built-in 500 KΩ pull high resistor.
If the wire of the input trigger is very close to the speaker wire in the application environment, the
coupling effect will occur. The input voltage of the trigger pin will be unstable, causing the trigger
operation to become abnormal.
An external pull high resistor (Ri) connecting the trigger pin and VDD can resolve this problem. The
value of the Ri depends on your application environment.
VDD
Ri
TGn
SPK
VDD
Headquarters
Winbond Electronics (H.K.) Ltd.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792697
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
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Publication Release Date: March 1999
Revision A1