Preliminary Data Sheet W6694A USB-ISDN S/T-Controller W6694A USB Bus ISDN S/T-Controller Preliminary Data Sheet -1Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller The information described in this document is the exclusive intellectual property of Winbond Electronics Corp and shall not be reproduced without permission from Winbond. Winbond is providing this document only for reference purposes for W6694A-based system design. Winbond assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. -2Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller Revision History Revision Date 1 October 2000 1.01 March 2001 1.02 April 2001 Descriptions First release. 1. Remove USB to USB loop back function from USBB1RS and USBB2ES registers. 2. Add EEPROM read/write function. Modify ISTA register, add data and address registers. 3. Add B channel auto mode in CTL register. 4. Pin Description: Change hardware reset circuit power from VDD to 3.3V. R1 changed from 10 k£ [to 22 k£ [. 5. Pin Description: Add IO0-7 current values. 6. DC Characteristics: Add ICC current values. Add microcontroller function and description. -3Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller TABLE OF CONTENTS 1. GENERAL DESCRIPTION ........................................................................................................... 7 2. FEATURES................................................................................................................................... 7 3. PIN CONFIGURATION................................................................................................................. 8 4. PIN DESCRIPTION....................................................................................................................... 9 5. SYSTEM DIAGRAM AND APPLICATIONS ............................................................................... 11 6. BLOCK DIAGRAM ..................................................................................................................... 12 7. FUNCTIONAL DESCRIPTIONS ................................................................................................. 13 7.1 Microcontroller .......................................................................................................................................................... 13 7.1.1 Special function register (SFR) ............................................................................................................................ 13 7.2 USB ........................................................................................................................................................................... 14 7.2.1 Control-IN Transactions (Endpoint 0).................................................................................................................. 15 7.2.2 Control-OUT Transactions (Endpoint 0).............................................................................................................. 17 7.2.3 Bulk-OUT Transaction (Endpoint 1).................................................................................................................... 18 7.2.4 Bulk-IN Transaction (Endpoint 2) ....................................................................................................................... 19 7.2.5 Interrupt-IN Transaction (Endpoint 3) ................................................................................................................. 19 7.2.6 Isochronous-OUT Transaction (Endpoint 4) ........................................................................................................ 19 7.2.7 Isochronous-IN Transaction (Endpoint 5) ............................................................................................................ 20 7.2.8 Suspend and Resume ........................................................................................................................................... 21 7.3 EEPROM Configuration............................................................................................................................................. 23 7.3.1 EEPROM wire connection ................................................................................................................................... 23 7.3.2 EEPROM Contents.............................................................................................................................................. 23 8. REGISTER DESCRIPTIONS ...................................................................................................... 24 8.1 Interrupt Registers...................................................................................................................................................... 24 8.1.1 Interrupt Status Register ISTA Read_clear ..................................................................................................... 24 8.1.2 Layer 1 Command/Indication Register CIR Read ............................................................................................. 24 8.1.3 PIO Input Change Register PICR Read_clear ................................................................................................. 25 8.1.4 Monitor Channel Interrupt Status MOIR Read_clear ....................................................................................... 25 8.2 Chip and FIFO Control Registers ............................................................................................................................... 25 8.2.1 Interrupt Mask Register IMASK Read/Write Address 00h .............................................................................. 25 8.2.2 Command Register 1 CMDR1 Write Address 01h ........................................................................................ 26 8.2.3 Command Register 2 CMDR2 Write Address 02h ........................................................................................ 27 8.2.4 Control Register CTL Read/Write Address 03h ............................................................................................ 27 8.2.5 Layer 1 Command/Indication Register CIX Read/Write Address 04h ............................................................... 28 -4Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller 8.2.6 U-layer1 Ready Code L1_RC Read/Write Address 05h.................................................................................. 28 8.3 GCI Mode Registers ................................................................................................................................................... 28 8.3.1 GCI Mode Command Register GCR Read/Write Address 06h......................................................................... 28 8.3.2 Monitor Channel Control Register MOCR Read/Write Address 07h................................................................. 29 8.3.3 Monitor Channel Receive Register MOR Read Address 08h .......................................................................... 30 8.3.4 Monitor Channel Transmit Register MOX Read/Write Address 09h................................................................ 30 8.4 Programmable IO Registers........................................................................................................................................ 30 8.4.1 PIO Input Enable Register PIE Read/Write Address 0Ah ............................................................................... 30 8.4.2 PIO Output Register 1 PO1 Read/Write Address 0Bh ................................................................................... 30 8.4.3 PIO Output Register 2 PO2 Read/Write Address 0Ch ................................................................................... 31 8.4.4 PIO Data Register PDATA Read Address 0Dh ............................................................................................. 31 8.5 B Channel Switch Registers ....................................................................................................................................... 31 8.5.1 Layer1 B1 Receiver Select Register L1B1RS Read/Write Address 0Eh ............................................................ 31 8.5.2 Layer1 B2 Receiver Select Register L1B2RS Read/Write Address 0Fh ............................................................ 31 8.5.3 USB B1 Receiver Select Register USBB1RS Read/Write Address 10h............................................................. 32 8.5.4 USB B2 Receiver Select Register USBB2RS Read/Write Address 11h............................................................. 32 8.5.5 PCM1 Receiver Select Register PCM1RS Read/Write Address 12h ................................................................. 32 8.5.6 PCM2 Receiver Select Register PCM2RS Read/Write Address 13h ................................................................. 33 8.6 EEPROM Access Registers......................................................................................................................................... 33 8.6.1 EEPROM Read/Write Address EPADR Write Address 14h ............................................................................ 33 8.6.2 EEPROM Read Data Low Byte EPRDL Read Address 15h............................................................................. 34 8.6.3 EEPROM Read Data High Byte EPRDH Read Address 16h ........................................................................... 34 8.6.4 EEPROM Write Data Low Byte EPWDL Write Address 17h.......................................................................... 34 8.6.5 EEPROM Write Data High Byte EPWDH Write Address 18h......................................................................... 34 9. ELECTRICAL CHARACTERISTICS .......................................................................................... 34 9.1 Absolute Maximum Rating......................................................................................................................................... 34 9.2 Power Supply ............................................................................................................................................................. 35 9.3 DC Characteristics ..................................................................................................................................................... 35 9.4 Preliminary Switching Characteristics........................................................................................................................ 37 9.4.1 PCM Interface Timing......................................................................................................................................... 37 9.4.2 Serial EEPROM Timing ...................................................................................................................................... 39 10. PACKAGE INFORMATION ..................................................................................................... 40 11. ORDERING INFORMATION..................................................................................................... 42 LIST OF FIGURES FIGURE 3.1 PIN OUT........................................................................................................................................................... 8 FIGURE 5.1 USB TA ORCAD SCHEMATIC ..................................................................................................................... 11 FIGURE 6.1 BLOCK DIAGRAM ........................................................................................................................................ 12 LIST OF TABLES TABLE 4.1 PIN DESCRIPTIONS ......................................................................................................................................... 9 -5Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller TABLE 7.1 W6694A SPECIFIED SFR................................................................................................................................ 13 TABLE 7.2 USB ENDPOINTS............................................................................................................................................ 14 -6Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller 1. GENERAL DESCRIPTION The Winbond's single chip USB bus ISDN S/T interface controller W6694A is an all-in-one device suitable for ISDN Internet access. With internal microprocessor, the integrated USB and ISDN design provides low cost solution for USBIDSN application. W6694A also provides two PCM CODEC interfaces for the ability to access ISDN through voice channel. 2. FEATURES ISDN • Full duplex 2B+D S/T-interface transceiver compatible with ITU-T I.430 Recommendation ♦ Four wire operation ♦ Received clock recovery ♦ Layer 1 activation/deactivation procedure ♦ D channel access control • Transparent data transmission of 2B+D channels • Test functions USB • USB Specification version 1.0/1.1 compliant • Full-speed, bus-powered USB device • Integrated transceiver, PLL, SIE, SIL, and voltage regulator • Built-in fully automatic enumeration procedure • Support suspend mode ♦ Suspend current requirement ♦ Wake-up by ISDN (remote) and PC (host) Microcontroller • Built-in programmable microcontroller for internal data transfer between USB, and ISDN/GCI/PCM interface Others • • • • • • GCI bus interface (slave mode) for connecting to ISDN U transceiver chip PCM port provides two 64K clear channels to connect to PCM CODEC chips B channel data switching function for selective connection between ISDN/GCI interface, USB, and PCM port EEPROM interface for retrieving/saving customized data dynamically IO pins with LED current drive capability Reset pin for whole-chip reset -7Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller 3. PIN CONFIGURATION V S S U 36 N C S U S P I O P 7 I O P 6 I O P 5 I O P 4 I O P 3 I O P 2 I O P 1 I O P 0 R E S E T # 35 34 33 32 31 30 29 28 27 26 25 VDDU 37 24 VDD23 D+ 38 23 VSS23 D- 39 22 TEST2# VDD3 40 21 TEST1# UCLK1 41 20 EPDO UCLK2 42 19 EPDI VDD3I 43 18 EPSK VSS1 44 17 EPCS SR1 45 16 PRXD SR2 46 15 PTXD VDD1 47 14 VDD22 SX1 48 13 VSS22 1 2 3 4 5 6 7 8 9 10 11 12 S X 2 X T A L 1 X T A L 2 V S S 2 1 V D D 2 1 G C I D C L G C I F S C G C I D D G C I D U P F C K 1 P F C K 2 P B C K FIGURE 3.1 PIN OUT -8Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller 4. PIN DESCRIPTION TABLE 4.1 PIN DESCRIPTIONS Note: The suffix # indicates active LOW signal. Symbol D+ DUCLK1 UCLK2 SR1 SR2 SX1 SX2 XTAL1 XTAL2 GCIDCL GCIFSC GCIDD GCIDU PFCK1 PFCK2 PBCK PTXD PRXD EPCS EPSK EPDI EPDO VDD1,VSS1 VDD21,VSS21 VDD22,VSS22 Pin No. I/O Function USB Bus 38 I/O USB D+ data line 39 I/O USB D- data line 41 I 24 MHz crystal/oscillator clock input 42 O 24 MHz crystal clock output. Left unconnected if use oscillator. ISDN Signals and External Crystal 45 I S/T bus receiver input (-). This is normal polarity. Reverse polarity is also OK. 46 I S/T bus receiver input (+) 48 O S/T bus transmitter output(+) 1 O S/T bus transmitter output(-) 2 I Crystal or Oscillator clock input. The clock frequency: 7.68MHz±100PPM. 3 O Crystal clock output. Left unconnected when using oscillator. GCI Bus 6 I GCI bus data clock 1.536 MHz 7 I GCI bus frame synchronization clock 8 I GCI bus data downstream (input) 9 O GCI bus data upstream (output) PCM Bus 10 O PCM port 1 frame synchronization signal with 8 KHz repetition rate and 8 bit pulse width 11 O PCM port 2 frame synchronization signal with 8 KHz repetition rate and 8 bit pulse width 12 O PCM bit clock of 1.536 MHz 15 O PCM data output 16 I PCM data input External Serial EEPROM Interface 17 O Serial EEPROM chip select 18 O Serial EEPROM data clock 19 I Serial EEPROM data input. Internal 10k ohm pullup is provided. 20 O Serial EEPROM data output Power and Ground 47,44 I ISDN S/T analog power (5V), Ground 5,4 I Digital power (5V), Ground 14,13 -9Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller VDD23,VSS23 VDDU,VSSU VDD3 VDD3I 24,23 37,36 40 43 I O I IOP0 IOP1 IOP2 IOP3 IOP4 IOP5 IOP6 IOP7 26 27 28 29 30 31 32 33 I/O I/O I/O I/O I/O I/O I/O I/O RESET# 25 I 21,22 I SUSP 34 O NC 35 TEST1#,TEST2# USB core power (5V), Ground Regulator output (3.3V) Regulator input (3.3V) IO Pins IO pin capable of driving LED IOP0-4 : 4 mA for source or sink current IOP5-7 : 2.67 mA for source or sink current Others External reset. Cause internal circuit reset. Internal 10k ohm pull-up is provided. Test mode enable. Connected to HIGH for normal operation. USB suspended. Active HIGH NC No connection. Internal pull-up is provided. -10Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller 5. SYSTEM DIAGRAM AND APPLICATIONS Typical applications include : § USB TA for data only service § USB TA with one data plus one voice C1 10pF 1 2 3.3V Y1 J1 JP1 24MXO 36 35 34 33 32 31 30 29 28 27 26 25 DD+ VDD 2 USB_P- 3 USB_P+ 4 GND R4 USBDN 3 1 3.3V 1 1 2 GND C5 33pF 220 IOP7 IOP6 IOP5 W6694-QFP48 D2:ISDN,D3:USB D2 LED D3 LED D4 LED D5 LED D6 LED D7 LED D8 LED D9 LED R15 560 R16 560 R17 560 R18 560 R19 560 R20 560 R21 560 R22 560 33 U2 6 EPCS EPSK EPDO EPDI R5 1.5K 5 R6 USBCONN USBDP 5 768MXO VDD GND 2 4 C B_GND 1 VDD GND VDD VDD EPDO EPDI EPSK EPCS VDD IOP4 1 2 3 4 5 6 7 8 9 10 11 12 BUS_P ATACH1 SW DPDT 24 23 22 21 20 19 18 17 16 15 14 13 SX2 768MXI 768MXO GND VDD GND GND VDD USB1 7.68MHz R3 VDD23 VSS23 TEST2# TEST1# EPDO EPDI EPSK EPCS PRXD PTXD VDD22 VSS22 IOP2 GND SR1 SR2 VDD SX1 VDDU D+ DVDD3 UCLK1 UCLK2 VDD3I VSS1 SR1 SR2 VDD1 SX1 IOP1 + 37 38 39 40 41 42 43 44 45 46 47 48 IOP0 1 C6 22UF 2 C7 0.1uF 24MXI 24MXO Y2 VSSU NC SUSPEND IOP7 IOP6 IOP5 IOP4 IOP3 IOP2 IOP1 IOP0 RESET# VDD USBDP USBDN 3.3V SX2 XTAL1 XTAL2 VSS21 VDD21 GCIDCL GCIFSC GCIDD GCIDU PFCK1 PFCK2 PBCK 3.3V GND C4 33pF 1 2 2 768MXI U1 1 2 IOP3 GND SUSPEND IOP7 IOP6 IOP5 IOP4 IOP3 IOP2 IOP1 IOP0 RESETN CB5 0.1uF 1 C2 10pF 150 1 CB4 0.1uF 2 + C3 1uF 1 1 CB3 0.1uF 2 2 RESET1 TR_RST CB2 0.1uF 2 + CB1 1uF 2 RESETN 24MHz R2 1 VDD 1 R1 22K 1 D1 1N4148 2 24MXI 1 2 3 4 CS SK DI DO VCC NC NC GND 8 7 6 5 VDD GND NMC9346 DIP8 JP2 33 1 2 3 4 HEADER 4 FB1 1 SX1C 2 JP3 JUMPER R7 SX1A 1 SX1 2 FERRI BEAD D12 1N4148 SX2 1N4148 D16 D11 1N4148 D13 ISDN1 D14 1N4148 D17 1N4148 1N4148 1.8K 9 2:1 SX2A 10 SR1A R11 R10 SX2C FB2 FERRI BEAD 1 2 SR1C 1 8 2:1 FB3 2 1 SX1C 3 17 18 SX2C 4 5 SR1C 14 SR2C 1N4148 JP4 JUMPER D19 8.2K 1N4148 SR2A 11 16 15 D20 1.8K ISDN CONNECTOR R12 100 UT28615 VDD VDD FB4 SR2C R13 2 FERRI BEAD SR1A D18 GND SR2 1 2 3 4 5 6 7 8 U3 1N4148 SX2A 9.1 SR1 R8 100 VDD VDD SX1A 1N4148 R9 D15 2 D10 1 9.1 1N4148 D21 1N4148 R14 1 2 FERRI BEAD SR2A 8.2K W6694 DEMO BOARD Size Document Number 15.20X12.00 Date: Sheet 1 of 1 FIGURE 5.1 USB TA ORCAD SCHEMATIC -11Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller 6. BLOCK DIAGRAM S/T GCI ISDN Transceiver & Layer 1 Function B Serial Interface Buffer USB Transceiver & SIE & Function GCI Control EEPROM Control PCM CODEC PCM Port Control B Channel Switch IO Port Control USB Serial EEPROM IO Port SFR 80C51 Microcontroller 4K x 8 Mask ROM FIGURE 6.1 BLOCK DIAGRAM -12Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller 7. FUNCTIONAL DESCRIPTIONS 7.1 Microcontroller The embedded 8 bit microcontroller core is a standard 80C51 MCU, operate at 24 MHz clock frequency. Its main function is to transparently transfer data between USB, and ISDN/GCI/PCM interface. Data in D/B1/B2 channel is transferred as it is, without further HDLC framing processing. All interface accept D/B1/B2 channel data, except for PCM interface, which accept only B channel data. The data from each interface is first stored at individual register in the SFR (Special Function Register) of microcontroller. Then the firmware, which resides in internal Mask ROM, is executed to constantly move data between registers for different interface. The B channel receiving registers can be programmed by way of USB interface to dynamically assign the data path between interfaces. 7.1.1 Special function register (SFR) The SFRs, as in standard 80C51 architecture, reside in the upper 128 bytes of internal RAM, from address 80H to FFH. W6694A specifically assign registers among SFRs exclusively for use of internal data transfer between interfaces. SFRs are accessed by internal firmware only, and cannot be directly accessed by Bulk-OUT commands of USB interface. However, some of the Bulk-OUT commands are used by host software to control FIFOs, such as CMDR1 and CMDR2. TAble 7.1 W6694A specified SFR SFR Addr. C0 C1 C2 C3 C4 C5 C6 C9 CA CB CC CD CE Symbol INTFS L1DDR L1DDW CB1DR CB1DW CB2DR CB2DW USBDDR USBDDW USBB1DR USBB1DW USBB2DR USBB2DW Meaning Interface Status Layer 1 D Channel Data Read Layer 1 D Channel Data Write Common B 1 Channel Data Read Common B 1 Channel Data Write Common B 2 Channel Data Read Common B 2 Channel Data Write USB D Channel Data Read USB D Channel Data Write USB B 1 Channel Data Read USB B 1 Channel Data Write USB B 2 Channel Data Read USB B 2 Channel Data Write Access R R W R W R W R W R W R W Bit Addressable Yes No No No No No No No No No No No No The reset values of above registers are all 0. 7.1.1.1 Interface Status Register INTFS Read_clear Address C0h Values after reset: 00h 7 L1DRR 6 L1DWR 5 CB1RR 4 CB1WR 3 CB2RR 2 CB2WR 1 UDRR 0 UDWR -13Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller L1DRR Layer 1 D Channel Read Ready 1: A 8-bit data byte is received from D channel of ISDN Layer 1 interface (S or GCI). Software should read the data byte from L1DDR register, and then write to USBDDW register. If USB D channel RFIFO is not already enabled, this data will be lost. 0: Not ready for read. L1DWR Layer 1 D Channel Write Ready 1: A 8-bit data byte is sent to D channel of ISDN Layer 1 interface (S or GCI). Software can continue to read next data byte from L1DDR register, and then write to USBDDW register. Initially this bit is automatically set to 1, when the opening flag of a HDLC frame is received in USB D channel XFIFO, after being enabled. 0: Not ready for write. CB1RR Common B1 Channel Read Ready 1: A 8-bit data byte is received from logical B1 channel of ISDN Layer 1 interface (S or GCI), or from logical channel 1 of PCM port. Software should read the data byte from CB1DR register, and then write to USBB1DW register. If USB B1 channel RFIFO is not already enabled, this data will be lost. 0: Not ready for read. CB1WR Common B1 Channel Write Ready 1: A 8-bit data byte is sent to logical B1 channel of ISDN Layer 1 interface (S or GCI), or to logical channel 1 of PCM port. Software can continue to read next data byte from USBB1DR register, and then write to CB1DW register. Initially this bit is automatically set to 1, when the first USB B1 channel data byte is received in USB B1 channel XFIFO, after being enabled. 0: Not ready for write. CB2RR Common B2 Channel Read Ready 1: A 8-bit data byte is received from logical B2 channel of ISDN Layer 1 interface (S or GCI), or from logical channel 2 of PCM port. Software should read the data byte from CB2DR register, and then write to USBB2DW register. If USB B2 channel RFIFO is not already enabled, this data will be lost. 0: Not ready for read. CB2WR Common B2 Channel Write Ready 1: A 8-bit data byte is sent to logical B2 channel of ISDN Layer 1 interface (S or GCI), or to logical channel 2 of PCM port. Software can continue to read next data byte from USBB2DR register, and then write to CB2DW register. Initially this bit is automatically set to 1, when the first USB B2 channel data byte is received in USB B2 channel XFIFO, after being enabled. 0: Not ready for write. 7.2 USB TABLE 7.2 USB ENDPOINTS End Point 0 1 2 3 Type Direction* Control Bulk Bulk Interrupt IN/OUT OUT IN IN Max. Packet Size (Bytes) 8/8 8 8 5 Internal Buffer Type and Size (Bytes) 8, single port x 2 8, single port x 1 8, single port x 1 5, single port x 1 -14Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller 4 Isoch. OUT (1+3) + (1+18) = 23 5 Isoch. IN 1+ (1+7) + (1+15) + (1+15) = 41 * Direction: IN – device to host, OUT – host to device 96, dual port x 1 96, dual port x 1 USB standard requests are supported by W6694A, and W6694A will respond to requests according to USB specification revesion 1.1. These includes “CLEAR_FEATURE, GET_CONFIGURATION, GET_DESCRIPTOR, GET_INTERFACE, GET_STATUS, SET_ADDRESS, SET_CONFIGURATION, SET_DESCRIPTOR, SET_FEATURE, SET_INTERFACE”. The “SYNC_FRAME” request is not supported. 7.2.1 Control-IN Transactions (Endpoint 0) 7.2.1.1 Get Device Descriptor Offset Field Size 0 1 2 4 5 bLength bDescriptorType bcdUSB bDeviceClass bDeviceSubClass 1 1 2 1 1 Default Value (Hex) 12 01 0110 FF 00 6 7 8 10 12 14 15 16 17 bDeviceProtocol bMaxPacketSize idVendor idProduct bcdDevice iManufacturer iProduct iSerialNumber bNumConfiguration 1 1 2 2 2 1 1 1 1 00 08 1046 6694 0100 00 01 00 01 Updated by EEPROM Yes * Yes * Yes * * Note: Refer to EEPROM session for its layout of contents. 7.2.1.2 Get Configuration Descriptor Offset 0 1 2 Field Size Value (Hex) Configuration Descriptor bLength 1 09 bDescriptorType 1 02 wTotalLength 2 003E Remark 62 -15Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller 4 5 6 7 bNumInterface bConfigurationValue iConfiguration bmAttributes 8 MaxPower 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 0 1 2 3 4 6 0 1 2 3 4 6 0 1 2 3 4 1 1 1 1 1 Interface 0 Descriptor bLength 1 bDescriptorType 1 bInterfaceNumber 1 bAlternateSetting 1 bNumEndpoints 1 bInterfaceClass 1 bInterfaceSubClass 1 01 01 00 A0 32 Bus Powered, Remote Wakeup 100 mA 09 04 00 00 00 FF 00 bInterfaceProtocol 1 00 iInterface 1 00 Alternate Interface 0 Descriptor bLength 1 09 bDescriptorType 1 04 bInterfaceNumber 1 00 bAlternateSetting 1 01 bNumEndpoints 1 05 bInterfaceClass 1 FF bInterfaceSubClass 1 00 bInterfaceProtocol 1 00 iInterface 1 00 Endpoint 1 Descriptor bLength 1 07 bDescriptorType 1 05 bEndpointAddress 1 01 bmAttributes 1 02 wMaxPacketSize 2 0008 bInterval 1 00 Endpoint 2 Descriptor bLength 1 07 bDescriptorType 1 05 bEndpointAddress 1 82 bmAttributes 1 02 wMaxPacketSize 2 0008 bInterval 1 00 Endpoint 3 Descriptor bLength 1 07 bDescriptorType 1 05 bEndpointAddress 1 83 bmAttributes 1 03 wMaxPacketSize 2 0005 OUT Bulk IN Bulk IN Interrupt -16Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller 6 0 1 2 3 4 6 0 1 2 3 4 6 bInterval 1 01 Endpoint 4 Descriptor bLength 1 07 bDescriptorType 1 05 bEndpointAddress 1 04 bmAttributes 1 01 wMaxPacketSize 2 0017 bInterval 1 01 Endpoint 5 Descriptor bLength 1 07 bDescriptorType 1 05 bEndpointAddress 1 85 bmAttributes 1 01 wMaxPacketSize 2 0029 bInterval 1 01 OUT Isochronous IN Isochronous Note: After W6694A is successfully enumerated by the USB host, software must issue SET_INTERFACE request with alternate setting 1, to enable all endpoints. When in default state (alternate setting 0), only endpoint 0 is functioning. 7.2.1.3 Get String Descriptor 0 Offset 0 1 2 Field Size bLength bDescriptorType wLanguage ID Value (Hex) 04 03 0409 1 1 2 Description U.S. English 7.2.1.4 Get String Descriptor 1 (Product) Offset 0 1 2 Field bLength bDescriptorType bString Size (Hex) 1 1 16 Value (Hex) 18 03 String (UNICODE) “USB ISDN TA” 7.2.2 Control-OUT Transactions (Endpoint 0) 7.2.2.1 Device Clear Feature, Remote Wake-up BmRequestType 00H bRequest CLEAR_FEATURE wValue 1 wIndex 0 wLength 0 Data None On received this request from host, W6694A will not detect the incoming ISDN broadcast message. -17Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller 7.2.2.2 Device Set Feature, Remote Wake-up BmRequestType 00H bRequest SET_FEATURE wValue 1 wIndex 0 wLength 0 Data None On received this request from host, W6694A will detect the incoming ISDN broadcast message. This is default setting. 7.2.2.3 Set Interface 0, Alternate Setting 0 bmRequestType 01H bRequest SET_INTERFACE wValue 0 wIndex 0 wLength 0 Data None On received this request from host, all endpoints except endpoint 0 are disabled. Also the B1/B2 channel FIFOs are reset and disabled. This is default setting. 7.2.2.4 Set Interface 0, Alternate Setting 1 bmRequestType 01H bRequest SET_INTERFACE wValue 1 wIndex 0 wLength 0 Data None On received this request from host, all endpoints are enabled and functioning. 7.2.3 Bulk-OUT Transaction (Endpoint 1) Bulk-OUT endpoint is used to write data to register or/and index which register to be read in following Bulk-IN transaction. A pare of two bytes (Address, Data) in Bulk-OUT data packet represents a read or write command on one register. A maximum of 8 bytes consist one Bulk-OUT transaction. W6694A perform the read/write commands following their order in the packet. Data packet for Bulk-OUT transaction: Offset 0 address1 1 data1 2 address2 3 data2 4 address3 5 data3 6 address4 7 data4 Address byte will indicate the read or write action to that register, by assigning highest order bit (bit 7) to 0 (read) or 1 (write). Contents of address byte: Bit 7 0/1 6 0 5 0 4 A4 3 A3 2 A2 1 A1 0 A0 -18Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller Bit 7: Bit 4-0: 0/1 = Read/Write Address offset of register. The data byte is the write data (write operation) or 00h (read operation). 7.2.4 Bulk-IN Transaction (Endpoint 2) Bulk-IN endpoint is for retrieving register data of W6694A. It returns the registers data that are requested by most recent Bulk-OUT data-read request. Inside the data packet, one register occupies 2 bytes. The first is register’s offset address, the 2nd byte is date. A maximum of 4 register data can be sent to host in one Bulk-IN packet. Offset 0 address1 1 data1 2 address2 3 data2 4 address3 5 data3 6 address4 7 data4 7.2.5 Interrupt-IN Transaction (Endpoint 3) Interrupt-IN endpoint is used to periodically poll device interrupt registers. W6694A use this endpoint to report interrupt status of all interrupt sources. All four bytes data of interrupt registers will be sent to host if ISTA is not 0. If no interrupt is detected by W6694A when received Interrupt-IN token, A NAK token will return to the USB host. Data packet for Interrupt-IN transaction: Offset 0 ISTA 1 CIR 2 PICR 3 PDATA 4 MOIR 7.2.6 Isochronous-OUT Transaction (Endpoint 4) After power-on or hardware reset, all B and D channels transmit FIFO (XFIFO) are disabled. A disabled XFIFO can not receive data from USB. But the transmitter will automatically send inter frame time fill pattern (all 1’s) to ISDN interface. The disabled XFIFO can be enabled by command XEN on each channel. An enabled XFIFO can receive data from USB, and send data to the USB host. Software decides the size of data to transmit depending on available XFIFO space, which is indicated by XFR flag carried by Isochronous-IN packet. When XFR is reported to host, it means that XFIFO has at least half of the total XFIFO size available for that channel. Each channel has its own XFIFO and status flags. If the incoming Isochronous-OUT packet is detected error, some action will be automatically taken for D and B channel XFIFO. For D channel, the XFIFO is reset and automatically enabled. For B channel, the XFIFO are not reset, and the data remained in XFIFO are still valid and will be transmitted to ISDN later. But the new incoming B channel data will be replaced by FFh, and stored into XFIFO. The continuous FFh will later be transmitted to corresponding B channel of ISDN interface. This Isochronous-OUT packet error will be reported to host, by setting bit ISOE of Isochronous-IN packet to 1. D channel FIFO will recognize and only accept data within HDLC frame (including opening and closing flag), all other data outside HDLC frame are ignored and not stored in FIFO. B channel FIFO accept any data after it is enabled. The packet format of Isochronous-OUT is as below: -19Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller Bit 7 6 5 4 3 D_DATA (1st byte) D_DATA (2nd byte) D_DATA (3rd byte) B_LEN3 B1_DATA ... B2_DATA ... 2 1 D_LEN1 0 D_LEN0 B_LEN2 B_LEN1 B_LEN0 D_LEN1-0 D Channel Data Length These bits indicate the data length of the subsequent data for D channel. The typical value is 1 to 3, if D channel message is sending; or 0 if no message to send. Once the opening flag of D channel message is sent, W6694A will move the data in D-XFIFO to S interface at the rate of 16K bps. The software must carefully assign proper length for each packet, otherwise a D-XFIFO under-run or overflow condition may occur. The only valid data are HDLC frame, including opening and closing flag (7Eh), and bit-stuffed data in between. Note that software should transmit the first data byte as opening flag in byte (8-bits) boundary. Due to the nature of HDLC framing, the closing flag may not be in byte-boundary. Software should stuff the remaining bit positions (if any) with binary 1, to fill the last byte, unless the last byte is 7Eh. D_DATA D Channel Data These are D channel data space, which always occupy 3 bytes in the packet. Software should put actual data length in D_LEN. If the data length D_LEN is less then 3, the remaining data bytes should be all FFh. B_LEN3-0 B Channel Data Length These bits indicate the data length of subsequent data for each B channel. Once the B-XFIFO is enabled (CMDR2:BnXEN), the length should be from 7 to 9 bytes inclusively, otherwise a transmit FIFO under run or overflow condition may occur. If there is no data for B1/B2 channel, the length can be 0. Note that the two B channels have same data length, but can be reset and enabled separately. B1_DATA B1 Channel Data These are B1 channel data, the length is indicated by B_LEN. B2_DATA B2 Channel Data These are B2 channel data, the length is indicated by B_LEN. 7.2.7 Isochronous-IN Transaction (Endpoint 5) After power on or reset, all B and D channels receive FIFO (RFIFO) are disabled. A disabled RFIFO can not receive data from ISDN, and will always return zero-length data for Isochronous-IN transaction. RFIFO can only be enabled by command CMDR:REN. Once enabled, an Isochronous-IN transaction can read data from RFIFO of that channel. The data packet also carries XFIFO status for that channel, and the most recent Isochronous-OUT packet error status (if error ever occurred). Note that since B1 and B2 channel output length is the same in Isochronous-OUT packet, the XFIFO status of B1/B2 channels are the same. The packet format of Isochronous-IN is as below: Bit 7 6 5 4 3 2 1 0 -20Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller ISOE D_XFR D_XCOL D_XDOV B1_XFR B1_XDOV B1_XDUN B2_XFR B2_XDOV B2_XDUN ISOE D_XDUN D_RDOV D_DATA ... B1_RDOV B1_LEN3 B1_DATA ... B2_RDOV B2_LEN3 B2_DATA ... D_LEN2 D_LEN1 D_LEN0 B1_LEN2 B1_LEN1 B1_LEN0 B2_LEN2 B2_LEN1 B2_LEN0 Isochronous-OUT Error This bit is set to indicate that the most recent received Isochronous-OUT packet has CRC error. This bit will remain set, until a CMDR1:CISOE clears it. XCOL Transmit Collision (D channel only) This bit indicates a D channel collision on the S-bus has been detected. The data in D channel XFIFO will be automatically re-transmitted, until the whole HDLC frame are successfully transmitted. This bit will remain set, until software issue CMDR1:DXEN to clear this bit. XFR Transmit FIFO Ready It is set when XFIFO has at least half of the XFIFO size available for incoming USB data. XDUN Transmit Data Under-run The corresponding XFIFO has run out of data. For D and B channel, the XFIFO is reset and disabled for that channel. This bit is cleared when XFIFO is enabled by XEN bit. XDOV Transmit Data Overflow The corresponding XFIFO has overflow condition. Data in XFIFO are overwritten by incoming USB data. For D and B channel, the XFIFO is reset and disabled for that channel. This bit is cleared when XFIFO is enabled by XEN bit. RDOV Receive Data Overflow The corresponding RFIFO has overflow condition. Data in RFIFO are overwritten by incoming ISDN data. When overflow condition occurred, the D and B channel RFIFO is reset and disabled for that channel. This bit is cleared when RFIFO is enabled by REN bit. 7.2.8 Suspend and Resume W6694A supports USB suspend and resume function as described in USB specification 1.1. When there is more than three millisecond period of inactivity on the USB, W6694A will automatically enter into a low-power suspend state. In this state, most of the ISDN and USB module will be powered off to consume minimum power. But the internal register values are preserved. Therefore it is recommended that the software perform necessary control to W6694A before power-down. The W6694A will leave suspend mode only when one of the two condition happens: host or device wake-up. (i). Host-Initiated Wake-up The USB host may wake-up W6694A by sending traffic on USB. On detected this wake-up signal, W6694A will automatically resume to normal operation. -21Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller (ii). Device Remote Wake-up In suspend mode, W6694A will ignore any ISDN traffic on S bus, except for incoming broadcast messages. When there is an incoming broadcast message from ISDN switch, such as SETUP message, W6694A will automatically wake-up, and signal the USB host that it has left suspend mode. The incoming SETUP message will be saved in D channel RFIFO. After returning from suspend mode, software should immediately read the RFIFO, and perform necessary operation as specified in ISDN protocol. -22Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller 7.3 EEPROM Configuration A 9346/93C46 type serial EEPROM can be used to store customized USB device configuration data. These configuration data will be read by W6694A after power on or reset, and sent to the USB host during enumeration. If EEPROM is not presented, or the first 16 bits in EEPROM is FFFFh, the default value in W6694A will be sent to the USB host instead. 7.3.1 EEPROM wire connection W6694A EEPROM EPCS EPCS EPSK Chip Select EPDO Data In EPDI Data Out Serial Clock 7.3.2 EEPROM Contents Offset 0 2 4 Size (Byte) 2 2 2 Contents MSB(15) LSB(0) Vendor ID (idVendor) *Note Device ID (idDevice) *Note Device Release Number (bcdDevice) *Note * Note: If any one of these fields is FFFFh, all default vaules are used. -23Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller 8. REGISTER DESCRIPTIONS All registers can be controlled from USB endpoints, as described in previous sections. 8.1 Interrupt Registers These registers will be read by Interrupt-IN packet only, so the USB host will periodically receive these data. These registers can not be read by Bulk-IN transfer. 8.1.1 Interrupt Status Register ISTA Read_clear This register indicates interrupt occurred in various interrupt sources. This register is cleared automatically after it is read and successfully ACKed by the USB host. Values after reset: 00h 7 6 5 4 3 2 1 0 ICC MOC PIOIC EPAC 0 0 0 0 ICC MOC Layer 1 Indication Code Change A change of value in the received indication code has been detected. Command/Indication Register (CIR) register. The new code is in Layer 1 Monitor Channel Status Change A change of value in the GCI mode Monitor Channel Interrupt Register (MOIR) has occurred. PIOIC Programmable IO Port Input Signal Changed A change of value in at least one input IO pin is detected. The input IO pins that change value can be identified in PIO Input Change Register (PICR) register. EPAC EEPROM Access Completed The most recent EEPROM access (read/write) operation is completed. If it was a read operation, the data is already stored in register EPRDL and EPRDH. 8.1.2 Layer 1 Command/Indication Register CIR Read Value after reset: 0Fh 7 6 5 4 3 2 1 0 0 0 0 0 CIR3 CIR2 CIR1 CIR0 CIR3-0 Layer 1 Indication Code Value of the received layer 1 indication code for S/T interface. Note these bits have a buffer size of two. -24Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller Note: If S/T layer 1 function is disabled and GCI bus is enabled (GE=1 in GCR register), CIR register is used to receive layer 1 indication code from U transceiver. In this case, the supported indication codes are : Indication Deactivation confirmation Power up indication Symbol DC PU Code 1111 0111 8.1.3 PIO Input Change Register Descriptions Idle code on GCI interface U transceiver power up PICR Read_clear Value after reset: 00h 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P7-0 Indicator of IO Pin Input Status 0: This IO pin is either output pin, or did not change input value. 1: This IO pin changed value. 8.1.4 Monitor Channel Interrupt Status MOIR Read_clear Value after reset: 00h 7 6 5 4 3 2 1 0 0 0 0 0 MDR MER MDA MAB MDR MER MDA MAB Monitor Channel Data Receive Monitor Channel End of Reception Monitor Channel Data Acknowledged Monitor Channel Data Abort NOTE : Registers in sections 8.2 to 8.5 are written/read by Bulk-OUT/Bulk-IN transactions. 8.2 Chip and FIFO Control Registers 8.2.1 Interrupt Mask Register IMASK Read/Write Address 00h Value after reset: F0h 7 6 5 4 3 2 1 0 ICC MOC PIOIC EPAC 0 0 0 0 Setting 1 to each bits masks the corresponding interrupt sources in ISTA register. -25Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller 8.2.2 Command Register 1 CMDR1 Write Address 01h Value after reset: 00h Writing 1 to the following bits will activate each corresponding function. Writing 0 to these bits has no effect. 7 6 5 4 3 2 1 0 DXRST DRRST DXEN DREN SRST CISOE DLP RLP DXRST D Channel Transmitter Reset Setting this bit resets D channel transmitter, and clear transmit FIFO (XFIFO). The transmitter will immediately transmit inter frame time fill pattern (all 1’s) to D channel in ISDN layer 1, but the XFIFO is disabled (not active). Software must issue DXEN to enable (activate) D channel XFIFO. After reset is done, this bit becomes 0. If this bit and DXEN bit are set at the same time, the reset action will be performed first and completed, then DXEN actions will follow. DRRST D Channel Receiver Reset Setting this bit resets D channels receiver, and clear receive FIFO (RFIFO). The D channels is disabled (not active). Software must issue DREN to enable (activate) D channel RFIFO, in order to receive D channel data from ISDN, and send data to USB. After reset is done, this bit becomes 0. If this bit and DREN bit are set at the same time, the reset action will be performed first and completed, then other actions will follow. DXEN D Channel Transmit FIFO Enable Setting this bit enables D channel transmit FIFO (XFIFO). After enabled, the D channel XFIFO will begin to receive D channel data from USB, and send data to ISDN. After enabled, this bit becomes 0. DREN D Channel Receive FIFO Enable Setting this bit enables D channel receive FIFO (RFIFO). After enabled, the D channel RFIFO will begin to receive D channel data from ISDN, and send data to USB. After enabled, this bit becomes 0. SRST Software Reset Setting this bit internally generates a software-reset signal. The effect of this reset signal is equivalent to hardwarereset pin, except that the USB circuit and all USB configured data are not reset. This bit must be set along, i.e., all other bits in this register must not set at the same time. This bit is not auto-clear, once this bit is set to 1, software must write 0 to this bit to exit from the reset mode. In the reset-mode the chip will not function properly. CISOE Clear Isochronous-OUT Error Setting this bit clears error-indication bit ISOE indicating Isochronous-OUT error. The ISOE bit is carried by Isochronous-IN packet. After cleared, this bit becomes 0. DLP Digital Loop back Setting this bit activates the digital loop back function. The transmitted digital 2B+D channels are looped to the received 2B+D channels. Note that after hardware reset, the internal clocks will turn off if the S bus is not connected or if there is no signal on the S bus. In this case, the C/I command ECK (value 0) must be issued through register CIX to enable loop back function. This bit remains set, until cleared by software reset (SRST). RLP Remote Loop back -26Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller Setting this bit activates the remote loop back function. The received 2B channels from the S/T interface are looped to the transmitted 2B channels of S/T interface. The D channel is not looped in this loop back function. This bit remains set, until cleared by software reset (SRST). 8.2.3 Command Register 2 CMDR2 Write Address 02h Value after reset: 00h Bits in this register act similar to that of CMDR1 register, except that the effect is on B1 or B2 channel XFIFO/RFIFO, instead of on D channel XFIFO/RFIFO. 7 6 5 4 3 2 1 0 B1XRST B1RRST B1XEN B1REN B2XRST B2RRST B2XEN B2REN B1XRST B1RRST B1XEN B1REN B2XRST B2RRST B2XEN B2REN B1 Channel Transmitter Reset B1 Channel Receiver Reset B1 Channel Transmit FIFO Enable B1 Channel Receive FIFO Enable B2 Channel Transmitter Reset B2 Channel Receiver Reset B2 Channel Transmit FIFO Enable B2 Channel Receive FIFO Enable 8.2.4 Control Register CTL Read/Write Address 03h Value after reset : 00H 7 BAM BAM 6 0 5 0 4 0 3 0 2 0 1 OPS1 0 OPS0 B Channel Auto Mode This mode let hardware automatically enable B1 or B2 channel transmit FIFO (XFIFO), whenever there is any error occurred for B channel XFIFO. No B channel XFIFO error status is reported to USB host. Writing 0 to this bit disable auto mode. OPS1-0 Output Phase Delay Compensation Select1-0 These two bits select the output phase delay compensation. OPS1 0 0 1 1 OPS0 0 1 0 1 Effect No output phase delay compensation Output phase delay compensation 260ns Output phase delay compensation 520 ns Output phase delay compensation 1040 ns -27Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller 8.2.5 Layer 1 Command/Indication Register CIX Read/Write Address 04h Value after reset: 0Fh 7 6 5 4 3 2 1 0 0 0 0 0 CIX3 CIX2 CIX1 CIX0 CIX3-0 Layer 1 Command Code Value of the command code transmitted to layer 1. A read to this register returns the previous written value. Note: If S/T layer 1 function is disabled and GCI bus is enabled (GE=1 in GCR register), CIX register is used to issue layer 1 command code to U transceiver. In this case, the supported command code is: Command Activate request command Symbol AR Code 1000 8.2.6 U-layer1 Ready Code Descriptions Activate request command L1_RC Read/Write Address 05h Value after reset: 0Ch 7 6 5 4 3 2 1 0 0 0 0 0 RC3 RC2 RC1 RC0 RC3-0 Ready Code When GCI bus is being enabled, these four programmable bits are allowed to program different Layer 1_Ready Code (AI: Activation Indication) by user. For example: Siemens PEB2091: AI=1100, Motorola MC145572: AI=1100. 8.3 GCI Mode Registers 8.3.1 GCI Mode Command Register GCR Read/Write Address 06h Value after reset: 00h 7 6 5 4 3 2 1 0 MAC 0 0 TLP GRLP SPU PD GE MAC Monitor Transmit Channel Active (Read Only) Data transmission is in progress in GCI mode Monitor channel. 0: The previous transmission has been terminated. Before starting a transmission, software should verify that the transmitter is inactive. 1: The previous transmission is in progress. TLP Test Loop back When set this bit both the GCIDU and GCIDD lines are internally connected together. The GCI mode loop back test function: GCIDU is internally connected with GCIDD, external input on GCIDD is ignored. -28Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller GRLP GCI Mode Remote Loop back Setting this bit to 1 activates the remote loop back function. The 2B+D channels data received from the GCI bus interface are looped to the transmitted channels. SPU PD Software Power Up Power Down SPU 0 PD 1 1 0 0 0 1 1 GE Description After U transceiver power down, W6694A will receive the indication DC (Deactivation Confirmation) from GCI bus and then software has to set SPU → 0, PD →1 to acknowledge U transceiver, by pulling GCIDU line to HIGH. W6694A remains normal operation. Setting SPU → 1, PD →0 will pull the GCI bus GCIDU line to LOW. This will enforce connected layer 1 devices (U transceiver) to deliver GCI bus clocking. After reception of the indication PU (Power Up indication) the reaction of the microprocessor should be: - To write an AR (Activate Request command) as C/I command code in the CIX register. - To reset the SPU bit and wait for the following ICC (indication code change) interrupt. Unused. GCI Mode Enable Setting this bit to 1 will enable the GCI bus interface. In the same time, the S/T layer 1 function is disabled. 8.3.2 Monitor Channel Control Register MOCR Read/Write Address 07h Value after reset: 00h 7 6 5 4 3 2 1 0 0 0 0 0 MRIE MRC MXIE MXC MRIE Monitor Channel 0 Receive Interrupt Enable Monitor channel interrupt status MDR, MER generation is enabled (1) or masked (0). MRC MR Bit Control Determines the value of the MR bit: 0: MR bit always 1. In addition, the MDR interrupt is blocked, except for the first byte of a packet (if MRIE=1). 1: MR internally controlled according to Monitor channel protocol. In addition, the MDR interrupt is enabled for all bytes according to the Monitor channel protocol (if MRIE=1). MXIE Monitor Channel Transmit Interrupt Enable Monitor interrupt status MDA, MAB generation is enabled (1) or masked (0). MXC MX Bit Control Determines the value of the MX bit: 0: MX always 1. 1: MX internally controlled according to Monitor channel protocol. -29Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller 8.3.3 Monitor Channel Receive Register MOR Read Address 08h Value after reset: FFh 7 6 5 4 3 8.3.4 Monitor Channel Transmit Register 2 1 MOX 0 Read/Write Address 09h Value after reset: FFh 7 6 5 4 3 2 1 0 8.4 Programmable IO Registers 8.4.1 PIO Input Enable Register PIE Read/Write Address 0Ah Value after reset: 00h 7 6 5 4 3 2 1 0 IE7 IE6 IE5 IE4 IE3 IE2 IE1 IE0 IE7-0 Input Enable for IO Pin 7-0. Setting these bits enable corresponding IO pin to become input pin. Default is output pin. 8.4.2 PIO Output Register 1 PO1 Read/Write Address 0Bh Value after reset: FFh 7 6 5 4 3 2 1 0 OM3_1 OM3_0 OM2_1 OM2_0 OM1_1 OM1_0 OM0_1 OM0_0 OMn_1-0 Output Mode of IO Pin n (n=3..0). Setting corresponding bits drive output pin with different output mode. Possible modes are: 00: always LOW 01: 0.5 second HIGH/LOW cycle 10: 1 second HIGH/LOW cycle 11: always HIGH These bits have no effect for input pin. Note: The ISDN clock must exist for the output cycle to take effect. If the S/T interface does not have clock input, it is necessary to enable clock by writing 1 to register CIX. -30Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller 8.4.3 PIO Output Register 2 PO2 Read/Write Address 0Ch Value after reset: FFh 7 6 5 4 3 2 1 0 OM7_1 OM7_0 OM6_1 OM6_0 OM5_1 OM5_0 OM4_1 OM4_0 OMn_1-0 Output Mode of IO Pin n (n=7..4). 8.4.4 PIO Data Register PDATA Read Address 0Dh Value after reset: 00h 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 D7-0 Read Data of IO Pins 7-0 The corresponding bits are the present values of input pins 7-0 (LOW=0, HIGH=1). 8.5 B Channel Switch Registers 8.5.1 Layer1 B1 Receiver Select Register L1B1RS Read/Write Address 0Eh Value after reset: 04h 7 6 5 4 3 2 1 0 0 0 0 0 0 RS2 RS1 RS0 RS2-0 Receiver Select These bits select the source where layer 1 B1 channel will receive data from. Possible values are: 000 (0): receive from PCM1 001 (1): receive from PCM2 010 (2): receive from Layer1 B1 100 (4): receive from USB B1 8.5.2 Layer1 B2 Receiver Select Register L1B2RS Read/Write Address 0Fh Value after reset: 05h 7 6 5 4 3 2 1 0 0 0 0 0 0 RS2 RS1 RS0 RS2-0 Receiver Select These bits select the source where layer 1 B2 channel will receive data from. Possible values are: 000 (0): receive from PCM1 001 (1): receive from PCM2 011 (3): receive from Layer1 B2 101 (5): receive from USB B2 -31Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller 8.5.3 USB B1 Receiver Select Register USBB1RS Read/Write Address 10h Value after reset: 02h 7 6 5 4 3 2 1 0 0 0 0 0 0 RS2 RS1 RS0 RS2-0 Receiver Select These bits select the source where USB B1 channel will receive data from. Possible values are: 000 (0): receive from PCM1 001 (1): receive from PCM2 010 (2): receive from Layer1 B1 8.5.4 USB B2 Receiver Select Register USBB2RS Read/Write Address 11h Value after reset: 03h 7 6 5 4 3 2 1 0 0 0 0 0 0 RS2 RS1 RS0 RS2-0 Receiver Select These bits select the source where USB B2 channel will receive data from. Possible values are: 000 (0): receive from PCM1 001 (1): receive from PCM2 011 (3): receive from Layer1 B2 channel 8.5.5 PCM1 Receiver Select Register PCM1RS Read/Write Address 12h Value after reset: 00h 7 6 5 4 3 2 1 0 0 0 0 0 EPCM RS2 RS1 RS0 EPCM Enable PCM Transmit/Receive 0: Disable data transmit/receive to/from PCM port. The frame synchronization clock is held LOW. The bit synchronization clock is LOW if both PCM ports are disabled. 1: Enable data transmit/receive to/from PCM port. The frame synchronization clock is active. The bit synchronization clock is active. RS2-0 Receiver Select These bits select the source where PCM1 channel will receive data from. Possible values are: 000 (0): receive from PCM1 001 (1): receive from PCM2 010 (2): receive from Layer1 B1 011 (3): receive from Layer1 B2 100 (4): receive from USB B1 101 (5): receive from USB B2 -32Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller Note: The ISDN line must plug-in for the PCM port to take effect. 8.5.6 PCM2 Receiver Select Register PCM2RS Read/Write Address 13h Value after reset: 00h 7 6 5 4 3 2 1 0 0 0 0 0 EPCM RS2 RS1 RS0 EPCM Enable PCM Transmit/Receive 0: Disable data transmit/receive to/from PCM port. The frame synchronization clock is held LOW. The bit synchronization clock is held LOW if both PCM ports are disabled. 1: Enable data transmit/receive to/from PCM port. The frame synchronization clock is active. The bit synchronization clock is active. RS2-0 Receiver Select These bits select the source where PCM2 channel will receive data from. Possible values are: 000 (0): receive from PCM1 001 (1): receive from PCM2 010 (2): receive from Layer1 B1 011 (3): receive from Layer1 B2 100 (4): receive from USB B1 101 (5): receive from USB B2 Note: The PCM ports operate with the clock input from ISDN line, therefore the ISDN line must plug-in for the PCM port to take effect. 8.6 EEPROM Access Registers 8.6.1 EEPROM Read/Write Address EPADR Write Address 14h 7 6 5 4 3 2 1 0 CM1 CM0 A5 A4 A3 A2 A1 A0 CM1-0 Command for Read/Write These bits indicate the possible operation to the serial EEPROM: 00: Read 16 bits data from address A5-0 10: Write 16 bits data to address A5-0 01: Erase all of EEPROM, ignore A5-0 11: Write all of EEPROM with data EPWDH + EPWDL, ignore A5-0 A5-0 Address Address corresponds to a 16-bit word. Once this register is written, W6694A begin to read or write one 16 bits word from or to serial EEPROM. When the read or write operation is completed, an interrupt bit is set at ISTA:EPAC. -33Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller 8.6.2 EEPROM Read Data Low Byte EPRDL Read Address 15h Value after reset: 00h 7 6 5 4 3 2 1 0 Store the low order byte of one 16-bit word most recently read from serial EEPROM with address EPADR. 8.6.3 EEPROM Read Data High Byte EPRDH Read Address 16h Value after reset: 00h 7 6 5 4 3 2 1 0 Store the high order byte of one 16-bit word most recently read from serial EEPROM with address EPADR. 8.6.4 EEPROM Write Data Low Byte 7 6 5 4 EPWDL 3 2 Write 1 Address 17h 0 Store the low order byte of one 16-bit word to write to serial EEPROM. 8.6.5 EEPROM Write Data High Byte 7 6 5 4 EPWDH 3 2 Write 1 Address 18h 0 Store the high order byte of one 16-bit word to write to serial EEPROM. 9. ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Rating Parameter Voltage on any pin with respect to ground Ambient temperature under bias Maximum voltage on VDD Symbol VS Limit Values -0.4 to VDD+0.4 Unit V TA 0 to 70 °C VDD 6 V -34Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller 9.2 Power Supply Parameter 5V Input voltage 3.3V regulator output Analog ground Digital ground Symbol VDD Min 4.75 Typ 5.0 Max 5.25 Unit V VDD3 3.0 3.3 3.6 V Pins VDD3I, VDD3 V V Pins VSS1 Pins VSS21, VSS22, VSS23, VSSU VSSA VSSD 0 0 Remarks Pins VDD1, VDD21, VDD22, VDD23, VDDU 9.3 DC Characteristics TA=0 to 70 °C; VDD=5 V ± 5 %, VSSA=0 V, VSSD=0 V Parameter Low input voltage High input voltage Low output voltage High output voltage Power supply current: suspended Power supply current: operational Power supply current: USB active only Power supply current: USB active, ISDN connected Absolute value of output pulse amplitude (VSX2-VSX1) Transmitter output current Transmitter output impedence Symbol VIL Min -0.4 Max 0.8 Unit V VIH 2.0 VDD +0.4 0.4 V VOL VOH 2.4 V Test conditions Remarks IOL= 12 mA V ICC 1.5 mA VDD=5V, S/T layer 1 in state “F3 Deactivated without clock”, USB in suspended mode VDD=5V, ISDN 2B+D active, USB is configured and active ICC 20.4 mA ICC 15.4 mA VDD=5V, ISDN cable disconnected, USB is configured and active ICC 18.1 mA VDD=5V, ISDN cable connected, USB is configured and active VX 2.03 2.10 2.31 2.39 V V RL=50 Ω 1) RL=400 Ω 1) SX1,2 IX 7.5 13.4 mA RL=5.6 Ω 1) SX1,2 RX 30 23 kΩ Ω Inactive or during binary ONE During binary ZERO (RL=50 Ω) SX1,2 -35Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller Note: 1) Due to the transformer, the load resistance seen by the circuit is four times RL. Capacitances of ISDN pins TA=25 °C, VDD= 5 V ± 5 %, VSSA= 0V, VSSD=0V, fc=1 Mhz, unmeasured pins grounded. Parameter Output capacitance against VSSA Input capacitance Load capacitance Symbol COUT CIN CL Min. Max. 10 Unit pF Remarks SX1,2 7 50 pF pF SR1,2 XTAL1,2 -36Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller Recommended oscillator circuits CL External oscillator signal XTAL1 7.68MHz CL≤50pF XTAL2 XTAL1 or N.C. XTAL2 CL Crystal specifications Parameter Frequency Frequency calibration tolerance Load capacitance Oscillator mode Symbol f Values 7.680 Max. 100 Unit MHz ppm CL Max. 50 Fundamental pF Note: The load capacitance CL depends on the crystal specification. The typical values are 33 to 47 pF. External oscillator input (XTAL1) clock characteristics Parameter Duty cycle Min. 1:2 Max. 2:1 9.4 Preliminary Switching Characteristics 9.4.1 PCM Interface Timing PBCK (1.536MHz) 24 CHs PFCK1 CH 1 CH 2 PTXD Port1 Port2 PRXD Port1 Port2 PFCK2 -37- Port1 Port2 Port1 Port2 Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller Note 1: These drawings are not to scale. Note 2 : The frequency of PBCK is 1536 kHz which includes 24 channels of 64 kbps data. The PFCK1 and PFCK2 are located at channel 1 and channel 2, each with a 8 x PBCK duration. Detailed PCM timing ta1 ta2 PBCK ta5 ta3 PFCK1 PFCK2 ta6 ta4 PTXD ta7 PRXD ta8 Parameter ta1 ta2 ta3 ta4 ta5 ta6 ta7 ta8 Parameter Descriptions PBCK pulse high PBCK pulse low Frame clock asserted from PBCK PTXD data delay from PBCK Frame clock deasserted from PBCK PTXD hold time from PBCK PRXD setup time to PBCK PRXD hold time from PBCK Min. 195 Nominal 325 325 Max. Remarks Unit = ns 455 20 20 20 10 20 10 Note: The PCM clocks are locked to the S/T receive clock. At every two or three PCM frame time (125 µs), PBCK and PFCK1, PFCK2 may be adjusted by one local oscillator cycle (130 ns) in order to synchronize with S/T clock. This shift is made on the LOW level time of PBCK and the HIGH level time is not affected. This introduces jitters on the PBCK, PFCK1 and PFCK2 with jitter amplitude 260 ns (peak-to-peak) and jitter frequency about 2.67~4 kHz. -38Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller 9.4.2 Serial EEPROM Timing tb1 tb2 EPSK tb3 tb3 EPCS tb6 tb4 A5 EPSDI Parameter tb1 tb2 tb3 tb4 tb5 tb6 tb7 tb5 tb4 Parameter Descriptions EPSK low EPSK high EPCS output delay EPSD output delay EPSD tri-state delay EPSD input setup time EPSD input hold time A4 ..... A1 Min. 2500 2500 A0 Max. tb7 D15 D14 ....... D1 D0 Remarks Unit = ns 30 30 30 30 30 -39Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller 10. PACKAGE INFORMATION 48L LQFP(7x7x1.4mm footprint 2.0mm) (Shown on next page) -40Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller HD D A A2 36 A1 25 37 24 48 13 HE E 1 12 b e c SEATING PLANE L Y θ L1 Controlling dimension : Millimeters Symbol A A1 A2 b c D E e HD HE L L1 Y 0 Dimension in inch Min Nom Max Dimension in mm Min Nom Max 0.002 0.004 0.006 0.05 0.055 0.057 1.35 1.40 1.45 0.006 0.008 0.010 0.15 0.20 0.25 0.004 0.006 0.008 0.10 0.15 0.20 0.272 0.276 0.280 6.90 7.00 7.10 0.272 0.276 0.280 6.90 7.00 7.10 0.020 0.026 0.35 0.50 0.65 0.053 0.014 0.10 0.15 0.350 0.354 0.358 8.90 9.00 9.10 0.350 0.354 0.358 8.90 9.00 9.10 0.018 0.024 0.030 0.45 0.60 0.75 1.00 0.039 0.004 0 7 0.10 0 7 -41Publication Release Date: May, 2001 Revision 1.03 Preliminary Data Sheet W6694A USB-ISDN S/T-Controller 11. ORDERING INFORMATION PART NUMBER W6694ACD Headquarters PACKAGE TYPE 48-pin LQFP PRODUCTION FLOW Commercial, 0 °C to +70 0C Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 4, Creation Rd. III, No. 378 Kwun Tong Rd; Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change withou t notice. -42Publication Release Date: May, 2001 Revision 1.03