ETC PSB3186

D at a Sh e e t , D S 1 , Ja n . 2 00 3
ISAC-SX TE
ISDN Subscriber Access
Controller for Terminals
PSB 3186, V 1.4
Wired
Communications
N e v e r
s t o p
t h i n k i n g .
ABM®, ACE®, AOP®, ARCOFI®, ASM®, ASP®, DigiTape®, DuSLIC®, EPIC®, ELIC®,
FALC®, GEMINAX®, IDEC®, INCA®, IOM®, IPAT®-2, ISAC®, ITAC®, IWE®, IWORX®,
MUSAC®, MuSLIC®, OCTAT®, OptiPort®, POTSWIRE®, QUAT®, QuadFALC®,
SCOUT®, SICAT®, SICOFI®, SIDEC®, SLICOFI®, SMINT®, SOCRATES®, VINETIC®,
10BaseV®, 10BaseVX® are registered trademarks of Infineon Technologies AG.
10BaseS™, EasyPort™, VDSLite™ are trademarks of Infineon Technologies AG.
Microsoft® is a registered trademark of Microsoft Corporation. Linux® is a registered
trademark of Linus Torvalds.
The information in this document is subject to change without notice.
Edition 2003-01-30
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2003.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide
(www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet
Revision History:
2003-01-30
Previous Version:
Data Sheet, DS1, V1.3, 2000-08-23
Page
Subjects (major changes since last revision)
Chapter 1 Comparison ISAC-S TE/ISAC-SX TE
Chapter
3.3.6.2
S- Transceiver Synchronization New
Chapter
3.3.10
Test Functions extended
Chapter
3.7.1.1
CDA Handler Description extended
Chapter
3.7.5.1
TIC Bus Access Control: Note added
Chapter
5.6
IOM-2 Interface Timing: Explanation added
Chapter
5.7.2
Parallel Microcontroller Interface Timing: Explanation added
Chapter
5.9
S-Transceiver
Chapter
5.10
Recommended Transformer Specification: Changed
Chapter
5.11
Line Overload Protection added
Chapter
5.12
EMC/ESD added
DS1
ISAC-SX TE
PSB 3186
Table of Contents
Page
1
1.1
1.2
1.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3
3.1
3.2
3.2.1
3.2.1.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.6.1
3.3.6.2
3.3.7
3.3.8
3.3.9
3.3.10
3.4
3.4.1
3.4.2
3.4.3
3.5
3.5.1
3.5.1.1
3.5.1.2
3.5.1.3
3.5.1.4
3.5.2
3.6
3.6.1
Description of Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Functions and Device Architecture . . . . . . . . . . . . . . . . . . . . . . .
Microcontroller Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Control Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Activation Indication via Pin ACL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S/T-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S/T-Interface Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S/T-Interface Multiframing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Transfer and Delay between IOM-2 and S/T . . . . . . . . . . . . . . . .
Transmitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S/T Interface Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Protection Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S-Transceiver Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S/T Interface Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Level Detection Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transceiver Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description of the Receive PLL (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Clock Output C768 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control of Layer-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State Machine TE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State Transition Diagram (TE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
States (TE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C/I Codes (TE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Infos on S/T (TE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command/ Indicate Channel Codes (C/I0) - Overview . . . . . . . . . . . . .
Control Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example of Activation/Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
4
12
15
17
18
25
25
27
28
29
31
33
34
35
38
39
40
42
44
45
46
47
47
50
50
50
51
52
54
55
55
56
57
59
59
61
63
65
66
67
67
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PSB 3186
Table of Contents
Page
3.7
3.7.1
3.7.1.1
3.7.2
3.7.2.1
3.7.2.2
3.7.3
3.7.3.1
3.7.3.2
3.7.3.3
3.7.3.4
3.7.3.5
3.7.3.6
3.7.4
3.7.5
3.7.5.1
3.7.5.2
3.7.6
3.8
3.8.1
3.8.2
3.8.2.1
3.8.2.2
3.8.3
3.8.3.1
3.8.3.2
3.8.4
3.8.5
3.8.6
3.9
IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
IOM-2 Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Controller Data Access (CDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Serial Data Strobe Signal and Strobed Data Clock . . . . . . . . . . . . . . . 82
Serial Data Strobe Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Strobed IOM-2 Bit Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
IOM-2 Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Handshake Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Error Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
MONITOR Channel Programming as a Master Device . . . . . . . . . . . 91
MONITOR Channel Programming as a Slave Device . . . . . . . . . . . . 91
Monitor Time-Out Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
MONITOR Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
C/I Channel Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
D-Channel Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
TIC Bus D-Channel Access Control . . . . . . . . . . . . . . . . . . . . . . . . . 95
S-Bus Priority Mechanism for D-Channel . . . . . . . . . . . . . . . . . . . . . 97
Activation/Deactivation of IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . 100
HDLC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Message Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Structure and Control of the Receive FIFO . . . . . . . . . . . . . . . . . . . 104
Receive Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Structure and Control of the Transmit FIFO . . . . . . . . . . . . . . . . . . 112
Transmit Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Access to IOM-2 Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Extended Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
HDLC Controller Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.1.9
4.1.10
Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-channel HDLC Control and C/I Registers . . . . . . . . . . . . . . . . . . . . . .
RFIFOD - Receive FIFO D-Channel . . . . . . . . . . . . . . . . . . . . . . . . .
XFIFOD - Transmit FIFO D-Channel . . . . . . . . . . . . . . . . . . . . . . . . .
ISTAD - Interrupt Status Register D-Channel . . . . . . . . . . . . . . . . . . .
MASKD - Mask Register D-Channel . . . . . . . . . . . . . . . . . . . . . . . . . .
STARD - Status Register D-Channel . . . . . . . . . . . . . . . . . . . . . . . . .
CMDRD - Command Register D-channel . . . . . . . . . . . . . . . . . . . . . .
MODED - Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EXMD1- Extended Mode Register D-channel 1 . . . . . . . . . . . . . . . . .
TIMR1 - Timer 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SAP1 - SAPI1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
5
121
128
128
128
128
130
130
131
132
134
135
135
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PSB 3186
Table of Contents
4.1.11
4.1.12
4.1.13
4.1.14
4.1.15
4.1.16
4.1.17
4.1.18
4.1.19
4.1.20
4.1.21
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
4.2.10
4.2.11
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.4.1
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10
4.3.11
4.3.12
4.3.13
4.3.14
4.3.15
4.3.16
Page
SAP2 - SAPI2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RBCLD - Receive Frame Byte Count Low D-Channel . . . . . . . . . . . .
RBCHD - Receive Frame Byte Count High D-Channel . . . . . . . . . . .
TEI1 - TEI1 Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TEI2 - TEI2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RSTAD - Receive Status Register D-Channel . . . . . . . . . . . . . . . . . .
TMD -Test Mode Register D-Channel . . . . . . . . . . . . . . . . . . . . . . . .
CIR0 - Command/Indication Receive 0 . . . . . . . . . . . . . . . . . . . . . . .
CIX0 - Command/Indication Transmit 0 . . . . . . . . . . . . . . . . . . . . . . .
CIR1 - Command/Indication Receive 1 . . . . . . . . . . . . . . . . . . . . . . .
CIX1 - Command/Indication Transmit 1 . . . . . . . . . . . . . . . . . . . . . . .
Transceiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TR_CONF0 - Transceiver Configuration Register 0 . . . . . . . . . . . . . .
TR_CONF1 - Transceiver Configuration Register 1 . . . . . . . . . . . . . .
TR_CONF2 - Transmitter Configuration Register 2 . . . . . . . . . . . . . .
TR_STA - Transceiver Status Register . . . . . . . . . . . . . . . . . . . . . . .
SQRR1 - S/Q-Channel Receive Register 1 . . . . . . . . . . . . . . . . . . . .
SQXR1- S/Q-Channel TX Register 1 . . . . . . . . . . . . . . . . . . . . . . . . .
SQRR2 - S/Q-Channel Receive Register 2 . . . . . . . . . . . . . . . . . . . . .
SQRR3 - S/Q-Channel Receive Register 3 . . . . . . . . . . . . . . . . . . . .
ISTATR - Interrupt Status Register Transceiver . . . . . . . . . . . . . . . . .
MASKTR - Mask Transceiver Interrupt . . . . . . . . . . . . . . . . . . . . . . . .
ACFG2 - Auxiliary Configuration Register . . . . . . . . . . . . . . . . . . . . .
IOM-2 and MONITOR Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDAxy - Controller Data Access Register xy . . . . . . . . . . . . . . . . . . .
XXX_TSDPxy - Time Slot and Data Port Selection for CHxy . . . . . . .
CDAx_CR - Control Register Controller Data Access CH1x . . . . . . .
TR_CR - Control Register Transceiver Data (IOM_CR.CI_CS=0) . . .
TRC_CR - Control Register Transceiver C/I0 (IOM_CR.CI_CS=1)
DCI_CR - Control Register for D and CI1 Handler
(IOM_CR.CI_CS=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MON_CR - Control Register Monitor Data . . . . . . . . . . . . . . . . . . . . .
SDS_CR - Control Register Serial Data Strobe . . . . . . . . . . . . . . . . .
IOM_CR - Control Register IOM Data . . . . . . . . . . . . . . . . . . . . . . . .
STI - Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .
ASTI - Acknowledge Synchronous Transfer Interrupt . . . . . . . . . . . .
MSTI - Mask Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . .
SDS_CONF - Configuration Register for Serial Data Strobe . . . . . . .
MCDA - Monitoring CDA Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MOR - MONITOR Receive Channel . . . . . . . . . . . . . . . . . . . . . . . . . .
MOX - MONITOR Transmit Channel . . . . . . . . . . . . . . . . . . . . . . . . .
MOSR - MONITOR Interrupt Status Register . . . . . . . . . . . . . . . . . . .
Data Sheet
6
136
136
137
137
138
138
140
140
141
142
142
144
144
145
145
146
147
147
148
148
148
149
149
151
151
151
152
153
154
154
156
156
157
159
159
160
160
161
161
162
162
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Table of Contents
Page
4.3.17
4.3.18
4.3.19
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
4.4.7
4.4.8
4.4.9
MOCR - MONITOR Control Register . . . . . . . . . . . . . . . . . . . . . . . . .
MSTA - MONITOR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . .
MCONF - MONITOR Configuration Register . . . . . . . . . . . . . . . . . . .
Interrupt and General Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISTA - Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MASK - Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUXI - Auxiliary Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . .
AUXM - Auxiliary Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODE1 - Mode1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODE2 - Mode2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ID - Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRES - Software Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMR2 - Timer 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
162
163
164
165
165
166
166
167
167
169
169
170
170
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.7.1
5.7.2
5.8
5.9
5.10
5.11
5.12
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOM-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microcontroller Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Control Interface (SCI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Microcontroller Interface Timing . . . . . . . . . . . . . . . . . . . . . . .
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Transformer Specification . . . . . . . . . . . . . . . . . . . . . . .
Line Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMC / ESD Aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
172
172
173
174
175
176
177
179
179
180
184
185
186
187
188
6
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
7
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Data Sheet
7
2003-01-30
ISAC-SX TE
PSB 3186
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Data Sheet
Page
Logic Symbol of the ISAC-SX TE . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Applications of the ISAC-SX TE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration of the ISAC-SX TE . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram of the ISAC-SX TE . . . . . . . . . . . . . . . . . . .
Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Direct/Indirect Register Address Mode . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Status and Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ACL Indication of Activated Layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .
ACL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wiring Configurations in User Premises . . . . . . . . . . . . . . . . . . . . . . .
S/T -Interface Line Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frame Structure at Reference Points S and T (ITU I.430). . . . . . . . . .
Data Delay between IOM-2 and S/T Interface . . . . . . . . . . . . . . . . . . .
Data Delay between IOM-2 and S/T Interface with S/G Bit Evaluation
Equivalent Internal Circuit of the Transmitter Stage . . . . . . . . . . . . . .
Equivalent Internal Circuit of the Receiver Stage . . . . . . . . . . . . . . . .
Connection of Line Transformers and Power Supply to the
ISAC-SX TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Circuitry for Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Circuitry for Symmetrical Receivers. . . . . . . . . . . . . . . . . . . .
External Circuitry for Symmetrical Receivers. . . . . . . . . . . . . . . . . . . .
Disabling of S/T Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Loop at the S/T-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock System of the ISAC-SX TE . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Relationships of ISAC-SX TE Clock Signals . . . . . . . . . . . . . .
Buffered Oscillator Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layer-1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State Transition Diagram (TE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State Transition Diagram of Unconditional Transitions (TE) . . . . . . . .
Example of Activation/Deactivation Initiated by the Terminal . . . . . . .
IOMÒ-2 Frame Structure in Terminal Mode . . . . . . . . . . . . . . . . . . . .
Architecture of the IOM Handler (Example Configuration). . . . . . . . . .
Data Access via CDAx1 and CDAx2 Register Pairs . . . . . . . . . . . . . .
Examples for Data Access via CDAxy Registers . . . . . . . . . . . . . . . . .
Data Access when Looping TSa from DU to DD . . . . . . . . . . . . . . . . .
Data Access when Shifting TSa to TSb on DU (DD) . . . . . . . . . . . . . .
8
17
18
19
26
28
29
32
33
34
36
37
37
38
38
40
41
41
44
45
46
46
47
48
49
50
51
52
54
55
56
57
58
60
61
67
69
71
73
74
75
76
2003-01-30
ISAC-SX TE
PSB 3186
List of Figures
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
Figure 53
Figure 54
Figure 55
Figure 56
Figure 57
Figure 58
Figure 59
Figure 60
Figure 61
Figure 62
Figure 63
Figure 64
Figure 65
Figure 66
Figure 67
Figure 68
Figure 69
Figure 70
Figure 71
Figure 72
Figure 73
Figure 74
Figure 75
Figure 76
Figure 77
Figure 78
Figure 79
Figure 80
Figure 81
Figure 82
Data Sheet
Page
Example for Monitoring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Interrupt Structure of the Synchronous Data Transfer . . . . . . . . . . . . . 79
Examples for the Synchronous Transfer Interrupt Control with one
Enabled STIxy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Data Strobe Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Strobed IOM-2 Bit Clock. Register SDS_CONF programmed to 01H . 84
Examples of MONITOR Channel Applications in IOM -2 TE Mode . . . 85
MONITOR Channel Protocol (IOM-2) . . . . . . . . . . . . . . . . . . . . . . . . . 87
Monitor Channel, Transmission Abort requested by the Receiver. . . . 90
Monitor Channel, Transmission Abort requested by the Transmitter. . 90
Monitor Channel, Normal End of Transmission . . . . . . . . . . . . . . . . . . 90
MONITOR Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
CIC Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Applications of TIC Bus in IOM-2 Bus Configuration . . . . . . . . . . . . . . 96
Structure of Last Octet of Ch2 on DU . . . . . . . . . . . . . . . . . . . . . . . . . 97
Structure of Last Octet of Ch2 on DD . . . . . . . . . . . . . . . . . . . . . . . . . 98
D-Channel Access Control on the S-Interface . . . . . . . . . . . . . . . . . . . 99
Deactivation of the IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Activation of the IOM-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
RFIFO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Data Reception Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Reception Sequence Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Receive Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Data Transmission Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Transmission Sequence Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Interrupt Status Registers of the HDLC Controllers . . . . . . . . . . . . . . 118
Layer 2 Test Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Register Mapping of the ISAC-SX TE . . . . . . . . . . . . . . . . . . . . . . . . 121
Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . 176
IOM-2 Timing (TE mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Definition of Clock Period and Width . . . . . . . . . . . . . . . . . . . . . . . . . 178
SCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Microprocessor Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Microprocessor Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Reset Signal RES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
9
2003-01-30
ISAC-SX TE
PSB 3186
Figure 83
Figure 84
Data Sheet
Maximum Line Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Transformer Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
10
2003-01-30
ISAC-SX TE
PSB 3186
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Data Sheet
Page
Comparison of the ISAC-SX TE with the previous version
ISAC-S TE: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
ISAC-SX TE Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . 20
Host Interface Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Header Byte Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Bus Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Reset Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ISAC-SX TE Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
S/Q-Bit Position Identification and Multiframe Structure . . . . . . . . . . . 42
IOM-2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Examples for Synchronous Transfer Interrupts . . . . . . . . . . . . . . . . . . 79
CDA Register Combinations with Correct Read/Write Access . . . . . . 81
Transmit Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Receive Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
HDLC Controller Address Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Receive Byte Count with RBC11...0 in the RBCHD/RBCLD
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Receive Information at RME Interrupt . . . . . . . . . . . . . . . . . . . . . . . . 111
XPR Interrupt (availability of XFIFOD) after XTF, XME Commands . 113
11
2003-01-30
ISAC-SX TE
PSB 3186
Overview
1
Overview
The ISDN Subscriber Access Controller for Terminals ISAC-SX TE integrates a
D-channel HDLC controller and a four wire S/T interface used to link voice/data terminals
to the ISDN. It is based on the ISAC-S TE PSB 2186, and provides enhanced features
and functionality.
The system integration is simplified by several configurations of the parallel
microcontroller interface selected via pin strapping. They include multiplexed and
demultiplexed interface selection as well as the optional indirect register access
mechanism which reduces the number of necessary registers in the address space to 2
locations. The ISAC-SX TE also provides a serial control interface (SCI).
The FIFO size of the cyclic D-channel buffer is 64 bytes per direction with programmable
block size (threshold). The S-transceiver supports terminals mode (TE), activation/
deactivation, timing recovery and D-channel access control and priority control.
One LED output which is capable to indicate the activation status of the S-interface
automatically or can be programmed by the host.
The ISAC-SX TE is produced in advanced CMOS technology.
Data Sheet
12
2003-01-30
ISAC-SX TE
PSB 3186
Overview
Table 1
Comparison of the ISAC-SX TE with the previous version ISAC-S TE:
ISAC-SX TE PSB 3186
ISAC-S TE PSB 2186
Operating modes
TE
TE
Supply voltage
3.3 V ± 5%
5 V ± 5%
Technology
CMOS
CMOS
Package
P-MQFP-64 / P-TQFP-64
P-MQFP-64 / P-LCC-44 /
P-DIP-40
Transceiver
Transformer ratio for the
transmitter
receiver
1:1
1:1
2:1
2:1
Test Functions
- Dig. loop via Layer 2 (TLP) - Dig. loop via Layer 2(TLP)
- Layer 1 disable (DIS_TR) - Layer 1 disable (DIS_TR)
- Analog loop (ARL)
- Analog loop (LP_A- bit
EXLP- bit, ARL)
Microcontroller Interface
Serial interface (SCI)
Not provided
8-bit parallel interface:
Motorola Mux
Siemens/Intel Mux
Siemens/Intel Non-Mux
direct/ indirect Addressing
8-bit parallel interface:
Motorola Mux
Siemens/Intel Mux
Siemens/Intel Non-Mux
Command structure of the Header/address/data
register access (SCI)
Address/data
Crystal
7.68 MHz
7.68 MHz
Buffered 7.68 MHz output
Provided
Not provided
Controller data access to
IOM-2 timeslots
All timeslots;
various possibilities of data
access
Restricted access to
B- and IC-channel
Data control and
manipulation
Various possibilities of data
control and data
manipulation (enable/
disable, shifting, looping,
switching)
B- and IC-channel looping
Data Sheet
13
2003-01-30
ISAC-SX TE
PSB 3186
Overview
ISAC-SX TE PSB 3186
ISAC-S TE PSB 2186
IOM-2 Interface
Double clock (DCL),
bit clock pin (BCL),
serial data strobe (SDS)
Double clock (DCL),
bit clock (BCL),
serial data strobe (SDS)
Monitor channel
programming
Provided
(MON0, 1, 2, ..., 7)
Provided
(MON0 or 1)
C/I channels
CI0 (4 bit),
CI1 (4/6 bit)
CI0 (4 bit),
CI1 (6 bit)
Layer 1 state machine
With changes for
correspondence with the
actual ITU specification
Layer 1 state machine
in software
Not possible
Not possible
HDLC support
D- and B-channel timeslots;
non-auto mode,
transparent mode 1-3,
extended transparent mode
D-channel timeslot;
auto mode,
non-auto mode,
transparent mode 1-3
D-channel FIFO size
64 bytes cyclic buffer per
2x32 bytes buffer per
direction with programmable direction
FIFO thresholds
Reset Signals
RES input signal
RSTO output signal
RST input/output signal
Reset Sources
RES Input
Watchdog
C/I Code Change
EAW Pin
Software Reset
RST Input
Watchdog
C/I Code Change
EAW Pin
Interrupt Output Signals
INT
low active (open drain) by
default, reprogrammable to
high active (push-pull)
Low active INT
Pin SCLK
1.536 MHz
512 kHz
IOM-2
Data Sheet
14
2003-01-30
ISDN Subscriber Access Controller for Terminals
ISAC-SX TE
PSB/PSF 3186
V 1.4
1.1
Features
• Full duplex 2B + D S/T interface transceiver according
to ITU-T I.430
• Successor of ISAC-S TE PSB 2186 in
3.3 V technology
• 8-bit parallel microcontroller interface,
P-MQFP-64-1, -2, -3, -8
Motorola and Siemens/Intel bus type
multiplexed or non-multiplexed,
P-MQFP-64-1
direct-/indirect register addressing
• Serial control interface (SCI)
• Microcontroller access to all IOM-2 timeslots
• Various types of protocol support (Non-auto mode,
transparent mode, extended transparent mode)
• D-channel HDLC controller with 2 x 64 byte FIFOs
• IOM-2 interface in TE mode, single/double clocks
• One serial data strobe signal (SDS)
• Monitor channel handler (master/slave)
• IOM-2 MONITOR and C/I-channel protocol to control P-TQFP-64-1
peripheral devices
• Conversion of the frame structure between the S/T-interface and IOM-2
• Receive timing recovery
• D-channel access control
• Activation and deactivation procedures with automatic activation from power down
state
• Access to S and Q bits of S/T-interface
• Adaptively switched receive thresholds
• Two programmable timers
• Watchdog timer
• Software Reset
Type
Package
PSB 3186 H
P-MQFP-64-1
PSB 3186 F
P-TQFP-64-1
Data Sheet
15
2003-01-30
ISAC-SX TE
PSB 3186
Overview
•
•
•
•
•
•
One LED pin automatically indicating layer 1 activated state
Test loops
Sophisticated power management for restricted power mode
Power supply 3.3 V
3.3 V output drivers, inputs are 5 V safe
Advanced CMOS technology
Data Sheet
16
2003-01-30
ISAC-SX TE
PSB 3186
Overview
1.2
Logic Symbol
The logic symbol gives an overview of the ISAC-SX TE functions.
IOM-2 Interface
+3.3V 0V
DD
DU
FSC
DCL
BCL
SDS
0V
VDD VSS TP
VDDA VSSA
RD / DS
C768
WR / R/W
7.68 MHz output
ALE
Host
Interface
A0...7
XTAL2
AD0...4
XTAL1
7.68 MHz ± 100ppm
AD5 / SCL
AD6 / SDR
SR1
AD7 / SDX
SR2
CS
S Interface
SX1
INT
SX2
RES
RSTO
Figure 1
Data Sheet
ACL
AMODE
EAW
LED Output
Address
Mode
Setting
External
Awake
3186_17
Logic Symbol of the ISAC-SX TE
17
2003-01-30
ISAC-SX TE
PSB 3186
Overview
1.3
Typical Applications
The ISAC-SX TE is designed for the user area of the ISDN basic access, especially for
subscriber terminal equipment with S interface.
Figure 2 illustrates the general application fields of the ISAC-SX TE.
PBX (NT2)
TE(1)
TE(8)
S
CP
SN
TE(1)
U
T
LT-S
LT-T
NT1
LT-S
CP = Central
Processor
Line
Card
TE(1)
TE(8)
R
SN = Switching
Network
Direct Subscriber Access
(point-to-point, short and extended
passive Bus)
= ISAC -SSX
TETE
U
S
NT1
ITS05407
Figure 2
Data Sheet
Applications of the ISAC-SX TE
18
2003-01-30
ISAC-SX TE
PSB 3186
Pin Configuration
2
Pin Configuration
P-MQFP-64-1
VSS
VDD
XTAL1
AMODE
VSS
XTAL2
WR / R/W
RD / DS
n.c.
ALE
SX2
SX1
VDDA
VSSA
SR2
SR1
P-TQFP-64-1
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
BCL
DU
49
DD
FSC
54
55
27
26
C768
A7
25
A6
24
23
A5
DCL
VSS
VSS
VDD
32
res_c
50
31
51
52
53
30
29
28
res_c
res_c
ISAC-SX TE
PSB 3186
56
res_l
EAW
57
58
ACL
res_c
59
22
A4
A3
60
61
21
20
A2
A1
62
19
63
18
A0
VDD
64
17
VSS
Data Sheet
SDR / AD6
SDX / AD7
SCL / AD5
AD4
AD3
AD1
AD2
8 9 10 11 12 13 14 15 16
AD0
VSS
6 7
VDD
2 3 4 5
INT
n.c.
1
RES
RSTO
res_c
res_c
res_c
CS
TP
res_c
Figure 3
SDS
res.
3186_22
Pin Configuration of the ISAC-SX TE
19
2003-01-30
ISAC-SX TE
PSB 3186
Pin Configuration
Table 2
ISAC-SX TE Pin Definitions and Functions
Pin No. Symbol
MQFP-64
TQFP-64
Input (I)
Function
Output (O)
Open Drain
(OD)
Host Interface
19
20
21
22
23
24
25
26
A0
A1
A2
A3
A4
A5
A6
A7
I
I
I
I
I
I
I
I
• Non-Multiplexed Bus Mode:
Address Bus
Address bus transfers addresses from the
microcontroller to the ISAC-SX TE. For indirect
address mode only A0 is valid (A1-A7 to be
connected to VDD).
• Multiplexed Bus Mode:
Not used in multiplexed bus mode. In this case
A0-A7 should directly be connected to VDD.
9
10
11
12
13
AD0
AD1
AD2
AD3
AD4
I/O
I/O
I/O
I/O
I/O
• Multiplexed Bus Mode:
Address/data bus
Transfers addresses from the microcontroller to the
ISAC-SX TE and data between the microcontroller
and the ISAC-SX TE.
• Non-Multiplexed Bus Mode:
Data bus
Transfers data between the microcontroller and the
ISAC-SX TE.
14
AD5
I/O
• Multiplexed Bus Mode:
Address/data bus
Address/data line AD5 if the parallel interface is
selected.
• Non-Multiplexed Bus Mode:
Data bus
Data line D5 if the parallel interface is selected.
SCL
I
SCI - Serial Clock
Clock signal of the SCI interface if a serial interface
is selected.
Data Sheet
20
2003-01-30
ISAC-SX TE
PSB 3186
Pin Configuration
Table 2
ISAC-SX TE Pin Definitions and Functions (cont’d)
Pin No. Symbol
MQFP-64
TQFP-64
15
16
39
40
Input (I)
Function
Output (O)
Open Drain
(OD)
AD6
I/O
• Multiplexed Bus Mode:
Address/data bus
Address/data line AD6 if the parallel interface is
selected.
• Non-Multiplexed Bus Mode:
Data bus
Data line D6 if the parallel interface is selected.
SDR
I
SCI - Serial Data Receive
Receive data line of the SCI interface if a serial
interface is selected.
AD7
I/O
• Multiplexed Bus Mode:
Address/data bus
Address/data line AD7 if the parallel interface is
selected.
• Non-Multiplexed Bus Mode:
Data bus
Data line D7 if the parallel interface is selected.
SDX
OD
SCI - Serial Data Transmit
Transmit data line of the SCI interface if a serial
interface is selected.
RD
I
DS
I
Read
Indicates a read access to the registers (Siemens/
Intel bus mode).
Data Strobe
The rising edge marks the end of a valid read or
write operation (Motorola bus mode).
WR
I
R/W
I
Data Sheet
Write
Indicates a write access to the registers (Siemens/
Intel bus mode).
Read/Write
A HIGH identifies a valid host access as a read
operation and a LOW identifies a valid host access
as a write operation (Motorola bus mode).
21
2003-01-30
ISAC-SX TE
PSB 3186
Pin Configuration
Table 2
ISAC-SX TE Pin Definitions and Functions (cont’d)
Pin No. Symbol
MQFP-64
TQFP-64
Input (I)
Function
Output (O)
Open Drain
(OD)
41
ALE
I
Address Latch Enable
A HIGH on this line indicates an address on the
external address/data bus (multiplexed bus type
only).
ALE also selects the microcontroller interface bus
type (multiplexed or non multiplexed).
3
CS
I
Chip Select
A low level indicates a microcontroller access to the
ISAC-SX TE.
1
INT
OD (O)
Interrupt Request
INT becomes active low (open drain) if the ISAC-SX
TE requests an interrupt.
The polarity can be reprogrammed to high active
with push-pull characteristic.
5
RES
I
Reset
A LOW on this input forces the ISAC-SX TE into a
reset state.
38
AMODE
I
Address Mode
Selects between direct (0) and indirect (1) register
access mode.
IOM-2 Interface
52
FSC
O
Frame Sync
8-kHz frame synchronization signal.
53
DCL
O
Data Clock
IOM-2 interface data clock signal 1.536 MHz
(double bit clock).
49
BCL
O
Bit Clock
IOM-2 interface bit clock signal 768 kHz
(single bit clock).
51
DD
O (OD)
Data Downstream
IOM-2 data signal in downstream direction.
Data Sheet
22
2003-01-30
ISAC-SX TE
PSB 3186
Pin Configuration
Table 2
ISAC-SX TE Pin Definitions and Functions (cont’d)
Pin No. Symbol
MQFP-64
TQFP-64
Input (I)
Function
Output (O)
Open Drain
(OD)
50
DU
I
Data Upstream
IOM-2 data signal in upstream direction.
29
SDS
O
Serial Data Strobe
Programmable strobe signal for time slot and/or
D-channel indication on IOM-2.
Miscellaneous
43
44
SX1
SX2
O
O
S-Bus Transmitter Output (positive)
S-Bus Transmitter Output (negative)
47
48
SR1
SR2
I
I
S-Bus Receiver Input
S-Bus Receiver Input
35
XTAL1
I
36
XTAL2
O
Crystal 1
Connection for a crystal or used as external clock
input. 7.68 MHz clock or crystal required.
Crystal 2
Connection for a crystal. Not connected if an
external clock is supplied to XTAL1.
58
EAW
I
External Awake
If a falling edge on this input is detected, the ISACSX TE generates an interrupt and, if enabled, a
reset pulse.
59
ACL
O
Activation LED
This pin can either function as a programmable
output or it can automatically indicate the activated
state of the S interface by a logic ’0’.
An LED with pre-resistance may directly be
connected to ACL.
27
C768
O
Clock Output
A 7.68 MHz clock is output to support other devices.
This clock is not synchronous to the S interface.
6
RSTO
OD
Reset Output
Low active reset output, either from a watchdog
timeout or programmed by the host.
Data Sheet
23
2003-01-30
ISAC-SX TE
PSB 3186
Pin Configuration
Table 2
ISAC-SX TE Pin Definitions and Functions (cont’d)
Pin No. Symbol
MQFP-64
TQFP-64
Input (I)
Function
Output (O)
Open Drain
(OD)
4
TP
I
Test Pin
Must be connected to VSS.
2, 42
n.c.
I
not connected
28
res.
57
res_l
I
reserved, connect LOW
This pin is reserved and must be connected to VSS.
30, 31, res_c
32, 60,
61, 62,
63, 64
I
reserved, connect HIGH or LOW
These pins are reserved and must be connected
either to VSS or VDD.
reserved
This pin is reserved and should be left not
connected.
Power Supply
8, 18,
33, 56
VDD
–
Digital Power Supply Voltage
(3.3 V ± 5 %)
46
VDDA
–
Analog Power Supply Voltage
(3.3 V ± 5 %)
–
Digital ground
(0 V)
–
Analog ground
(0 V)
7, 17,
VSS
34, 37,
54, 55
45
VSSA
Data Sheet
24
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
3
Description of Functional Blocks
3.1
General Functions and Device Architecture
Figure 4 shows the architecture of the ISAC-SX TE containing the following functions:
• S/T-interface transceiver supporting TE mode
• Different host interface modes:
- Parallel microcontroller interface
(Siemens/Intel multiplexed, Siemens/Intel non multiplexed, Motorola modes)
- Serial Control Interface (SCI)
• Optional indirect register address mode reduces number of registers to be accessed
to two locations
• One D-channel HDLC-controller with 64 byte FlFOs per direction with programmable
FIFO block size (threshold) of 4, 8, 16 or 32 byte (receive) and 16 or 32 byte (transmit).
• IOM-2 interface for terminal mode (TE)
• One serial data strobe signals (SDS)
• IOM handler with controller data access registers (CDA) allows flexible access to IOM
timeslots for reading/writing, looping and shifting data
• Synchronous transfer interrupts (STI) allow controlled access to IOM timeslots
• MONITOR channel handler on IOM-2 for master mode, slave mode or data exchange
• C/I-channel handler and TIC bus access controller
• D-channel access mechanism
• LED connected to pin ACL indicates S-interface activation status automatically or can
be controlled by the host
• Level detect circuit on the S interface reduces power consumption in power down
mode
• Two timers for periodic or single interrupts (periods between 1 ms and 14.336 s)
• Clock and timing generation
• Digital PLL to synchronize the transceiver to the S/T interface
• Buffered 7.68 MHz oscillator clock output allows connection of further devices and
saves another crystal on the system board
• Reset generation (watchdog timer)
Data Sheet
25
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
Peripheral Devices
IOM-2 Interface
IOM-2 Handler
S Transceiver
D-channel
HDLC
MON
Handler
TIC
C/I
RX/TX
FIFOs
DPLL
Host Interface
8-bit parallel
Reset
Interrupt
-generation
SCI
OSC
3186_18
Host
Figure 4
Data Sheet
Functional Block Diagram of the ISAC-SX TE
26
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.2
Microcontroller Interfaces
The ISAC-SX TE supports a serial or a parallel microcontroller interface. For applications
where no controller is connected to the ISAC-SX TE microcontroller interface
programming is done via the IOM-2 MONITOR channel from a master device. In such
applications the ISAC-SX TE operates in the IOM-2 slave mode (refer to the
corresponding chapter of the IOM-2 MONITOR handler). This mode is suitable for
control functions (e.g. programming registers of the S/T transceiver), but the bandwidth
is not sufficient for access to the HDLC controllers.
The interface selections are all done by pinstrapping (see Table 3). The selection pins
are evaluated when the reset input RES is active. For the pin levels stated in the tables
the following is defined:
’High’, ’Low’: dynamic pin; value must be ’High’ or ’Low’ only during reset
static pin; pin must statically be strapped to ’High’ or ’Low’ level
VDD, VSS:
edge:
dynamic pin; any transition (’High’ to ’Low’, ’Low’ to ’High’) has occured
Table 3
Host Interface Selection
PINS
WR
(R/W)
RD
(DS)
Serial /Parallel
PINS
Interface
CS
ALE
VDD
’High’
’High’ Parallel
‘High’ VSS
edge
VSS
VSS
Serial
’High’ VSS
VSS
No
Host Interface
VSS
Interface
Type/Mode
Motorola
Siemens/Intel Non-Mux
Siemens/Intel Mux
Serial Control Interface(SCI)
IOM-2 MONITOR Channel
(Slave Mode)
Note: For a selected interface mode which doesn’t need all input selection and address
pins the unused pins must be tied to VDD or VSS.
The interfaces contain all circuitry necessary for the access to programmable registers,
status registers and HDLC FIFOs. The mapping of all these registers can be found in
Chapter 4.
The microcontroller interface also provides an interrupt request at pin INT which is low
active by default but can be reprogrammed to high active, a reset input pin RES and a
reset output pin RSTO.
The interrupt request pin INT becomes active if the ISAC-SX TE requests an interrupt
and this can occur at any time.
Data Sheet
27
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.2.1
Serial Control Interface (SCI)
The serial control interface (SCI) is compatible to the SPI interface of Motorola or
Siemens C510 family of microcontrollers.
The SCI consists of 4 lines: SCL, SDX, SDR and CS. Data is transferred via the lines
SDR and SDX at the rate given by SCL. The falling edge of CS indicates the beginning
of a serial access to the registers. The ISAC-SX TE latches incoming data at the rising
edge of SCL and shifts out at the falling edge of SCL. Each access must be terminated
by a rising edge of CS. Data is transferred in groups of 8 bits with the MSB first.
Figure 5 shows the timing of a one byte read/write access via the serial control interface.
Write Access
CS
SCL
Header
SDR
Address
Data
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
'0'
write
SDX
Read Access
CS
SCL
Header
SDR
Address
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
'1'
read
Data
7 6 5 4 3 2 1 0
SDX
21150_19
Figure 5
Data Sheet
Serial Control Interface Timing
28
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.2.1.1
Programming Sequences
The basic structure of a read/write access to the ISAC-SX TE registers via the serial
control interface is shown in Figure 6.
write sequence:
write
byte 2
0
header
SDR
7
address
0 7 6
read sequence:
byte 3
write data
0 7
0
read
byte 2
header
SDR
7
1
address
0 7 6
0 7
SDX
Figure 6
byte 3
0
read data
Serial Control Interface Timing
A new programming sequence starts with the transfer of a header byte. The header byte
specifies different programming sequences allowing a flexible and optimized access to
the individual functional blocks of the ISAC-SX TE.
The possible sequences for access to the complete address range 00H-7FH are listed in
Table 4 and described after that.
Table 4
Header
Byte
Header Byte Code
Sequence
40H/44H
48H/4CH
Alternating Read/Write (non-interleaved)
Adr-Data-Adr-Data
43H/47H
41H/45H
49H/4DH
Sequence Type
Alternating Read/Write (interleaved)
Read-only/Write-only (constant address)
Adr-Data-Data-Data
Read and following Write-only (non-interleaved)
Read and following Write-only (interleaved)
Note: In order to access the address range 00H-7FH bit 2 of the header byte must be set
to ’0’ (header bytes 40H, 48H, 43H, 41H, 49H), and for the addresses 80H-FFH bit 2
must be set to ’1’ (header bytes 44H, 4CH, 47H, 45H, 4DH).
Data Sheet
29
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
Header 40H: Non-interleaved A-D-A-D Sequences
The non-interleaved A-D-A-D sequence gives direct read/write access to the complete
address range and can have any length. In this mode SDX and SDR can be connected
together allowing data transmission on one line.
Example for a read/write access with header 40H:
SDR header wradr wrdata
rdadr
SDX
rdadr
rddata
wradr wrdata
rdata
Header 48H: Interleaved A-D-A-D Sequences
The interleaved A-D-A-D sequence gives direct read/write access to the complete
address range and can have any length. This mode allows a time optimized access to
the registers by interleaving the data on SDX and SDR (SDR and SDX must not be
connected together).
Example for a read/write access with header 48H:
SDR header wradr wrdata
rdadr
SDX
rdadr
wradr wrdata
rddata rddata
Header 43H: Read-/Write- only A-D-D-D Sequence (Constant Address)
This mode can be used for a fast access to the HDLC FIFO data. Any address (rdadr,
wradr) in the range 00H-1FH and 6AH/7AH gives access to the current FIFO location
selected by an internal pointer which is automatically incremented with every data byte
following the first address byte. The sequence can have any length and is terminated by
the rising edge of CS.
Example for a write access with header 43H:
SDR header wradr wrdata wrdata wrdata wrdata wrdata wrdata wrdata
(wradr)
(wradr)
(wradr)
(wradr)
(wradr)
(wradr)
(wradr)
SDX
Example for a read access with header 43H:
SDR header rdadr
SDX
rddata rddata rddata rddata rddata rddata rddata
(rdadr)
Data Sheet
(rdadr)
(rdadr)
30
(rdadr)
(rdadr)
(rdadr)
(rdadr)
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
Header 41H: Non-interleaved A-D-D-D Sequence
This sequence allows in front of the A-D-D-D write access a non-interleaved A-D-A-D
read access. This mode is useful for reading status information before writing to the
HDLC XFIFO. The termination condition of the read access is the reception of the wradr.
The sequence can have any length and is terminated by the rising edge of CS.
Example for a read/write access with header 41H:
SDR header rdadr
wradr wrdata wrdata wrdata
rdadr
(wradr)
SDX
rddata
(wradr)
(wradr)
rddata
Header 49H: Interleaved A-D-D-D Sequence
This sequence allows in front of the A-D-D-D write access an interleaved A-D-A-D read
access. This mode is useful for reading status information before writing to the HDLC
XFIFO. The termination condition of the read access is the reception of the wradr. The
sequence can have any length and is terminated by the rising edge of the CS line.
Example for a read/write access with header 49H:
SDR header rdadr
rdadr
wradr wrdata wrdata wrdata
(wradr)
SDX
3.2.2
(wradr)
(wradr)
rddata rddata
Parallel Microcontroller Interface
The 8-bit parallel microcontroller interface with address decoding on chip allows easy
and fast microcontroller access.
The parallel interface of the ISAC-SX TE provides three types of mP buses which are
selected via pin ALE. The bus operation modes with corresponding pins are listed in
Table 5.
Table 5
Bus Operation Modes
Bus Mode
Pin ALE
Control Pins
(1)
Motorola
VDD
CS, R/W, DS
(2)
Siemens/Intel non-multiplexed
VSS
CS, WR, RD
(3)
Siemens/Intel multiplexed
Edge
CS, WR, RD, ALE
The occurrence of an edge on ALE, either positive or negative, at any time during the
operation immediately selects the interface type (3). A return to one of the other interface
types is possible only if a hardware reset is issued.
Data Sheet
31
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
Note: If the multiplexed address/data bus type (3) is selected, the unused address pins
A0-A7 must be tied to VDD.
A read/write access to the ISAC-SX TE registers can be done in multiplexed or nonmultiplexed mode:
• In non-multiplexed mode the register address must be applied to the address bus (A0A7) for the data access via the data bus (AD0-AD7).
• In multiplexed mode the address on the address/data bus (AD0-AD7) is latched in by
ALE before a data read/write access via the same bus is performed.
The ISAC-SX TE provides two different ways to address the register contents which is
selected with the AMOD pin (’0’ = direct mode, ’1’ = indirect mode). Figure 7 illustrates
both register addressing modes.
Direct address mode (AMOD = ’0’): The register address to be read or written is directly
set in the way described above.
Indirect address mode (AMOD = ’1’): Only the LSB of the address is used to select
either the address register (A0 = ’0’) or the data register (A0 = ’1’). The microcontroller
writes the register address to the ADDRESS register before it reads/writes data from/to
the corresponding DATA register.
In indirect address mode the ISAC-SX TE evaluates no address line except the least
significant address bit. The remaining address lines must not be left open but have to be
tied to logical ’1’.
Indirect Address Mode
MODE2:AMOD=1
Address
A0
Direct Address Mode
MODE2:AMOD=0
Data
AD0-7
Address
A0-7
Data
AD0-7
8Fh
8Eh
Address
1h
0h
Data
:
:
01h
00h
DATA
ADDRESS
21150_11
Figure 7
Data Sheet
Direct/Indirect Register Address Mode
32
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.2.3
Interrupt Structure
Special events in the device are indicated by means of a single interrupt output, which
requests the host to read status information from the device or transfer data from/to the
device.
Since only one interrupt request pin (INT) is provided, the cause of an interrupt must be
determined by the host reading the interrupt status registers of the device.
The structure of the interrupt status registers is shown in Figure 8.
MASK
ISTA
ST
ST
CIC
CIC
AUX
AUX
TRAN
TRAN
MOS
MOS
ICD
ICD
Interrupt
STI
STOV21
ASTI
STOV20
STOV20
STOV11
STOV11
STOV10
STOV10
STI21
STI21
ACK21
STI20
STI20
ACK20
STI11
STI11
ACK11
STI10
STI10
ACK10
RME
RME
RPF
RPF
RFO
RFO
CIX1
CIR0
CIC0
CI1E
CIC1
EAW
EAW
LD
WOV
WOV
RIC
RIC
TIN2
TIN2
SQC
SQC
TIN1
LD
SQW
MASKTR
SQW
ISTATR
XPR
XPR
XMR
XMR
MRE
XDU
MASKD
XDU
ISTAD
MIE
MDA
MOCR
MAB
MOSR
D-channel
Figure 8
MSTI
STOV21
AUXM
TIN1
AUXI
MDR
MER
3186_16.vsd
Interrupt Status and Mask Registers
All six interrupt bits in the ISTA register point at interrupt sources in the D-channel HDLC
Controller (ICD), Monitor- (MOS) and C/I- (CIC) handler, the transceiver (TRAN), the
synchronous transfer (ST) and the auxiliary interrupts (AUXI).
All these interrupt sources are described in the corresponding chapters. After the device
has requested an interrupt activating the interrupt pin (INT), the host must read first the
device interrupt status register (ISTA) in the associated interrupt service routine. The
interrupt pin of the device remains active until all interrupt sources are cleared by reading
the corresponding interrupt register. Therefore it is possible that the interrupt pin is still
active when the interrupt service routine is finished.
Each interrupt indication of the interrupt status registers can selectively be masked by
setting the respective bit in the MASK register.
For some interrupt controllers or hosts it might be necessary to generate a new edge on
the interrupt line to recognize pending interrupts. This can be done by masking all
interrupts at the end of the interrupt service routine (writing FFH into the MASK register)
and write back the old mask to the MASK register.
Data Sheet
33
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.2.4
Reset Generation
Figure 9 shows the organization of the reset generation of the device.
.
RSS1
125µs £ t £ 250µs
C/I Code Change
(Exchange Awake)
³1
EAW
(Subscriber Awake)
125µs £ t £ 250µs
'0'
(reserved)
RSS2,1
'1x'
'1'
'01'
'00'
³1
' 01 '
RSS2,1
125µs £ t £ 250µs
Watchdog
Software Reset
Register (SRES)
Pin
RSTO
³1
125µs £ t £ 250µs
D, C/I-channel (00H-2FH)
Transceiver (30H-3FH)
Reset
Functional IOM-2 (40H-5BH)
Block
MON-channel (5CH-5FH)
General Config (60H-6FH)
Reset MODE1 Register
Pin
RES
Internal Reset of all Registers
3186_21
Figure 9
Reset Generation
Reset Source Selection
The internal reset sources C/I code change, EAW and Watchdog can be output at the
low active reset pin RSTO. The selection of these reset sources can be done with the
RSS2,1 bits in the MODE1 register according Table 6.
The setting RSS2,1 = ’01’ is reserved for further use. In this case no reset except
software reset (SRES.RSTO) is output on RSTO. The internal reset sources set the
MODE1 register to its reset value.
Table 6
Reset Source Selection
RSS2 Bit 1
RSS1 Bit 0
C/I Code
Change
EAW
Watchdog
Timer
0
0
--
--
--
0
1
1
0
x
x
--
1
1
--
--
x
Data Sheet
reserved
34
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
• C/I Code Change (Exchange Awake)
A change in the downstream C/I channel (C/I0) generates an external reset pulse of
125 µs £ t £ 250 µs.
• EAW (Subscriber Awake)
A low level on the EAW input starts the oscillator from the power down state and
generates a reset pulse of 125 µs £ t £ 250 µs.
• Watchdog Timer
After the selection of the watchdog timer (RSS = ’11’) an internal timer is reset and
started. During every time period of 128 ms the microcontroller has to program the
WTC1- and WTC2 bits in the following sequence to reset and restart the watchdog timer:
1.
2.
WTC1
WTC2
1
0
0
1
If not, the timer expires and a WOV-interrupt (ISTA Register) together with a reset pulse
of 125 µs is generated.
Deactivation of the watchdog timer is only possible with a hardware reset.
External Reset Input
At the RES input an external reset can be applied forcing the device in the reset state.
This external reset signal is additionally fed to the RSTO output. The length of the reset
signal is specified in Chapter 5.8.
After an external reset from the RES pin all registers of the device are set to its reset
values (see register description in Chapter 4).
Software Reset Register (SRES)
Every main functional block of the device can be reset separately by software setting the
corresponding bit in the SRES register. A reset to external devices can also be controlled
in this way. The reset state is activated by setting the corresponding bit to ’1’ and onchip
logic resets this bit again automatically after 4 BCL clock cycles. The address range of
the registers which will be reset at each SRES bit is listed in Figure 9.
3.2.5
Timer Modes
The ISAC-SX TE provides two timers which can be used for various purposes. Each of
them provides two modes (Table 7), a count down timer interrupt, i.e. an interrupt is
generated only once after expiration of the selected period, and a periodic timer interrupt,
which means an interrupt is generated continuously after every expiration of that period.
Data Sheet
35
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
Table 7
Address
24H
65H
ISAC-SX TE Timers
Register
TIMR1
TIMR2
Modes
Period
Periodic
64 ... 2048 ms
Count Down
64 ms ... 14.336 s
Periodic
1 ... 63 ms
Count Down
1 ... 63 ms
When the programmed period has expired an interrupt is generated and indicated in the
auxiliary interrupt status ISTA.AUX. The source of the interrupt can be read from AUXI
(TIN1, TIN2) and each of the interrupt sources can be masked in AUXM.
MASK
ST
CIC
AUX
TRAN
MOS
ICD
ISTA
AUXM
EAW
WOV
TIN2
TIN1
ST
CIC
AUX
TRAN
MOS
ICD
AUXI
EAW
WOV
TIN2
TIN1
Interrupt
Figure 10
Timer Interrupt Status Registers
Timer 1
The host controls the timer 1 by setting bit CMDRD.STI to start the timer and by writing
register TIMR1 to stop the timer. After time period T1 an interrupt (AUXI.TIN1) is
generated continuously if CNT= 7 or a single interrupt is generated after timer period T
if CNT<7 (Figure 11).
Data Sheet
36
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
Retry Counter
0 ... 6 : Count Down Timer
7 : Periodic Timer
T = CNT x 2.048 sec + T1
T = T1
Expiration Period
T1 = (VALUE + 1) x 0.064 sec
7 6 5 4 3 2 1 0
TIMR1
Figure 11
CNT
VALUE
24H
21150_14
Timer 1 Register
Timer 2
The host starts and stops timer 2 in TIMR2.CNT (Figure 12). If TIMR2.TMD=0 the timer
is operating in count down mode, for TIMR2.TMD=1 a periodic interrupt AUXI.TIN2 is
generated. The timer length (for count down timer) or the timer period (for periodic timer),
respectively, can be configured to a value between 1 - 63 ms (TIMR2.CNT).
Timer Mode
0 : Count Down Timer
1 : Periodic Timer
Timer Count
0 : Timer off
1 ... 63 : 1 ... 63 ms
7
TIMR2
Figure 12
Data Sheet
6
5
TMD 0
4
3
CNT
2
1
0
65H
21150_14
Timer 2 Register
37
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.2.6
Activation Indication via Pin ACL
The activated state of the S-interface is directly indicated via pin ACL (Activation LED).
An LED with pre-resistance may directly be connected to this pin and a low level is driven
on ACL as soon as the layer 1 state machine reaches the activated state (see
Figure 13).
Figure 13
ACL Indication of Activated Layer 1
By default (ACFG2.ACL=0) the state of layer 1 is indicated at pin ACL. If the automatic
indication of the activated layer 1 is not required, the state on pin ACL can also be
controlled by the host (see Figure 14).
If ACFG2.ACL=1 the LED on pin ACL can be switched on (ACFG2.LED=1) and off
(ACFG2.LED=0) by the host.
+3.3V
'1'
ACL
ACFG2:LED
0 : off
1 : on
'0'
Layer 1
S Interface
ACFG2:ACL
3086_15
Figure 14
Data Sheet
ACL Configuration
38
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.3
S/T-Interface
The layer-1 functions for the S/T interface of the ISAC-SX TE are:
– line transceiver functions for the S/T interface according to the electrical specifications
of ITU-T I.430;
– conversion of the frame structure between IOM-2 and S/T interface;
– conversion from/to binary to/from pseudo-ternary code;
– level detection
– receive timing recovery for point-to-point, passive bus and extended passive bus
configuration
– S/T timing generation using IOM-2 timing synchronous to system, or vice versa;
– D-channel access control and priority handling;
– D-channel echo bit generation by handling of the global echo bit;
– activation/deactivation procedures, triggered by primitives received over the IOM-2
C/I channel or by INFO's received from the line;
– execution of test loops.
The wiring configurations in user premises, in which the ISAC-SX TE can be used, are
illustrated in Figure 15.
Data Sheet
39
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
£ 1000 m 1)
ISAC-SX TE
TR
TR
ISAC-SX
TE
LT-S
Point-to-Point
Configuration
1) The maximum line attenuation tolerated by the ISAC-SX TE is 7 dB at 96 kHz.
£ 100 m
TR
TR
£ 10 m
ISAC-SX TE
....
TE1
ISAC-SX
Short
Passive Bus
NT / LT-S
ISAC-SX TE
TE8
£ 500 m
£ 25 m
TR
TR
£ 10 m
ISAC-SX TE
TE1
Figure 15
3.3.1
....
ISAC-SX
Extended
Passive Bus
NT / LT-S
TR: Terminating Resistor
ISAC-SX TE
TE8
3186_20
Wiring Configurations in User Premises
S/T-Interface Coding
Transmission over the S/T-interface is performed at a rate of 192 kbit/s. 144 kbit/s are
used for user data (B1+B2+D), 48 kbit/s are used for framing and maintenance
information.
Line Coding
The following figure illustrates the line code. A binary ONE is represented by no line
signal. Binary ZEROs are coded with alternating positive and negative pulses with two
exceptions:
For the required frame structure a code violation is indicated by two consecutive pulses
of the same polarity. These two pulses can be adjacent or separated by binary ONEs.
In bus configurations a binary ZERO always overwrites a binary ONE.
Data Sheet
40
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
0 1 1
code violation
Figure 16
S/T -Interface Line Code
Frame Structure
Each S/T frame consists of 48 bits at a nominal bit rate of 192 kbit/s. For user data
(B1+B2+D) the frame structure applies to a data rate of 144 kbit/s (see Figure 17).
In the direction TE ® NT the frame is transmitted with a two bit offset. For details on the
framing rules please refer to ITU I.430 section 6.3. The following figure illustrates the
standard frame structure for both directions (NT ® TE and TE ® NT) with all framing
and maintenance bits.
Figure 17
Frame Structure at Reference Points S and T (ITU I.430)
Note: The ITU I.430 standard specifies S1 - S5 for optional use.
Data Sheet
41
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
– F
Framing Bit
F = (0b) ® identifies new frame (always
positive pulse, always code violation)
– L.
D.C. Balancing Bit
L. = (0b) ® number of binary ZEROs sent
after the last L. bit was odd
– D
D-Channel Data Bit
Signaling data specified by user
– E
D-Channel Echo Bit
E = D ® received E-bit is equal to transmitted
D-bit
– FA
Auxiliary Framing Bit
See section 6.3 in ITU I.430
– N
N = FA
– B1
B1-Channel Data Bit
User data
– B2
B2-Channel Data Bit
User data
– A
Activation Bit
A = (0b) ® INFO 2 transmitted
A = (1b) ® INFO 4 transmitted
– S
S-Channel Data Bit
S1 channel data (see note below)
– M
Multiframing Bit
M = (1b) ® Start of new multiframe
3.3.2
S/T-Interface Multiframing
According to ITU recommendation I.430 a multiframe provides extra layer 1 capacity in
the TE-to-NT direction by using an extra channel between the TE and NT (Q-channel).
The Q bits are defined to be the bits in the FA bit position.
In the NT-to-TE direction the S-channel bits are used for information transmission. One
S channel (S1) out of five possible S-channels can be accessed by the ISAC-SX TE.
In the NT-to-TE direction the S-channel bits are used for information transmission.
The S and Q channels are accessed via the µC interface or the IOM-2 MONITOR
channel, respectively, by reading/writing the SQR or SQX bits in the S/Q channel
registers (SQRRx, SQXRx).
Table 8 shows the S and Q bit positions within the multiframe.
Table 8
S/Q-Bit Position Identification and Multiframe Structure
After multiframe synchronization has been established, the Q data will be inserted at the
upstream (TE ® NT) FA bit position in each 5th S/T frame (see Table 8).
When synchronization is not achieved or lost, each received FA bit is mirrored to the next
transmitted FA bit.
Multiframe synchronization is achieved after two complete multiframes have been
detected with reference to FA/N bit and M bit positions. Multiframe synchronization is lost
if bit errors in FA/N bit or M bit positions have been detected in two consecutive
Data Sheet
42
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
Frame Number
NT-to-TE
NT-to-TE
FA Bit Position M Bit
NT-to-TE
S Bit
TE-to-NT
FA Bit Position
1
2
3
4
5
ONE
ZERO
ZERO
ZERO
ZERO
ONE
ZERO
ZERO
ZERO
ZERO
S11
S21
S31
S41
S51
Q1
ZERO
ZERO
ZERO
ZERO
6
7
8
9
10
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
S12
S22
S32
S42
S52
Q2
ZERO
ZERO
ZERO
ZERO
11
12
13
14
15
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
S13
S23
S33
S43
S53
Q3
ZERO
ZERO
ZERO
ZERO
16
17
18
19
20
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
S14
S24
S34
S44
S54
Q4
ZERO
ZERO
ZERO
ZERO
1
2
ONE
ZERO
ONE
ZERO
S11
S21
Q1
ZERO
multiframes. The synchronization state is indicated by the MSYN bit in the S/Q-channel
receive register (SQRR1).
The multiframe synchronization can be enabled or disabled by programming the MFEN
bit in the S/Q-channel transmit register (SQXR1).
Interrupt Handling for Multiframing
To trigger the microcontroller for a multiframe access an interrupt can be generated once
per multiframe (SQW) or if the received S-channels have changed (SQC).
In both cases the microcontroller has access to the multiframe within the duration of one
multiframe (5 ms).
Data Sheet
43
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.3.3
Data Transfer and Delay between IOM-2 and S/T
In the state F7 (Activated) the B1, B2, D and E bits are transferred transparently from the
S/T to the IOM-2 interface. In all other states ’1’s are transmitted to the IOM-2 interface.
To transfer data transparently to the S/T interface any activation request C/I command
(AR8, AR10 or ARL) is additionally necessary . Figure 18 shows the data delay between
the IOM-2 and the S/T interface and vice versa.
For the D channel the delay from the IOM-2 to the S/T interface is only valid if S/G
evaluation is disabled (MODED.DIM0=0). If S/G evaluation is enabled
(MODED.DIM2-0=0x1) the delay depends on the selected priority and the relation
between the echo bits on S and the D channel bits on the IOM-2, e.g. for priority 8 the
timing relation between the 8th D-bit on S bus and the D-channel on IOM-2.
E
NT -> TE
F
D
E
B1
B2
D
TE -> NT
F
B1
B2
D
E
D
E
B1
B2
D
D
B1
D
E
F
E
B1
D
B2
D
F
B2
D
B1
B2
D
E
D
E
B1
B2
D
D
B1
D
D
B2
FSC
DU
B1 B2 D
B1 B2 D
B1 B2 D
B1 B2 D
DD
B1 B2 D
Figure 18
Data Sheet
E
B1 B2 D
E
B1 B2 D
E
B1 B2 D
E
line_iom_s.vsd
Data Delay between IOM-2 and S/T Interface
44
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
E
NT -> TE
F
D
E
B1
B2
D
TE -> NT
F
B1
B2
D
E
D
E
B1
B2
D
D
B1
D
E
F
E
B1
D
B2
D
F
B2
D
B1
D
E
D
E
B1
B2
D
D
B2
B1
D
D
B2
FSC
DU
B1 B2 D
B1 B2 D
B1 B2 D
B1 B2 D
DD
B1 B2 D
E
B1 B2 D
E
B1 B2 D
E
B1 B2 D
Mapping of B-Channel Timeslots
Mapping of a 4-bit group of D-bits on S and IOM depends on prehistory (e.g. priority control):
1. Possibility
2. Possibility
Figure 19
3.3.4
E
line_iom_s_dch.vsd
Data Delay between IOM-2 and S/T Interface with S/G Bit Evaluation
Transmitter Characteristics
The full-bauded pseudo-ternary pulse shaping is achieved with the integrated transmitter
which is realized as a symmetrical current limited voltage source (VSX1/SX2 = +/-1.0 V;
Imax = 26 mA). The equivalent circuit of the transmitter is shown in Figure 20.
The nominal pulse amplitude on the S-interface 750 mV (zero-peak) is adjusted with
external resistors (see Chapter 3.3.6.1).
Data Sheet
45
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
'+0'
VCM+0.525V
VCM
VCM-0.525V
'1'
'-0'
+
SX1
V=1
-
Level
'+0'
VCM-0.525V
VCM
VCM+0.525V
Figure 20
3.3.5
'1'
'+0' '1' '-0'
TR_CONF2.DIS_TX
VCM
-
SX2
V=1
+
'-0'
21150_28
Equivalent Internal Circuit of the Transmitter Stage
Receiver Characteristics
The receiver consists of a differential input stage, a peak detector and a set of
comparators. Additional noise immunity is achieved by digital oversampling after the
comparators. A simplified equivalent circuit of the receiver is shown in Figure 21.
100 kW
10 kW
SR1
40 kW
VrefLD
Level detected
Vrefmin
10 kW
SR2
40 kW
VCM
Vref+
Positive detected
Peak
Detector Vref-
Negative detected
reccirc
Figure 21
Equivalent Internal Circuit of the Receiver Stage
The input stage works together with external 10 kW resistors to match the input voltage
to the internal thresholds. The data detection threshold Vref is continuously adapted
between a maximal (Vrefmax) and a minimal (Vrefmin) reference level related to the line
level. The peak detector requires maximum 2 ms to reach the peak value while storing
the peak level for at least 250 ms (RC > 1 ms).
The additional level detector for power up/down control works with a fixed thresholds
VrefLD. The level detector monitors the line input signals to detect whether an INFO is
present. When closing an analog loop it is therefore possible to indicate an incoming
signal during activated loop.
Data Sheet
46
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.3.6
S/T Interface Circuitry
For both, receive and transmit direction a 1:1 transformer is used to connect the ISACSX TE transceiver to the 4 wire S/T interface. Typical transformer characteristics can be
found in the chapter on electrical characteristics. The connections of the line
transformers is shown in Figure 22.
3.3 V
1:1
SX1
VDD
Protection
Circuit
Transmit
Pair
SX2
10 µF
1:1
SR1
Protection
Circuit
VSS
GND
Receive
Pair
SR2
21150_05
Figure 22
Connection of Line Transformers and Power Supply to the ISAC-SX
TE
For the transmit direction an external transformer is required to provide isolation and
pulse shape according to the ITU-T recommendations.
3.3.6.1
External Protection Circuitry
The ITU-T I.430 specification for both transmitter and receiver impedances in TEs results
in a conflict with respect to external S-protection circuitry requirements:
– To avoid destruction or malfunction of the S-device it is desirable to drain off even
small overvoltages reliably.
– To meet the 96 kHz impedance test specified for transmitters and receivers (for TEs
only, ITU-T I.430 sections 8.5.1.2a and 8.6.1.1) the protection circuit must be
dimensioned such that voltages below 1.2 V (ITU-T I.430 amplitude) x transformer
ratio are not affected.
This requirement results from the fact that this test is also to be performed with no supply
voltage being connected to the TE. Therefore the second reference point for
overvoltages VDD, is tied to GND. Then, if the amplitude of the 96 kHz test signal is
greater than the combined forward voltages of the diodes, a current exceeding the
specified one may pass the protection circuit.
The following recommendations aim at achieving the highest possible device protection
against overvoltages while still fulfilling the 96 kHz impedance tests.
Data Sheet
47
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
Protection Circuit for Transmitter
SX1
1:1
R
S Bus
Vdd
SX2
R
3186_23
Figure 23
External Circuitry for Transmitter
Figure 23 illustrates the secondary protection circuit recommended for the transmitter.
The external resistors (R = 5 ... 10 W) are required in order to adjust the output voltage
to the pulse mask on the one hand and in order to meet the output impedance of
minimum 20 W (transmission of a binary zero according to ITU-T I.430) on the other
hand.
Two mutually reversed diode paths protect the device against positive or negative
overvoltages on both lines.
An ideal protection circuit should limit the voltage at the SX pins from – 0.4 V to VDD
+ 0.4 V. With the circuit In Figure 23 the pin voltage range is increased from – 1.4 V to
VDD + 0.7 V. The resulting forward voltage of 1.4 V will prevent the protection circuit from
becoming active if the 96 kHz test signal is applied while no supply voltage is present.
Protection Circuit for Receiver
Figure 24 illustrates the external circuitry used in combination with a symmetrical
receiver. Protection of symmetrical receivers is rather simple.
Data Sheet
48
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
1:1
S Bus
Note: up to 10 pF capacitors are optional for noise reduction
Figure 24
External Circuitry for Symmetrical Receivers
Between each receive line and the transformer a 10 kW resistor is used. This value is
split into two resistors: one between transformer and protection diodes for current limiting
during the 96 kHz test, and the second one between input pin and protection diodes to
limit the maximum input current of the chip.
With symmetrical receivers no difficulties regarding LCL measurements are observed;
compensation networks thus are obsolete.
In order to comply to the physical requirements of ITU-T recommendation I.430 and
considering the national requirements concerning overvoltage protection and
electromagnetic compatibility (EMC), the ISAC-SX TE may need additional circuitry.
Data Sheet
49
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.3.6.2
S-Transceiver Synchronization
Synchronization problems can occur on a S-Bus that is not terminated properly.
Therefore, it is recommended to change the resistor values in the receive path. The sum
of both resistors is increased from 10 kW (1.8 + 8.2) to e.g. 34 kW (6.8 + 27) for either
receiver line. This change is possible but not necessary for a S-Bus that is terminated
properly.
R1
R2
SR2
GND
VDD
1:1
S Bus
SR1
R1
R2
21150_33
Note: Capacitors (up to 10 pF) are optional for noise reduction.
Figure 25
External Circuitry for Symmetrical Receivers
Note: Lower or higher values than 34 kW may be used as well, however for values above
34 kW the additional delay must be compensated by setting TR_CONF2.PDS=1
(compensates 260 ns) so the allowed input phase delay is not violated.
3.3.7
S/T Interface Delay Compensation
The S/T transmitter is shifted by two S/T bits minus 7 oscillator periods (plus analog
delay plus delay of the external circuitry) with respect to the received frame. To
compensate additional delay introduced into the receive and transmit path by the
external circuit the delay of the transmit data can be reduced by another two oscillator
periods (2 x 130 ns). Therefore PDS of the TR_CONF2 register must be programmed to
’1’. This delay compensation might be necessary in order to comply with the "total phase
deviation input to output" requirement of ITU-T recommendation I.430 which specifies a
phase deviation in the range of – 7% to + 15% of a bit period.
3.3.8
Level Detection Power Down
If MODE1.CFS is set to ’0’, the clocks are also provided in power down state, whereas
if CFS is set to ’1’ only the analog level detector is active in power down state. All clocks,
including the IOM-2 interface, are stopped (DD, DU are ’high’, DCL and BCL are ’low’).
Data Sheet
50
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
An activation initiated from the exchange side will have the consequence that a clock
signal is provided automatically if TR_CONF0.LDD is set to ’0’. If TR_CONF0.LDD is set
to ’1’ the microcontroller has to take care of an interrupt caused by the level detect circuit
(ISTATR.LD)
From the terminal side an activation must be started by setting and resetting the SPUbit in the IOM_CR register and writing TIM to the CIX0 register or by resetting
MODE1.CFS=0.
3.3.9
Transceiver Enable/Disable
The layer-1 part of the ISAC-SX TE can be enabled/disabled by configuration (see
Figure 26) with the two bits TR_CONF0.DIS_TR and TR_CONF2.DIS_TX .
By default all layer-1 functions with the exception of the transmitter buffer is enabled
(DIS_TR = ’0’, DIS_TX = ’1’). With several terminals connected to the S/T interface,
another terminal may keep the interface activated although the ISAC-SX TE does not
establish a connection. The receiver will monitor for incoming calls in this configuration.
If the transceiver is disabled (DIS_TR = ’1’) all layer-1 functions are disabled including
the level detection circuit of the receiver. In this case the power consumption of the
Layer-1 is reduced to a minimum. The HDLC controller can still operate via IOM-2. The
DCL and FSC pins become input.
TR_CONF0.DIS_TR
TR_CONF2.DIS_TX
’1’
’0’
Figure 26
Disabling of S/T Transmitter
Data Sheet
51
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.3.10
Test Functions
The ISAC-SX TE provides test and diagnostic functions for the S/T interface:
Note: For more details please refer to the application note “Test Function of new STransceiver family”
– The internal local loop (internal Loop A) is activated by a C/I command ARL.
The transmit data of the transmitter is looped back internally to the receiver. The data
of the IOM-2 input B- and D-channels are looped back to the output B- and Dchannels.
The S/T interface level detector is enabled, i.e. if a level is detected this will be
reported by the Resynchronization Indication (RSY) but the loop function is not
affected.
Depending on the DIS_TX bit in the TR_CONF2 register the internal local loop can be
transparent or non transparent to the S/T line.
– The external local loop (external Loop A) is activated in the same way as the internal
local loop described above. Additionally the EXLP bit in the TR_CONF0 register has
to be programmed and the loop has to be closed externally as described in Figure 27.
The S/T interface level detector is disabled.
This allows complete system diagnostics.
– In remote line loop (RLP) received data is looped back to the S/T interface. The Dchannel information received from the line card is transparently forwarded to the
output
IOM-2 D-channel. The output B-channel information on IOM-2 is fixed to ‘FF’H while
this test loop is active. The remote loop is programmable in TR_CONF2.RLP.
SX1
100 W
SX2
SCOUT-S(X)
SR1
100 W
SR2
Figure 27
Data Sheet
External Loop at the S/T-Interface
52
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
– transmission of special test signals on the S/T interface according to the modified AMI
code are initiated via a C/I command written in CIX0 register (see Chapter 3.5.2)
Two kinds of test signals may be transmitted by the ISAC-SX:
– The single pulses are of alternating polarity. One pulse is transmitted in each frame
resulting in a frequency of the fundamental mode of 2 kHz. The corresponding C/I
command is SSP (Send Single Pulses).
– The continuous pulses are of alternating polarity. 48 pulses are transmitted in each
frame resulting in a frequency of the fundamental mode of 96 kHz. The corresponding
C/I command is SCP (Send Continuous Pulses).
Data Sheet
53
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.4
Clock Generation
Figure 28 shows the clock system of the ISAC-SX TE. The oscillator is used to generate
a 7.68 MHz clock signal (fXTAL). The DPLL generates the IOM-2 clocks FSC (8 kHz),
DCL (1536 kHz) and BCL (768 kHz) synchronous to the received S/T frames.
The FSC signal is used to generate the pulse lengths of the different reset sources C/I
Code, EAW pin and Watchdog (see Chapter 3.2.4). The IOM-2 clocks are summarized
in Table 9.
XTAL
FSC
f XTAL
7.68 MHz
OSC
DPLL
DCL
BCL
SW Reset
C/I
EAW
Watchdog
Pin RSTO
Reset
Generation
125 µs £ t £ 250 µs
125 µs £ t £ 250 µs
125 µs £ t £ 250 µs
125 µs £ t £ 250 µs
3186_06
Figure 28
Clock System of the ISAC-SX TE
Table 9
IOM-2 Clocks
Signal
Function
FSC
o:8 kHz (DIS_TR=0), normal mode
i:8 kHz (DIS_TR=1), S transceiver disabled *1)
DCL
o:1536 kHz (DIS_TR=0), normal mode
i:1536/768 kHz (DIS_TR=1), S transceiver disabled *1)
BCL
o:768 kHz
DU
i *2)
DD
o *2)
Data Sheet
54
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
Note: i = input; o = output;
1) The S transceiver can be disabled (TR_CONF0.DIS_TR=1) so the IOM clocks
become inputs and with IOM_CR.CLKM the DCL input can be selected to double
clock (0) or single bit clock (1).
2) The direction input/output refers to the direction of the B- and D-channel data
stream across the S-transceiver. Due to the capabilites of the IOM-2 handler the
direction of some other timeslots may be different if this is programmed by the host
(e.g. for data exchange between different devices connected to IOM-2).
3.4.1
Description of the Receive PLL (DPLL)
The receive PLL performs phase tracking between the F/L transition of the receive signal
and the recovered clock. Phase adjustment is done by adding or subtracting 0.5 or 1
XTAL period to or from a 1.536-MHz clock cycle. The 1.536-MHz clock is than used to
generate any other clock synchronized to the line.
During (re)synchronization an internal reset condition may effect the 1.536-MHz clock to
have high or low times as short as 130 ns. After the S/T interface frame has achieved
the synchronized state (after three consecutive valid pairs of code violations) the FSC
output is set to a specific phase relationship, thus causing once an irregular FSC timing.
The phase relationships of the clocks are shown in Figure 29.
7.68 MHz
F-bit
1536 kHz *
* Synchronous to receive S/T. Duty Ratio 1:1 Normally
768 kHz
ITD09664
FSC
Figure 29
3.4.2
Phase Relationships of ISAC-SX TE Clock Signals
Jitter
The timing extraction jitter of the ISAC-SX TE conforms to ITU-T Recommendation I.430
(– 7% to + 7% of the S-interface bit period).
Data Sheet
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ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.4.3
Oscillator Clock Output C768
The ISAC-SX TE derives its system clocks from an external clock connected to XTAL1
(while XTAL2 is not connected) or from a 7.68 MHz crystal connected across XTAL1 and
XTAL2.
At pin C768 a buffered 7.68 MHz output clock is provided to drive further devices, which
is suitable in multiline applications for example (see Figure 30). This clock is not
synchronized to the S-interface.
In power down mode the C768 output is disabled (low signal).
7.68
MHz
XTAL1
XTAL2
C768
XTAL1
n.c.
n.c.
XTAL2
C768
XTAL1
n.c.
n.c.
XTAL2
C768
3086_12
Figure 30
Data Sheet
Buffered Oscillator Clock Output
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ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.5
Control of Layer-1
The layer-1 activation / deactivation is controlled by an internal state machine via the
IOM-2 C/I0 channel. The ISAC-SX TE layer-1 control flow is shown in Figure 31.
Transmit
INFO
Command
CIX0
Transmitter
Layer-1
State
Machine
CI0 Data Register
Indication
CIR0
Receiver
IOM-2
C/I0 channel
Layer-1 Control
µC Interface
Figure 31
S/T Interface
INFO Signals
Receive
INFO
3186_01
Layer-1 Control
In the following sections the layer-1 control by the ISAC-SX TE state machine will be
described. For the description of the IOM-2 C/I0 channel see also Chapter 3.7.4.
The layer-1 functions are controlled by commands issued via the CIX0 register. These
commands, sent over the IOM-2 C/I channel 0 to layer 1, trigger certain procedures,
such as activation/deactivation, switching of test loops and transmission of special pulse
patterns. These procedures are governed by layer-1 state diagrams. Responses from
layer 1 are obtained by reading the CIR0 register after a CIC interrupt (ISTA).
The state diagrams of the ISAC-SX TE are shown in Figure 33 and Figure 34. The
activation/deactivation implemented by the ISAC-SX TE agrees with the requirements
set forth in ITU recommendations. State identifiers F1-F8 are in accordance with ITU
I.430.
State machines are the key to understanding the transceiver part of the ISAC-SX TE.
They include all information relevant to the user and enable him to understand and
predict the behaviour of the ISAC-SX TE. The state diagram notation is given in
Figure 32. The informations contained in the state diagrams are:
–
–
–
–
–
state name (based on ITU I.430)
S/T signal transmitted (INFO)
C/I code received
C/I code transmitted
transition criteria
The coding of the C/I commands and indications are described in detail in Chapter 3.5.2.
Data Sheet
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ISAC-SX TE
PSB 3186
Description of Functional Blocks
ISAC-SX
IPAC TE
IPAC
OUT
IN
IOM-2 Interface
C /Ι
Ind.
Cmd.
Unconditional
Transition
State
S / T Interface
INFO
ix
ir
ITD09657
Figure 32
State Diagram Notation
The following example illustrates the use of a state diagram with an extract of the TE
state diagram. The state explained is “F3 deactivated”.
The state may be entered:
– from the unconditional states (ARL, RES, TM)
– from state “F3 pending deactivation”, “F3 power up”, “F4 pending activation” or “F5
unsynchronized” after the C/I command “DI” has been received.
The following informations are transmitted:
– INFO 0 (no signal) is sent on the S/T-interface.
C/I message “DC” is issued on the IOM-2 interface.
The state may be left by either of the following methods:
– Leave for the state “F3 power up” in case C/I = “TIM” code is received.
– Leave for state “F4 pending activation” in case C/I = AR8 or AR10 is received.
– Leave for the state “F6 synchronized” after INFO 2 has been recognized on the S/
T-interface.
– Leave for the state “F7 activated” after INFO 4 has been recognized on the S/
T-interface.
– Leave for any unconditional state if any unconditional C/I command is received.
As can be seen from the transition criteria, combinations of multiple conditions are
possible as well. A “*” stands for a logical AND combination. And a “+” indicates a logical
OR combination.
The sections following the state diagram contain detailed information on all states and
signals used.
Data Sheet
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ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.5.1
State Machine TE Mode
3.5.1.1
State Transition Diagram (TE)
Figure 33 shows the state transition diagram of the ISAC-SX TE state machine.
Figure 34 shows this for the unconditional transitions (Reset, Loop, Test Mode i).
Data Sheet
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2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
DC
i4
DI
F3
Deactivated
i0
TIM
i0
AR i2
DI
PU AR2)
AR
F4
Pending Act.
i1
DI
TIM
i0
TIM
F3
Power Up
i0
i2
i0
i0
i4
X
RSY
i4
PU
TIM
F5
Unsynchronized DI
i0
X
DI
Uncond. State
TIM
ix
i2
AR
X
X4)
F6
Synchronized
i0*TO1
i2
i3
ix
i4
RSY
i2
i4
X
F8
Lost Framing
i2
i0
i0
DI
TIM
i0*TO1
i2
DI*TO2
ix
AI3) AR2)
F7
Activated
i3
TO1:
TO2:
i4
i0*TO1
i4
DR1)
X
F3
Pending Deact.
i0
TIM*TO2
i0
16 ms
0.5 ms
1)
DR for transition from F7 or F8
DR6 for transition from F6
AR stands for AR8 or AR10
3) AI stands for AI8 or AI10
4) X stands for commands initiating unconditional
transitions (RES, ARL, SSP or SCP)
2)
Figure 33
Data Sheet
statem_te_s.vsd
State Transition Diagram (TE)
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ISAC-SX TE
PSB 3186
Description of Functional Blocks
SSP
SCP
ARL
TIM
SSP
TMA SCP
TIM
ARL ARL
DI
Test Mode i
DI
iti
RST
*
Loop A Closed
i3
TIM
DI
RES RES
Reset
i0
*
*
i3
i3
RES
TIM
DI
AIL ARL
RSY
Any
State
Loop A Activated
i3
*
statem_te_aloop_s.vsd
Figure 34
3.5.1.2
State Transition Diagram of Unconditional Transitions (TE)
States (TE)
F3 Pending Deactivation
State after deactivation from the S/T interface by info 0. Note that no activation from the
terminal side is possible starting from this state. A ’DI’ command has to be issued to enter
the state ’Deactivated State’.
F3 Deactivated State
The S/T interface is deactivated and the clocks are deactivated 500 µs after entering this
state and receiving info 0 if the CFS bit of the ISAC-SX TE Configuration Register is set
to “0“. Activation is possible from the S/T interface and from the IOM-2 interface.
F3 Power Up
The S/T interface is deactivated (info 0 on the line) and the clocks are running.
F4 Pending Activation
The ISAC-SX transmits info 1 towards the network, waiting for info 2.
F5 Unsynchronized
Any signal except info 2 or 4 detected on the S/T interface.
F6 Synchronized
The receiver has synchronized and detects info 2. Info 3 is transmitted to synchronize
the NT.
Data Sheet
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ISAC-SX TE
PSB 3186
Description of Functional Blocks
F7 Activated
The receiver has synchronized and detects info 4. All user channels are now conveyed
transparently to the IOM-2 interface.
To transfer user channels transparently to the S/T interface either the command AR8 or
AR10 has to be issued and the signal from remote side must be synchronous.
F8 Lost Framing
The receiver has lost synchronization in the states F6 or F7 respectively.
Unconditional States
Loop A Closed (internal or external)
The ISAC-SX loops back the transmitter to the receiver and activates by transmission of
info 3. The receiver has not yet synchronized.
For a non transparent internal loop the DIS_TX bit of register TR_CONF2 has to be set
to ’1’.
Loop A Activated (internal or external)
The receiver has synchronized to info 3. Data may be sent. The indication “AIL” is output
to indicate the activated state. If the loop is closed internally and the S/T line awake
detector detects any signal on the S/T interface, this is indicated by “RSY”.
Test Mode - SSP
Single alternating pulses are transmitted to the S/T-interface resulting in a frequency of
the fundamental mode of 2 kHz.
Test Mode - SCP
Continuous alternating pulses are transmitted to the S/T-interface resulting in a
frequency of the fundamental mode of 96 kHz.
Data Sheet
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ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.5.1.3
C/I Codes (TE)
Command
Abbr. Code Remark
Activation Request with
priority class 8
AR8
Activation Request with
priority class 10
AR10 1001 Activation requested by the ISAC-SX,
D-channel priority set to 10 (see note)
1000 Activation requested by the ISAC-SX,
D-channel priority set to 8 (see note)
Activation Request Loop ARL
1010 Activation requested for the internal or
external Loop A (see note).
For a non transparent internal loop bit DIS_TX
of register TR_CONF2 has to be set to ’1’
additionally.
Deactivation Indication
DI
1111 Deactivation Indication
Reset
RES
0001 Reset of the layer-1 statemachine
Timing
TIM
0000 Layer-2 device requires clocks to be activated
Test mode SSP
SSP
0010 One AMI-coded pulse transmitted in each
frame, resulting in a frequency of the
fundamental mode of 2 kHz
Test mode SCP
SCP
0011 AMI-coded pulses transmitted continuously,
resulting in a frequency of the fundamental
mode of 96 kHz
Note: In the activated states (AI8, AI10 or AIL indication) the 2B+D channels are only
transferred transparently to the S/T interface if one of the three “Activation
Request” commands is permanently issued.
Data Sheet
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ISAC-SX TE
PSB 3186
Description of Functional Blocks
Indication
Abbr. Code Remark
Deactivation Request
DR
0000
Deactivation request via S/T-interface if left
from F7/F8
Reset
RES
0001
Reset acknowledge
Test Mode
Acknowledge
TMA
0010
Acknowledge for both SSP and SCP
Slip Detected
SLD
0011
Resynchronization
during level detect
RSY
0100
Signal received, receiver not synchronous
Deactivation Request
from F6
DR6
0101
Deactivation Request from state F6
Power up
PU
0111
IOM-2 interface clocking is provided
Activation request
AR
1000
Info 2 received
Activation request loop
ARL
1010
Internal or external loop A closed
Illegal Code Violation
CVR
1011
Illegal code violation received. This function
has to be enabled by setting the EN_ICV bit of
register TR_CONF0.
Activation indication
loop
AIL
1110
Internal or external loop A activated
Activation indication
with priority class 8
AI8
1100
Info 4 received,
D-channel priority is 8 or 9.
Activation indication
with priority class 10
AI10
1101
Info 4 received,
D-channel priority is 10 or 11.
Deactivation
confirmation
DC
1111
Clocks are disabled if CFS bit of register
MODE1 is set to ’1’, quiescent state
Data Sheet
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ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.5.1.4
Infos on S/T (TE)
Receive Infos on S/T (Downstream)
Name
Abbr. Description
info 0
i0
No signal on S/T
info 2
i2
4 kHz frame
A=’0’
info 4
i4
4 kHz frame
A=’1’
info X
ix
Any signal except info 2 or info 4
Transmit Infos on S/T (Upstream)
Name
Abbr. Description
info 0
i0
No signal on S/T
info 1
i1
Continuous bit sequence of the form ’00111111’
info 3
i3
4 kHz frame
Test info 1
it1
SSP - Send Single Pulses
Test info 2
it2
SCP - Send Continuous Pulses
Data Sheet
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ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.5.2
Command/ Indicate Channel Codes (C/I0) - Overview
The table below presents all defined C/I0 codes. A command needs to be applied
continuously until the desired action has been initiated. Indications are strictly state
orientated. Refer to the state diagrams in the previous sections for commands and
indications applicable in various states.
Code
TE Mode
Cmd
Ind
0
0
0
0
TIM
DR
0
0
0
1
RES
RES
0
0
1
0
SSP
TMA
0
0
1
1
SCP
SLD
0
1
0
0
–
RSY
0
1
0
1
–
DR6
0
1
1
0
–
–
0
1
1
1
–
PU
1
0
0
0
AR8
AR
1
0
0
1
AR10
–
1
0
1
0
ARL
ARL
1
0
1
1
–
CVR
1
1
0
0
–
AI8
1
1
0
1
–
AI10
1
1
1
0
–
AIL
1
1
1
1
DI
DC
Data Sheet
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ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.6
Control Procedures
3.6.1
Example of Activation/Deactivation
An example of an activation/deactivation of the S/T interface initiated by the terminal with
the time relationships mentioned in the previous chapters is shown in Figure 35.
NT/Linecard
TE
INFO 0
INFO 1
RSY
max. 6 ms
AR
INFO 2
INFO 3
AR
0.5 ms
INFO 4
AI
DR
16 ms
INFO 0
INFO 0
A_DEACT.DRW
Figure 35
Data Sheet
Example of Activation/Deactivation Initiated by the Terminal
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ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.7
IOM-2 Interface
The ISAC-SX TE supports the IOM-2 interface in terminal mode with single clock and
double clock. The IOM-2 interface consists of four lines: FSC, DCL, DD and DU. Another
clock signal BCL provides a single bit clock. The rising edge of FSC indicates the start
of an IOM-2 frame. The DCL and the BCL clock signals synchronize the data transfer on
both data lines DU and DD. The DCL is twice the bit rate, the BCL rate is equal to the bit
rate. The bits are shifted out with the rising edge of the first DCL clock cycle and sampled
at the falling edge of the second clock cycle.
The IOM-2 interface can be enabled/disabled with the DIS_IOM bit in the IOM_CR
register.
The IOM clock signals are generated by the receive DPLL which synchronizes the FSC
to the received S/T frame.
The BCL clock together with the serial data strobe signals SDS can be used to connect
timeslot oriented standard devices to the IOM-2 interface. If the transceiver is disabled
(TR_CON.DIS_TR) the DCL and FSC pins become input and the HDLC part can still
work via IOM-2. In this case the clock mode bit (IOM_CR.CLKM) selects between a
double clock and a single clock input for DCL.
The clock rate/frequency of the IOM-2 signals in TE mode are:
DD, DU: 768 kbit/s
FSC (o): 8 kHz
DCL (o): 1536 kHz (double clock rate)
BCL (o): 768 kHz (single clock rate)
Option - Transceiver disabled (DIS_TR = ’1’):
FSC (i): 8 kHz
DCL (i): 1536 ... 4096 kHz, in steps of 512 kHz (double clock rate)
Data Sheet
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ISAC-SX TE
PSB 3186
Description of Functional Blocks
IOM-2 Frame Structure (TE Mode)
The frame structure on the IOM-2 data ports (DU,DD) of a master device in IOM-2
terminal mode is shown in Figure 36.
Figure 36
IOMÒ-2 Frame Structure in Terminal Mode
The frame is composed of three channels
• Channel 0 contains 144-kbit/s of user and signaling data (2B + D), a MONITOR
programming channel (MON0) and a command/indication channel (CI0) for control
and programming of the layer-1 transceiver.
• Channel 1 contains two 64-kbit/s intercommunication channels (IC) plus a MONITOR
and command/indicate channel (MON1, CI1) to program or transfer data to other
IOM-2 devices.
• Channel 2 is used for the TlC-bus access. Only the command/indicate bits are
specified in this channel.
Data Sheet
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ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.7.1
IOM-2 Handler
The IOM-2 handler offers a great flexibility for handling the data transfer between the
different functional units of the ISAC-SX TE and voice/data devices connected to the
IOM-2 interface. Additionally it provides a microcontroller access to all timeslots of the
IOM-2 interface via the four controller data access registers (CDA). Figure 37 shows the
architecture of the IOM-2 handler. For illustrating the functional description it contains all
configuration and control registers of the IOM-2 handler. A detailed register description
can be found in Chapter 4.3.
The PCM data of the functional units
• Transceiver (TR) and the
• Controller data access (CDA)
can be configured by programming the timeslot and data port selection registers (TSDP).
With the TSS bits (Timeslot Selection) the PCM data of the functional units can be
assigned to each of the 12 PCM timeslots of the IOM-2 frame. With the DPS bit (Data
Port Selection) the output of each functional unit is assigned to DU or DD respectively.
The input is assigned vice versa. With the data control registers (xxx_CR) the access to
the data of the functional units can be controlled by setting the corresponding control bits
(EN, SWAP).
The IOM-2 handler also provides access to the
•
•
•
•
MONITOR channel (MON)
C/I channels (C/I0,C/I1)
TIC bus (TIC) and
HDLC control
The access to these channels is controlled by the registers MON_CR and DCI_CR.
The IOM-2 interface with the Serial Data Strobe SDS is controlled by the control registers
IOM_CR, SDS_CR.
The reset configuration of the ISAC-SX TE IOM-2 handler corresponds to the defined
frame structure and data ports of a master device in IOM-2 terminal mode (see
Figure 36).
Data Sheet
70
2003-01-30
71
CDA_TSDPxy
CDAx_CRx
MCDA
STI
MSTI
ASTI
( DPS, TSS,
EN_TBM, SWAP,
EN_I1/0, EN_O1/0,
MCDAxy, STIxy,
STOVxy, ACKxy )
CDA Control
CDA Data
BCL
FSC
DD
DU
MON Handler
TIC
IOM-2 Interface
Control
C/I0
Data
C/I1
SDS
D-ch
FIFOs
(CS2-0,
D_EN_D,
D_EN_B1,
D_EN_B2)
D-channel
HDLC
Data
D, B1, B2, C/I0 Data
TR_TSDP_BC1
TR_TSDP_BC2
TRC_CR
(DPS, TSS,
CS2-0, EN_D,
EN_B1R,
EN_B1X,
EN_B2R,
EN_B2X )
Control
Transceiver
Data Access
( ENS_TSS, ENS_TSS+1,
ENS_TSS+3, TSS, SDS_BCL
DCI_CR
(DPS_CI1,
EN_CI1)
(CS2-0)
DCIC_CR
C/I1
C/I0
C/I Data
Microcontroller Interface
IOM_CR
(TIC_DIS)
(DPS, CS2-0,
EN_MON)
MON_CR
TIC Bus
Disable
Monitor Data
EN_BCL, CLKM, DIS_OD, DIS_IOM,
DIOM_INV, DIOM_SDS
DCL
TIC Bus Data
Control
Monitor Data
Note: The registers shown above are used to control
the corresponding functional block (e.g. programming
of timeslot, data port, enabling/disabling, etc.)
CDA10
CDA11
CDA20
CDA21
CDA Registers
Controller Data Access (CDA)
IOM_CR
SDS_CR
C/I0 Data
Data Sheet
C/I1 Data
Figure 37
D Data
IOM-2 Handler
3186_07
D-channel RX/TX
B1-channel RX
B1-channel TX
B2-channel RX
B2-channel TX
Transceiver
Data TR
ISAC-SX TE
PSB 3186
Description of Functional Blocks
.
Architecture of the IOM Handler (Example Configuration)
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.7.1.1
Controller Data Access (CDA)
With its four controller data access registers (CDA10, CDA11, CDA20, CDA21) the
ISAC-SX TE IOM-2 handler provides a very flexible solution for the host access to up to
32 IOM-2 timeslots. However, in the normal mode (DCL output = 1.536 MHz) 12
timeslots are supported. Only if the transceiver is disabled (DIS_TR = ’1’) and external
clocks are provided, up to 32 timeslots (DCL input = 4.096 MHz) can be used.
The functional unit CDA (controller data access) allows with its control and configuration
registers
• looping of up to four independent PCM channels from DU to DD or vice versa over the
four CDA registers
• shifting of two independent PCM channels to another two independent PCM channels
on both data ports (DU, DD). Between reading and writing the data can be
manipulated (processed with an algorithm) by the microcontroller. If this is not the
case a switching function is performed
• monitoring of up to four timeslots on the IOM-2 interface simultaneously
• microcontroller read and write access to each PCM timeslot
The access principle which is identical for the two channel register pairs CDA10/11 and
CDA20/21 is illustrated in Figure 38. Each of the index variables x,y used in the following
description can be 1 or 2 for x and 0 or 1 for y. The prefix ’CDA_’ from the register names
has been omitted for simplification.
To each of the four CDAxy data registers a TSDPxy register is assigned by which the
timeslot and the data port can be determined. With the TSS (Timeslot Selection) bits a
timeslot from 0...31 can be selected. With the DPS (Data Port Selection) bit the output
of the CDAxy register can be assigned to DU or DD, respectively. The timeslot and data
port for the output of CDAxy is always defined by its own TSDPxy register. The input of
CDAxy depends on the SWAP bit in the control registers CRx.
• If the SWAP bit = ’0’ (swap is disabled) the timeslot and data port for the input and
output of the CDAxy register is defined by its own TSDPxy register.
• If the SWAP bit = ’1’ (swap is enabled) the input port and timeslot of the CDAx0 is
defined by the TSDP register of CDAx1 and the input port and timeslot of CDAx1 is
defined by the TSDP register of CDAx0. The input definition for timeslot and data port
CDAx0 are thus swapped to CDAx1 and for CDAx1 swapped to CDAx0. The output
timeslots are not affected by SWAP.
The input and output of every CDAxy register can be enabled or disabled by setting the
corresponding EN (-able) bit in the control register CDAx_CR. If the input of a register is
disabled the output value in the register is retained.
Usually one input and one output of a functional unit (transceiver, HDLC controller, CDA
register) is programmed to a timeslot on IOM-2 (e.g. for B-channel transmission in
upstream direction the HDLC controller writes data onto IOM and the transceiver reads
data from IOM). For monitoring data in such cases a CDA register is programmed as
Data Sheet
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ISAC-SX TE
PSB 3186
Description of Functional Blocks
described below under “Monitoring Data”. Besides that none of the IOM timeslots must
be assigned more than one input and output of any functional unit.
.
TSa
TSb
DU
Control
Register
1
CDAx0
0
1
1
1
1
1
CDAx1
1
0
1
CDA_TSDPx2
Enable
input *
output
(EN_I1)
(EN_O1)
Input
Swap
(SWAP)
input *
(EN_I0)
1
Time Slot
Selection (TSS)
0
Data Port
Selection (DPS)
Time Slot
Selection (TSS)
CDA_CRx
0
Enable
output
(EN_O0)
Data Port
Selection (DPS)
CDA_TSDPx1
1
DD
x = 1 or 2; a,b = 0...11
TSa
TSb
IOM_HAND.FM4
*) In the normal mode (SWAP=0) the input of CDAx0 and CDAx1 is enabled via EN_I0 and
EN_I1, respectively. If SWAP=1 EN_I0 controls the input of CDAx1 and EN_I1 controls the
input of CDAx0. The output control (EN_O0 and EN_O1) is not affected by SWAP.
Figure 38
Data Access via CDAx1 and CDAx2 Register Pairs
Looping and Shifting Data
Figure 39 gives examples for typical configurations with the above explained control and
configuration possibilities with the bits TSS, DPS, EN and SWAP in the registers
TSDPxy or CDAx_CR:
a) Looping IOM-2 timeslot data from DU to DD or vice versa (SWAP = 0)
b) Shifting data from TSa to TSb and TSc to TSd in both transmission directions
(SWAP = 1)
c)Sswitching data from TSa to TSb and looping from DU to DD or TSc to TSd and looping
from DD to DU respectively
TSa is programmed in TSDP10, TSb in TSDP11, TSc in TSDP20 and TSd in TSDP21.
It should also be noted that the input control of CDA registers is swapped if SWAP=1
while the output control is not affected (e.g. for CDA11 in example a: EN_I1=1 and
EN_O1=1, whereas for CDA11 in example b: EN_I0=1 and EN_O1=1).
Data Sheet
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ISAC-SX TE
PSB 3186
Description of Functional Blocks
a) Looping Data
TSa
TSb
TSc
TSd
CDA10
CDA11
CDA20
CDA21
TSc
’1’
TSd
’1’
DU
DD
.TSS: TSa
TSb
.DPS ’0’
’0’
.SWAP
’0’
’0’
b) Shifting Data
TSa
TSb
TSc
TSd
CDA10
CDA11
CDA20
CDA21
DU
DD
.TSS: TSa
TSb
.DPS ’0’
’1’
.SWAP
’1’
c) Switching Data
TSa
TSb
CDA10
CDA11
TSc
’0’
TSd
’1’
’1’
TSc
TSd
CDA20
CDA21
DU
DD
.TSS: TSa
TSb
.DPS ’0’
’0’
.SWAP
’1’
Figure 39
TSc
’1’
TSd
’1’
’1’
Examples for Data Access via CDAxy Registers
a) Looping Data
b) Shifting (Switching) Data
c) Shifting and Looping Data
Data Sheet
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PSB 3186
Description of Functional Blocks
Figure 40 shows the timing of looping TSa from DU to DD (a = 0...11) via CDAxy
register. TSa is read in the CDAxy register from DU and is written one frame later on DD.
.
a = 0...11
FSC
DU
TSa
TSa
µC *)
DD
TSa
STOV
ACK
WR
RD
STI
CDAxy
TSa
*) if access by the µC is required
Figure 40
Data Access when Looping TSa from DU to DD
Figure 41 shows the timing of shifting data from TSa to TSb on DU (DD). In Figure 41a)
shifting is done in one frame because TSa and TSb didn’t succeed direct one another (a,
b = 0...9 and b ³ a+2. In Figure 41b) shifting is done from one frame to the following
frame. This is the case when the timeslots succeed one other (b = a+1) or b is smaller
than a (b < a).
At looping and shifting the data can be accessed by the controller between the
synchronous transfer interrupt (STI) and the status overflow interrupt (STOV). STI and
STOV are explained in the section ’Synchronous Transfer’. If there is no controller
intervention the looping and shifting is done autonomous.
Data Sheet
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PSB 3186
Description of Functional Blocks
a) Shifting TSa ® TSb within one frame
(a,b: 0...11 and b ³ a+2)
FSC
DU
(DD)
TSa
TSa
TSb
µC *)
STI
STOV
ACK
WR
RD
STI
CDAxy
b) Shifting TSa ® TSb in the next frame
(a,b: 0...11 and (b = a+1 or b <a)
FSC
DU
(DD)
TSa TSb
TSa TSb
µC *)
STOV
WR
RD
STI
CDAxy
ACK
*) if access by the µC is required
Figure 41
Data Sheet
Data Access when Shifting TSa to TSb on DU (DD)
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Description of Functional Blocks
Monitoring Data
Figure 42 gives an example for monitoring of two IOM-2 timeslots each on DU or DD
simultaneously. For monitoring on DU and/or DD the channel registers with even
numbers (CDA10, CDA20) are assigned to timeslots with even numbers TS(2n) and the
channel registers with odd numbers (CDA11, CDA21) are assigned to timeslots with odd
numbers TS(2n+1). The user has to take care of this restriction by programming the
appropriate timeslots..
.
a) Monitoring Data
EN_O: ’0’
CDA_CR1. EN_I: ’1’
DPS: ’0’
TSS: TS(2n)
’0’
’1’
’0’
TS(2n+1)
DU
CDA10
CDA11
CDA20
CDA21
TSS: TS(2n)
’1’
DPS:
CDA_CR2.
EN_I: ’1’
EN_O: ’0’
Figure 42
TS(2n+1)
’1’
’1’
’0’
DD
Example for Monitoring Data
Monitoring TIC Bus
Monitoring the TIC bus (TS11) is handled as a special case. The TIC bus can be
monitored with the registers CDAx0 by setting the EN_TBM (Enable TIC Bus Monitoring)
bit in the control registers CRx. In this special case the TSDPx0 must be set to 08h for
monitoring from DU or 88h for monitoring from DD respectively. By this it is possible to
monitor the TIC bus (TS11) and the odd numbered D-channel (TS3) simultaneously on
DU and DD.
Data Sheet
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PSB 3186
Description of Functional Blocks
Synchronous Transfer
While looping, shifting and switching the data can be accessed by the controller between
the synchronous transfer interrupt (STI) and the status overflow interrupt (STOV).
The microcontroller access to the CDAxy registers can be synchronized by means of
four programmable synchronous transfer interrupts (STIxy)1) and synchronous transfer
overflow interrupts (STOVxy)2) in the STI register.
Depending on the DPS bit in the corresponding CDA_TSDPxy register the STIxy is
generated two (for DPS=’0’) or one (for DPS=’1’) BCL clock after the selected timeslot
(CDA_TSDPxy.TSS). One BCL clock is equivalent to two DCL clocks.
In the following description the index xy0 and xy1 are used to refer to two different
interrupt pairs (STI/STOV) out of the four CDA interrupt pairs (STI10/STOV10, STI11/
STOV11, STI20/STOV20, STI21/STOV21).
An STOVxy0 is related to its STIxy0 and is only generated if STIxy0 is enabled and not
acknowledged. However, if STIxy0 is masked, the STOVxy0 is generated for any other
STIxy1 which is enabled and not acknowledged.
Table 10 gives some examples for that. It is assumed that an STOV interrupt is only
generated because an STI interrupt was not acknowledged before.
In example 1 only the STIxy0 is enabled and thus STIxy0 is only generated. If no STI is
enabled, no interrupt will be generated even if STOV is enabled (example 2).
In example 3 STIxy0 is enabled and generated and the corresponding STOVxy0 is
disabled. STIxy1 is disabled but its STOVxy1 is enabled, and therefore STOVxy1 is
generated due to STIxy0. In example 4 additionally the corresponding STOVxy0 is
enabled, so STOVxy0 and STOVxy1 are both generated due to STIxy0.
In example 5 additionally the STIxy1 is enabled with the result that STOVxy0 is only
generated due to STIxy0 and STOVxy1 is only generated due to STIxy1.
Compared to the previous example STOVxy0 is disabled in example 6, so STOVxy0 is
not generated and STOVxy1 is only generated for STIxy1 but not for STIxy0.
Compared to example 5 in example 7 a third STOVxy2 is enabled and thus STOVxy2 is
generated additionally for both STIxy0 and STIxy1.
1)
In order to enable the STI interrupts the input of the corresponding CDA register has to be enabled. This is also
valid if only a synchronous write access is wanted. The enabling of the output alone does not effect an STI
interrupt.
2) In order to enable the STOV interrupts the output of the corresponding CDA register has to be enabled. This
is also valid if only a synchronous read access is wanted. The enabling of the input alone does not effect an
interrupt.
Data Sheet
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PSB 3186
Description of Functional Blocks
Table 10
Examples for Synchronous Transfer Interrupts
Enabled Interrupts
(Register MSTI)
Generated Interrupts
(Register STI)
STI
STOV
STI
STOV
xy0
-
xy0
-
Example 1
-
xy0
-
-
Example 2
xy0
xy1
xy0
xy1
Example 3
xy0
xy0 ; xy1
xy0
xy0 ; xy1
Example 4
xy0 ; xy1
xy0 ; xy1
xy0
xy1
xy0
xy1
Example 5
xy0 ; xy1
xy1
xy0
xy1
xy1
Example 6
xy0 ; xy1
xy0 ; xy1 ; xy2
xy0
xy1
xy0 ; xy2
xy1 ; xy2
Example 7
An STOV interrupt is not generated if all stimulating STI interrupts are acknowledged.
An STIxy must be acknowledged by setting the ACKxy bit in the ASTI register until two
BCL clocks (for DPS=’0’) or one BCL clocks (for DPS=’1’) before the timeslot which is
selected for the appropriate STIxy.
The interrupt structure of the synchronous transfer is shown in Figure 43.
.
MASK
ISTA
ST
CIC
ST
CIC
WOV
TRAN
MOS
ICD
WOV
TRAN
MOS
ICD
MSTI
STOV21
STOV20
STOV11
STOV10
STI21
STI20
STI11
STI10
STI
STOV21
STOV20
STOV11
STOV10
STI21
STI20
STI11
STI10
ASTI
ACK21
ACK20
ACK11
ACK10
Interrupt
Figure 43
Data Sheet
Interrupt Structure of the Synchronous Data Transfer
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Description of Functional Blocks
Figure 44 shows some examples based on the timeslot structure. Figure a) shows at
which point in time an STI and STOV interrrupt is generated for a specific timeslot. Figure
b) is identical to example 3 above, figure c) corresponds to example 5 and figure d)
shows example 4.
.
: STI interrupt generated
: STOV interrupt generated for a not acknowledged STI interrupt
a) Interrupts for data access to time slot 0 (B1 after reset), MSTI.STI10 and MSTI.STOV10 enabled
xy:
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
10
TS0
'0'
'0'
11
TS1
'1'
'1'
TS11 TS0 TS1
21
TS5
'1'
'1'
TS2 TS3
TS4 TS5 TS6
20
TS11
'1'
'1'
TS7 TS8
TS9 TS10 TS11 TS0
b) Interrupts for data access to time slot 0 (B1 after reset), STOV interrupt used as flag for "intermediate CDA
access"; MSTI.STI10 and MSTI.STOV21 enabled
xy:
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
10
TS0
'0'
'1'
11
TS1
'1'
'1'
TS11 TS0 TS1
21
TS5
'1'
'0'
TS2 TS3
TS4 TS5 TS6
20
TS11
'1'
'1'
TS7 TS8
TS9 TS10 TS11 TS0
c) Interrupts for data access to time slot 0 and 5, MSTI.STI10, MSTI.STOV10,
MSTI.STI21 and MSTI.STOV21 enabled
xy:
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
10
TS0
'0'
'0'
11
TS1
'1'
'1'
TS11 TS0 TS1
21
TS5
'0'
'0'
TS2 TS3
TS4 TS5 TS6
20
TS11
'1'
'1'
TS7 TS8
TS9 TS10 TS11 TS0
d) Interrupts for data access to time slot 0 (B1 after reset), STOV21 interrupt used as flag for "intermiediate CDA
access", STOV10 interrupt used as flag for "CDA access failed"; MSTI.STI10, MSTI.STOV10 and
MSTI.STOV21 enabled
xy:
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
10
TS0
'0'
'0'
11
TS1
'1'
'1'
TS11 TS0 TS1
21
TS5
'1'
'0'
TS2 TS3
TS4 TS5 TS6
20
TS11
'1'
'1'
TS7 TS8
TS9 TS10 TS11 TS0
sti_stov.vsd
Figure 44
Data Sheet
Examples for the Synchronous Transfer Interrupt Control with one
Enabled STIxy
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PSB 3186
Description of Functional Blocks
Restrictions Concerning Monitoring and Shifting Data
Due to the hardware design, there are some restrictions for the CDA shifting data
function and for the CDA monitoring data function. The selection of the CDA registers is
restricted if other functional blocks of the ISAC-SX TE (transceiver cores, HDLC
controllers, CI handler, Monitor handler, TIC bus etc.) access the corresponding timeslot.
If no functional block is assigned to a certain timeslot, any CDA register can be used for
monitoring or shifting it.
If a timeslot is already occupied by a functional block in a certain transmission direction,
only CDA registers with odd numbers (CDA11/21) can be assigned to odd timeslots and
CDA registers with even numbers (CDA10/20) can be assigned to even timeslots in the
same transmission direction. For the other transmission direction every CDA register can
be used. (Example: If TS 5 is already occupied in DD direction, only CDA11 and 21 can
be used for monitoring it. For monitoring TS 5 in DU direction, also CDA10 or CDA20
could be used.)
If above guideline is not considered, data can be overwritten in corresponding timeslots.
In this context no general rules can be derived in which way the data are overwritten.
The usage of the looping data and switching data functions are unrestricted.
Restrictions Concerning Read/Write Access
If data shall be read out from a certain transmission direction and other data shall be
written in the opposite transmission direction in the same timeslot, only special CDA
register combinations can be used. The correct behavior can be achieved with the
following CDA register combinations:
Table 11
CDA Register Combinations with Correct Read/Write Access
CDA Register Combination
1
2
3
4
Data of the downstream timeslot is read by CDA10
CDA11
CDA20
CDA21
Data is written to the upstream timeslot from CDA20
CDA21
CDA10
CDA11
With other register combinations unintended loops or erroneous monitorings can occur
or wrong data is written to the IOM interface.
Unexpected Write/Read Behavior of CDA Registers
If inputs and outputs are disabled, the programmed values of CDA10/11/20/21 registers
cannot be read back. Instead of the expected value the content of the previous
programming can be read out. The programmed value (5AH in the following example)
will be fetched if the output is enabled.
Data Sheet
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PSB 3186
Description of Functional Blocks
Example:
w CDA1_CR = 00H (inputs and outputs are disabled)
w CDA10 = 5AH (example)
r CDA10 = FFH (old value of previous programming)
w CDA1_CR = 02H (output of CDA10 is enabled)
r CDA10 = 5AH (the programmed value can be read back)
3.7.2
Serial Data Strobe Signal and Strobed Data Clock
For timeslot oriented standard devices connected to the IOM-2 interface the ISAC-SX
TE provides an independent data strobe signal SDS. Instead of a data strobe signal a
strobed IOM-2 bit clock can be provided on pin SDS.
3.7.2.1
Serial Data Strobe Signal
The strobe signal can be generated with every 8-kHz frame and is controlled by the
register SDS_CR. By programming the TSS bits and three enable bits (ENS_TSS,
ENS_TSS+1, ENS_TSS+3) a data strobe can be generated for the IOM-2 timeslots TS,
TS+1 and TS+3 and any combination of them.
The data strobe for TS and TS+1 are always 8 bits long (bit7 to bit0) whereas the data
strobe for TS+3 is always 2 bits long (bit7, bit6).
Figure 45 shows three examples for the generation of a strobe signal. In example 1 the
SDS is active during channel B2 on IOM-2 whereas in the second example during IC2
and MON1. The third example shows a strobe signal for 2B+D channels which can be
used e.g. for an IDSL (144kbit/s) transmission.
Data Sheet
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PSB 3186
Description of Functional Blocks
FSC
DD,DU
B1
B2
MON0
TS0
TS1
TS2
D CI0
MM
RX
TS3
IC1
IC2 MON1
TS4
TS5
TS6
CI1
MM
RX
TS7
TS8
TS9
TS10 TS11
TS0
TS1
SDS
(Example1)
SDS
(Example2)
SDS
(Example3)
Example 1:
TSS
ENS_TSS
ENS_TSS+1
ENS_TSS+3
= '0H'
= '0'
= '1'
= '0'
Example 2:
TSS
ENS_TSS
ENS_TSS+1
ENS_TSS+3
= '5H'
= '1'
= '1'
= '0'
Example 3:
TSS
ENS_TSS
ENS_TSS+1
ENS_TSS+3
= '0H'
= '1'
= '1'
= '1'
3186_02.vsd
For all examples SDS_CONF.SDS_BCL must be set to “0”.
Figure 45
Data Sheet
Data Strobe Signal
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PSB 3186
Description of Functional Blocks
3.7.2.2
Strobed IOM-2 Bit Clock
The strobed IOM-2 bit clock is active during the programmed window. Outside the
programmed window a ’0’ is driven. Two examples are shown in Figure 46.
FSC
DD,DU
B1
B2
TS0
TS1
MM
MON0 D CI0 R X IC1
TS2
TS3
TS4
IC2 MON1
TS5
TS6
CI1
MM
RX
TS7
TS8
TS9
TS10 TS11
TS0
TS1
SDS
(Example1)
SDS
(Example2)
Setting of SDS_CR:
Example 1:
TSS
ENS_TSS
ENS_TSS+1
ENS_TSS+3
= '0H'
= '0'
= '0'
= '1'
Example 2:
TSS
ENS_TSS
ENS_TSS+1
ENS_TSS+3
= '5H'
= '1'
= '1'
= '0'
3186_03.vsd
For all examples SDS_CONF.SDS_BCL must be set to “1”.
Figure 46
Strobed IOM-2 Bit Clock. Register SDS_CONF programmed to 01H
The strobed bit clock can be enabled in SDS_CONF.SDS_BCL.
3.7.3
IOM-2 Monitor Channel
The IOM-2 MONITOR channel (Figure 47) is utilized for information exchange in the
MONITOR channel between a master mode device and a slave mode device.
The MONTIOR channel data can be controlled by the bits in the MONITOR control
register (MON_CR). For the transmission of the MONITOR data one of the IOM-2
channels (3 IOM-2 channels in TE mode) can be selected by setting the MONITOR
channel selection bits (MCS) in the MONITOR control register (MON_CR).
Data Sheet
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PSB 3186
Description of Functional Blocks
The DPS bit in the same register selects between an output on DU or DD respectively
and with EN_MON the MONITOR data can be enabled/disabled. The default value is
MONITOR channel 0 (MON0) enabled and transmission on DD.
IOM-2 MONITOR Channel
V/D Module
(e.g. ARCOFI-BA)
IOM-2 MONITOR Channel
V/D Module
(e.g. ISAR34)
MONITOR Handler
MONITOR Handler
Layer 1
Layer 1
Master
Device
Slave
Device
µC
µC
IOM-2 MONITOR Channel
V/D Module
(e.g. ISAR34)
MONITOR Handler
Layer 1
µC
Data Exchange between
two µC Systems
Figure 47
µC
3086_08
Examples of MONITOR Channel Applications in IOM -2 TE Mode
The MONITOR channel of the ISAC-SX TE can be used in following applications which
are illustrated in Figure 47:
• As a master device the ISAC-SX TE can program and control other devices attached
to the IOM-2 which do not need a parallel microcontroller interface e.g. ARCOFI-BA
PSB 2161. This facilitates redesigning existing terminal designs in which e.g. an
interface of an expansion slot is realized with IOM-2 interface and monitor
programming.
• As a slave device the transceiver part of the ISAC-SX TE is programmed and
controlled from a master device on IOM-2 (e.g. ISAR34 PSB 7115). This is used in
applications where no microcontroller is connected directly to the ISAC-SX TE in order
to simplify host interface connection. The HDLC controlling is processed by the master
device therefore the HDLC data is transferred via IOM-2 interface directly to the
master device.
• For data exchange between two microcontroller systems attached to two different
devices on one IOM-2 backplane. Use of the MONITOR channel avoids the necessity
of a dedicated serial communication path between the two systems. This simplifies the
system design of terminal equipment.
Data Sheet
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PSB 3186
Description of Functional Blocks
3.7.3.1
Handshake Procedure
The MONITOR channel operates on an asynchronous basis. While data transfers on the
bus take place synchronized to frame sync, the flow of data is controlled by a handshake
procedure using the MONITOR Channel Receive (MR) and MONITOR Channel
Transmit (MX) bits. Data is placed onto the MONITOR channel and the MX bit is
activated. This data will be transmitted once per 8-kHz frame until the transfer is
acknowledged via the MR bit.
The MONITOR channel protocol is described in the following section and Figure 48
illustrates this. The relevant control and status bits for transmission and reception are
listed in Table 12 and Table 13.
Table 12
Transmit Direction
Control/
Status Bit
Register
Bit
Function
Control
MOCR
MXC
MX Bit Control
MIE
Transmit Interrupt Enable
MDA
Data Acknowledged
MAB
Data Abort
MAC
Transmission Active
Status
MOSR
MSTA
Table 13
Receive Direction
Control/
Status Bit
Register
Bit
Function
Control
MOCR
MRC
MR Bit Control
MRE
Receive Interrupt Enable
MDR
Data Received
MER
End of Reception
Status
Data Sheet
MOSR
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PSB 3186
Description of Functional Blocks
µP
Transmitter
MIE = 1
MOX = ADR
MXC = 1
MAC = 1
MDA Int.
MOX = DATA1
MDA Int.
MOX = DATA2
MDA Int.
MXC = 0
µP
Receiver
MON
MX
MR
FF
FF
ADR
1
1
0
1
1
1
ADR
DATA1
DATA1
0
1
0
0
0
0
DATA1
DATA1
0
0
1
0
DATA2
DATA2
1
0
0
0
DATA2
DATA2
0
0
1
0
FF
FF
1
1
0
0
FF
FF
1
1
1
1
125 µ s
MDR Int.
RD MOR (=ADR)
MRC = 1
MDR Int.
RD MOR (=DATA1)
MDR Int.
RD MOR (=DATA2)
MER Int.
MRC = 0
MAC = 0
ITD10032
Figure 48
MONITOR Channel Protocol (IOM-2)
Before starting a transmission, the microprocessor should verify that the transmitter is
inactive, i.e. that a possible previous transmission has been terminated. This is indicated
by a ’0’ in the MONITOR Channel Active MAC status bit.
After having written the MONITOR Data Transmit (MOX) register, the microprocessor
sets the MONITOR Transmit Control bit MXC to ’1’. This enables the MX bit to go active
(0), indicating the presence of valid MONITOR data (contents of MOX) in the
corresponding frame. As a result, the receiving device stores the MONITOR byte in its
MONITOR Receive MOR register and generates an MDR interrupt status.
Alerted by the MDR interrupt, the microprocessor reads the MONITOR Receive (MOR)
register. When it is ready to accept data (e.g. based on the value in MOR, which in a
point-to-multipoint application might be the address of the destination device), it sets the
MR control bit MRC to ’1’ to enable the receiver to store succeeding MONITOR channel
bytes and acknowledge them according to the MONITOR channel protocol. In addition,
it enables other MONITOR channel interrupts by setting MONITOR Interrupt Enable
(MIE) to ’1’.
Data Sheet
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PSB 3186
Description of Functional Blocks
As a result, the first MONITOR byte is acknowledged by the receiving device setting the
MR bit to ’0’. This causes a MONITOR Data Acknowledge MDA interrupt status at the
transmitter.
A new MONITOR data byte can now be written by the microprocessor in MOX. The MX
bit is still in the active (0) state. The transmitter indicates a new byte in the MONITOR
channel by returning the MX bit active after sending it once in the inactive state. As a
result, the receiver stores the MONITOR byte in MOR and generates a new MDR
interrupt status. When the microprocessor has read the MOR register, the receiver
acknowledges the data by returning the MR bit active after sending it once in the inactive
state. This in turn causes the transmitter to generate an MDA interrupt status.
This "MDA interrupt – write data – MDR interrupt – read data – MDA interrupt"
handshake is repeated as long as the transmitter has data to send. Note that the
MONITOR channel protocol imposes no maximum reaction times to the microprocessor.
When the last byte has been acknowledged by the receiver (MDA interrupt status), the
microprocessor sets the MONITOR Transmit Control bit MXC to ’0’. This enforces an
inactive (’1’) state in the MX bit. Two frames of MX inactive signifies the end of a
message. Thus, a MONITOR Channel End of Reception MER interrupt status is
generated by the receiver when the MX bit is received in the inactive state in two
consecutive frames. As a result, the microprocessor sets the MR control bit MRC to 0,
which in turn enforces an inactive state in the MR bit. This marks the end of the
transmission, making the MONITOR Channel Active MAC bit return to ’0’.
During a transmission process, it is possible for the receiver to ask a transmission to be
aborted by sending an inactive MR bit value in two consecutive frames. This is effected
by the microprocessor writing the MR control bit MRC to ’0’. An aborted transmission is
indicated by a MONITOR Channel Data Abort MAB interrupt status at the transmitter.
The MONITOR transfer protocol rules are summarized in the following section:
• A pair of MX and MR in the inactive state for two or more consecutive frames indicates
an idle state or an end of transmission.
• A start of a transmission is initiated by the transmitter by setting the MXC bit to ’1’
enabling the internal MX control. The receiver acknowledges the received first byte by
setting the MR control bit to ’1’ enabling the internal MR control.
• The internal MX,MR control indicates or acknowledges a new byte in the MON slot by
toggling MX,MR from the active to the inactive state for one frame.
• Two frames with the MX-bit in the inactive state indicate the end of transmission.
• Two frames with the MR-bit set to inactive indicate a receiver request for abort.
• The transmitter can delay a transmission sequence by sending the same byte
continuously. In that case the MX-bit remains active in the IOM-2 frame following the
first byte occurrence. Delaying a transmission sequence is only possible while the
receiver MR-bit and the transmitter MX-bit are active.
Data Sheet
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PSB 3186
Description of Functional Blocks
• Since a double last-look criterion is implemented the receiver is able to receive the
MON slot data at least twice (in two consecutive frames), the receiver waits for the
acknowledge of the reception of two identical bytes in two successive frames.
• To control this handshake procedure a collision detection mechanism is implemented
in the transmitter. This is done by making a collision check per bit on the transmitted
MONITOR data and the MX bit.
• Monitor data will be transmitted repeatedly until its reception is acknowledged or the
transmission time-out timer expires.
• Two frames with the MX bit in the inactive state indicates the end of a message
(EOM).
• Transmission and reception of monitor messages can be performed simultaneously.
This feature is used by the ISAC-SX TE to send back the response before the
transmission from the controller is completed (the ISAC-SX TE does not wait for EOM
from controller).
3.7.3.2
Error Treatment
In case the ISAC-SX TE does not detect identical monitor messages in two successive
frames, transmission is not aborted. Instead the ISAC-SX TE will wait until two identical
bytes are received in succession.
A transmission is aborted of the ISAC-SX TE if
• an error in the MR handshaking occurs
• a collision on the IOM-2 bus of the MONITOR data or MX bit occurs
• the transmission time-out timer expires
A reception is aborted by the device if
• an error in the MX handshaking occurs or
• an abort request from the opposite device occurs
MX/MR Treatment in Error Case
In the master mode the MX/MR bits are under control of the microcontroller through MXC
or MRC, respectively. An abort is indicated by an MAB interrupt or MER interrupt,
respectively.
In the slave mode the MX/MR bits are under control of the device. An abort is always
indicated by setting the MX/MR bit inactive for two or more IOM-2 frames. The controller
must react with EOM.
Figure 49 shows an example for an abort requested by the receiver, Figure 50 shows
an example for an abort requested by the transmitter and Figure 51 shows an example
for a successful transmission.
Data Sheet
89
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
IOM -2 Frame No.
1
2
3
4
5
6
7
1
MX (DU)
EOM
0
1
MR (DD)
0
Abort Request from Receiver
mon_rec-abort.vsd
Figure 49
Monitor Channel, Transmission Abort requested by the Receiver
IOM -2 Frame No.
1
3
2
4
5
6
7
1
MR (DU)
EOM
0
1
MX (DD)
0
Abort Request from Transmitter
mon_tx-abort.vsd
Figure 50
Monitor Channel, Transmission Abort requested by the Transmitter
IOM -2 Frame No.
MR (DU)
1
2
3
4
5
6
8
1
EOM
0
MX (DD)
7
1
0
mon_norm.vsd
Figure 51
Data Sheet
Monitor Channel, Normal End of Transmission
90
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.7.3.3
MONITOR Channel Programming as a Master Device
As a master device the ISAC-SX TE can program and control other devices attached to
the IOM-2 interface. The master mode is selected by default if one of the possible
microcontroller interfaces are selected. The monitor data is written by the
microprocessor in the MOX register and transmitted via IOM-2 DD (DU) line to the
programmed/controlled device e.g. ARCOFI-BA PSB 2161 or IEC-Q TE PSB 21911.
The transfer of the commands in the MON channel is regulated by the handshake
protocol mechanism with MX, MR which is described in the previous chapter
Chapter 3.7.3.1.
If the transmitted command was a read command the slave device responds by sending
the requested data.
The data structure of the transmitted monitor message depends on the device which is
programmed. Therefore the first byte of the message is a specific address code which
contains in the higher nibble a MONITOR channel address to identify different devices.
The length of the messages depends on the accessed device and the type of MONITOR
command.
3.7.3.4
MONITOR Channel Programming as a Slave Device
In applications without direct host controller connection the ISAC-SX TE must operate in
the MONITOR slave mode which can be selected by pinstrapping the microcontroller
interface pins according Table 3 respectively in Chapter 3.2. As a slave device the
transceiver part of the ISAC-SX TE is programmed and controlled by a master device at
the IOM-2 interface. All programming data required by the ISAC-SX TE is received in the
MONITOR timeslot on the IOM-2 and is transferred in the MOR register. The transfer of
the commands in the MON channel is regulated by the handshake protocol mechanism
with MX, MR which is described in the previous Chapter 3.7.3.1.
The first byte of the MONITOR message must contain in the higher nibble the MONITOR
channel address code which is ’1010’ for the ISAC-SX TE. The lower nibble
distinguishes between a programming command or an identification command.
Identification Command
In order to be able to identify unambiguously different hardware designs of the ISAC-SX
TE by software, the following identification command is used:
DD 1st byte value
1
0
1
0
0
0
0
0
DD 2nd byte value
0
0
0
0
0
0
0
0
The ISAC-SX TE responds to this DD identification sequence by sending a DU
identification sequence:
DESIGN:six bit code, specific for each device in order to identify differences in operation
Data Sheet
91
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
DU 1st byte value
1
0
DU 2nd byte value
0
1
e.g.
000001
1
0
0
0
0
0
DESIGN
<IDENT>
ISAC-SX TE PSB 3186 V 1.4
This identification sequence is usually done once, when the terminal is connected for the
first time. This function is used so that the software can distinguish between different
possible hardware configurations. However this sequence is not compulsory.
Programming Sequence
The programming sequence is characterized by a ’1’ being sent in the lower nibble of the
received address code. The data structure after this first byte and the principle of a read/
write access to a register is similar to the structure of the serial control interface
described in Chapter 3.2.1.1. For write access the header 43H/47H can be used and for
read access the header 40H/44H.
DD 1st byte value
1
0
1
DD 2nd byte value
DD 3rd byte value
0
0
0
0
1
Header Byte
R/W
Register Address
DD 4th byte value
Data 1
DD (nth + 3) byte value
Data n
All registers can be read back when setting the R/W bit in the byte for the command/
register address. The ISAC-SX TE responds by sending its IOM-2 specific address byte
(A1h) followed by the requested data.
Note: Application Hint:
It is not allowed to disable the MX- and MR-control in the programming device at
the same time! First, the MX-control must be disabled, then the mC has to wait for
an End of Reception before the MR-control may be disabled. Otherwise, the
ISAC-SX TE does not recognize an End of Reception.
3.7.3.5
Monitor Time-Out Procedure
To prevent lock-up situations in a MONITOR transmission a time-out procedure can be
enabled by setting the time-out bit (TOUT) in the MONITOR configuration register
(MCONF). An internal timer is always started when the transmitter must wait for the reply
of the addressed device. After 5 ms without reply the timer expires and the transmission
will be aborted with a EOM (End of Message) command by setting the MX bit to ’1’ for
two consecutive IOM-2 frames.
Data Sheet
92
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.7.3.6
MONITOR Interrupt Logic
Figure 52 shows the MONITOR interrupt structure of the ISAC-SX TE. The MONITOR
Data Receive interrupt status MDR has two enable bits, MONITOR Receive interrupt
Enable (MRE) and MR bit Control (MRC). The MONITOR channel End of Reception
MER, MONITOR channel Data Acknowledged MDA and MONITOR channel Data Abort
MAB interrupt status bits have a common enable bit MONITOR Interrupt Enable MIE.
MRE prevents the occurrence of MDR status, including when the first byte of a packet is
received. When MRE is active (1) but MRC is inactive, the MDR interrupt status is
generated only for the first byte of a receive packet. When both MRE and MRC are
active, MDR is always generated and all received MONITOR bytes - marked by a 1-to-0
transition in MX bit - are stored. (Additionally, an active MRC enables the control of the
MR handshake bit according to the MONITOR channel protocol.)
MASK
ISTA
ST
CIC
WOV
TRAN
MOS
ICD
ST
CIC
WOV
TRAN
MOS
ICD
MRE
MDR
MER
MIE
MDA
MAB
MOSR
MOCR
Interrupt
Figure 52
3.7.4
MONITOR Interrupt Structure
C/I Channel Handling
The Command/Indication channel carries real-time status information between the
ISAC-SX TE and another device connected to the IOM-2 interface.
1) One C/I channel (called C/I0) conveys the commands and indications between the
layer-1 and the layer-2 parts of the ISAC-SX TE. It can be accessed by an external
layer-2 device e.g. to control the layer-1 activation/deactivation procedures. C/I0 channel
access may be arbitrated via the TIC bus access protocol. In this case the arbitration is
done in IOM-2 channel 2 (see Figure 36).
The C/I0 channel is accessed via register CIR0 (in receive direction, layer-1 to layer-2)
and register CIX0 (in transmit direction, layer-2 to layer-1). The C/I0 code is four bits
long. A listing and explanation of the layer-1 C/I codes can be found in Chapter 3.5.2.
In the receive direction, the code from layer-1 is continuously monitored, with an interrupt
Data Sheet
93
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
being generated anytime a change occurs (ISTA.CIC). A new code must be found in two
consecutive IOM-2 frames to be considered valid and to trigger a C/I code change
interrupt status (double last look criterion).
In the transmit direction, the code written in CIX0 is continuously transmitted in C/I0.
2) A second C/I channel (called C/I1) can be used to convey real time status information
between the ISAC-SX TE and various non-layer-1 peripheral devices e.g. PSB 2161
ARCOFI-BA. The C/I1 channel consists of four or six bits in each direction.The width can
be changed from 4bit to 6bit by setting bit CIX1.CICW.
In 4-bit mode 6-bits are written whereby the higher 2 bits must be set to “1” and 6-bits
are read whereby only the 4 LSBs are used for comparison and interrupt generation (i.e.
the higher two bits are ignored).
The C/I1 channel is accessed via registers CIR1 and CIX1. A change in the received
C/I1 code is indicated by an interrupt status without double last look criterion.
CIC Interrupt Logic
Figure 53 shows the CIC interrupt structure.
A CIC interrupt may originate
– from a change in received C/I channel 0 code (CIC0)
or
– from a change in received C/I channel 1 code (CIC 1).
The two corresponding status bits CIC0 and CIC1 are read in CIR0 register. CIC1 can
be individually disabled by clearing the enable bit CI1E in the CIX1 register. In this case
the occurrence of a code change in CIR1 will not be displayed by CIC1 until the
corresponding enable bit has been set to one.
Bits CIC0 and CIC1 are cleared by a read of CIR0.
An interrupt status is indicated every time a valid new code is loaded in CIR0 or CIR1.
The CIR0 is buffered with a FIFO size of two. If a second code change occurs in the
received C/I channel 0 before the first one has been read, immediately after reading of
CIR0 a new interrupt will be generated and the new code will be stored in CIR0. If several
consecutive codes are detected, only the first and the last code is obtained at the first
and second register read, respectively.
For CIR1 no FIFO is available. The actual code of the received C/I channel 1 is always
stored in CIR1.
Data Sheet
94
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
MASK
ISTA
ST
CIC
ST
CIC
WOV
TRAN
MOS
ICD
WOV
TRAN
MOS
ICD
CI1E
CIX1
CIC0
CIC1
CIR0
Interrupt
Figure 53
3.7.5
CIC Interrupt Structure
D-Channel Access Control
D-channel access control is defined to guarantee all connected TEs and HDLC
controllers a fair chance to transmit data in the D-channel. Collisions are possible
• on the IOM-2 interface if there is more than one HDLC controller connected or
• on the S-interface when there is more than one terminal connected in a point to
multipoint configuration (NT ® TE1 … TE8).
Both arbitration mechanisms are implemented in the ISAC-SX TE and will be described
in the following two chapters.
3.7.5.1
TIC Bus D-Channel Access Control
The TIC bus is imlemented to organize the access to the layer-1 functions provided in
the ISAC-SX TE (C/I-channel) and to the D-channel from up to 7 external communication
controllers (Figure 54).
Note: If the TIC Bus feature is not used, it has to be switched off in order not to
disturb the layer-1 control and the HDLC controller. This is done by setting
bit DIM 1 in register Mode D and bit 4 in register IOM_CR. For more details
please refer to the application note “Reconfigurable PBX”.
To this effect the outputs of the D-channel controllers (e.g. ICC - ISDN Communication
Controller PEB 2070) are wired-or (negative logic, i.e. a “0” wins) and connected to pin
DU. The inputs of the ICCs are connected to pin DD. External pull-up resistors on DU/
DD are required. The arbitration mechanism must be activated by setting
MODED.DIM2-0=00x.
Data Sheet
95
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
ICC (7)
.
.
.
TIC-Bus
on IOM-2
ICC (2)
ICC (1)
S-Interface
D-channel
control
Stransceiver
U-Interface
NT
3086_09
Figure 54
Applications of TIC Bus in IOM-2 Bus Configuration
The arbitration mechanism is implemented in the last octet in IOM-2 channel 2 of the
IOM-2 interface (Figure 55). An access request to the TIC bus may either be generated
by software (µP access to the C/I channel) or by the ISAC-SX TE itself (transmission of
an HDLC frame in the D-channel). A software access request to the bus is effected by
setting the BAC bit (CIX0 register) to ’1’.
In the case of an access request, the ISAC-SX TE checks the Bus Accessed-bit BAC (bit
5 of last octet of CH2 on DU, Figure 55) for the status "bus free“, which is indicated by
a logical ’1’. If the bus is free, the ISAC-SX TE transmits its individual TIC bus address
TAD programmed in the CIX0 register (CIX0.TBA2-0). The ISAC-SX TE sends its TIC
bus address TAD and compares it bit by bit with the value on DU. If a sent bit set to ’1’
is read back as ’0’ because of the access of another D-channel source with a lower TAD,
the ISAC-SX TE withdraws immediately from the TIC bus, i.e. the remaining TAD bits
are not transmitted. The TIC bus is occupied by the device which sends its address errorfree. If more than one device attempt to seize the bus simultaneously, the one with the
lowest address values wins. This one will set BAC=0 on TIC bus and starts D-channel
transmission in the same frame.
Data Sheet
96
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
DU
Figure 55
Structure of Last Octet of Ch2 on DU
When the TIC bus is seized by the ISAC-SX TE, the bus is identified to other devices as
occupied via the DU Ch2 Bus Accessed-bit state ’0’ until the access request is
withdrawn. After a successful bus access, the ISAC-SX TE is automatically set into a
lower priority class, that is, a new bus access cannot be performed until the status "bus
free" is indicated in two successive frames.
If none of the devices connected to the IOM-2 interface request access to the D and C/
I channels, the TIC bus address 7 will be present. The device with this address will
therefore have access, by default, to the D and C/I channels.
Note: Bit BAC (CIX0 register) should be reset by the mP when access to the C/I channels
is no more requested, to grant other devices access to the D and C/I channels.
3.7.5.2
S-Bus Priority Mechanism for D-Channel
The S-bus access procedure specified in ITU I.430 was defined to organize D-channel
access with multiple TEs connected to a single S-bus (Figure 57).
To implement collision detection the D (channel) and E (echo) bits are used. The
D-channel S-bus condition is indicated towards the IOM-2 interface with the S/G bit, i.e.
the availability of the S/T interface D channel is indicated in bit 5 "Stop/Go" (S/G) of the
DD last octet of Ch2 channel (Figure 56).
S/G = 1 : stop
S/G = 0 : go
Data Sheet
97
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
MR
MX
DD
B1
B2
MON0 D CI0
IC1
MR
MX
IC2
MON1
S/G
A/B
CI1
ITD09693
E E S/G A/B
Stop/Go
Figure 56
Available/Blocked
Structure of Last Octet of Ch2 on DD
The Stop/Go bit is available to other layer-2 devices connected to the IOM-2 interface to
determine if they can access the S/T bus D channel.
The access to the D-channel is controlled by a priority mechanism which ensures that all
competing TEs are given a fair access chance. This priority mechanism discriminates
among the kind of information exchanged and information exchange history: Layer-2
frames are transmitted in such a way that signalling information is given priority (priority
class 1) over all other types of information exchange (priority class 2). Furthermore, once
a TE having successfully completed the transmission of a frame, it is assigned a lower
level of priority of that class. The TE is given back its normal level within a priority class
when all TEs have had an opportunity to transmit information at the normal level of that
priority class.
The priority mechanism is based on a rather simple method: A TE not transmitting
layer-2 frames sends binary 1s on the D-channel. As layer-2 frames are delimited by
flags consisting of the binary pattern “01111110” and zero bit insertion is used to prevent
flag imitation, the D-channel may be considered idle if more than seven consecutive 1s
are detected on the D-channel. Hence by monitoring the D echo channel, the TE may
determine if the D-channel is currently used by another TE or not.
A TE may start transmission of a layer-2 frame first when a certain number of
consecutive 1s has been received on the echo channel. This number is fixed to 8 in
priority class 1 and to 10 in priority class 2 for the normal level of priority; for the lower
level of priority the number is increased by 1 in each priority class, i.e. 9 for class 1 and
11 for class 2.
A TE, when in the active condition, is monitoring the D echo channel, counting the
number of consecutive binary 1s. If a 0 bit is detected, the TE restarts counting the
number of consecutive binary 1s. If the required number of 1s according to the actual
level of priority has been detected, the TE may start transmission of an HDLC frame. If
a collision occurs, the TE immediately shall cease transmission, return to the D-channel
monitoring state, and send 1s over the D-channel.
Data Sheet
98
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
S-Interface
D-channel
control
D-channel
control
TE 1
TE 2
U-Interface
D-Bits
Stransceiver
NT
E-Bits
Stransceiver
.
.
.
D-channel
control
TE 8
Stransceiver
3086_10
Figure 57
D-Channel Access Control on the S-Interface
S-Bus D-channel Access Control in the ISAC-SX TE
The above described priority mechanism is fully implemented in the ISAC-SX TE. For
this purpose the D-channel collission detection according to ITU I.430 must be enabled
by setting MODED.DIM2-0 to ’0x1’. In this case the transceiver continuously compares
the received E-echo bits with its own transmitted D data bits.
Depending on the priority class selected, 8 or 10 consecutive ONEs (high priority level,
priority 8) need to be detected before the transceiver sends valid D-channel data on the
upstream D-bits on S. In low priority level (priority 10) 10 or 11 consecutive ONEs are
required.
The priority class (priority 8 or priority 10) is selected by transferring the appropriate
activation command via the Command/Indication (C/I) channel of the IOM-2 interface to
the transceiver. If the activation is initiated by a TE, the priority class is selected implicitly
by the choice of the activation command. If the S-interface is activated from the NT, an
activation command selecting the desired priority class should be programmed at the TE
on reception of the activation indication (AI8 or AI10). In the activated state the priority
class may be changed whenever required by simply programming the desired activation
request command (AR8 or AR10).
Data Sheet
99
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.7.6
Activation/Deactivation of IOM-2 Interface
The IOM-2 interface can be switched off in the inactive state, reducing power
consumption to a minimum. In this deactivated state is FSC = ’1’, DCL and BCL = ’0’ and
the data lines are ’1’.
The IOM-2 interface can be kept active while the S interface is deactivated by setting the
CFS bit to "0" (MODE1 register). This is the case after a hardware reset. If the IOM-2
interface should be switched off while the S interface is deactivated, the CFS bit should
be set to ’1’. In this case the internal oscillator is disabled when no signal (info 0) is
present on the S bus and the C/I command is ’1111’ = DIU. If the TE wants to activate
the line, it has first to activate the IOM-2 interface either by using the "Software Power
Up" function (IOM_CR.SPU bit) or by setting the CFS bit to "0" again.
The deactivation procedure is shown in Figure 58. After detecting the code DIU
(Deactivate Indication Upstream) the layer 1 of the ISAC-SX TE responds by transmitting
DID (Deactivate Indication Downstream) during subsequent frames and stops the timing
signals synchronously with the end of the last C/I (C/I0) channel bit of the fourth frame.
IOMÒ -2
IOMÒ-2
Deactivated
FSC
DI
DI
DI
DI
DI
DI
DI
DI
DI
DR
DR
DR
DR
DR
DC
DC
DC
DC
DU
DD
B1
B2
D
D CIO
CIO
DCL
ITD09655_s.vsd
Figure 58
Deactivation of the IOM-2 Interface
The clock pulses will be enabled again when the DU line is pulled low (bit SPU in the
IOM_CR register), i.e. the C/I command TIM = "0000" is received by layer 1, or when a
non-zero level on the S-line interface is detected (if TR_CONF0.LDD=0). The clocks are
turned on after approximately 0.2 to 4 ms depending on the oscillator.
DCL is activated such that its first rising edge occurs with the beginning of the bit
following the C/I (C/I0) channel.
Data Sheet
100
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
After the clocks have been enabled this is indicated by the PU code in the C/I channel
and, consequently, by a CIC interrupt. The DU line may be released by resetting the
Software Power Up bit IOM_CR =’0’ and the C/I code written to CIX0 before (e.g. TIM or
AR8) is output on DU.
The ISAC-SX TE supplies IOM-2 timing signals as long as there is no DIU command in
the C/I (C/I0) channel. If timing signals are no longer required and activation is not yet
requested, this is indicated by programming DIU in the CIX0 register.
CIC : CIXO = TIM
Int. SPU = 0
~~
SPU = 1
FSC
TIM
TIM
TIM
PU
PU
PU
~~
DU
~~
PU
PU
~~
DD
~~
IOM -CH1
IOM -CH2
IOM -CH2
~~
R
~~
~~
~~ ~~
DU
~~ ~~
FSC
R
B1
DD
MR MX
R
IOM -CH1
~~
~~
0.2 to 4 ms
R
B1
~~
DCL
132 x DCL
Figure 59
Data Sheet
ITD09656
Activation of the IOM-2 interface
101
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.8
HDLC Controller
The ISAC-SX TE contains an HDLC controller for the layer-2 functions of the D- channel
protocol (LAPD). By setting the Enable HDLC channel bits (D_EN_x) in the DCI_CR
register the HDLC controller can access the D or B-channels on IOM-2.
It performs the framing functions used in HDLC based communication: flag generation/
recognition, bit stuffing, CRC check and address recognition.
The FIFO has a size of 64 byte per direction and is implemented as cyclic buffers. The
transceiver reads and writes data sequentially with constant data rate whereas the data
transfer between FIFO and microcontroller uses a block oriented protocol with variable
block sizes.
The configuration, control and status bits related to the HDLC controller are all assigned
to the following address ranges:
Table 14
HDLC Controller Address Range
D-channel HDLC
FIFO Address
Config/Ctrl/Status Registers
00H-1FH
20H-29H
Note: For D-channel access the address range 00H-1FH is used (similar as in ISAC-S
TE PSB 2186), however a single address from this range is sufficient to access
the FIFO as the internal FIFO pointer is incremented automatically independent
from the external address.
3.8.1
Message Transfer Modes
The HDLC controller can be programmed to operate in various modes, which are
different in the treatment of the HDLC frame in receive direction. Thus the receive data
flow and the address recognition features can be programmed in a flexible way to satisfy
different system requirements.
The structure of a D-channel two-byte address (LAPD) is shown below:
High Address Byte
SAPI1, 2, SAPG
Low Address Byte
C/R 0
TEI 1, 2, TEIG
EA
For address recognition on the D-channel the ISAC-SX TE contains four programmable
registers for individual SAPI and TEI values (SAP1, 2 and TEI1, 2), plus two fixed values
for the “group” SAPI (SAPG = ’FE’ or ’FC’) and TEI (TEIG = ’FF’).
The received C/R bit is excluded from the address comparison. EA is the address field
extension bit which must be set to ’1’ according to HDLC LAPD.
Data Sheet
102
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
Operating Modes
There are 5 different operating modes which can be selected via the mode selection bits
MDS2-0 in the MODED registers:
Non-Auto Mode (MDS2-0 = ’01x’)
Characteristics:
Full address recognition with one-byte (MDS = ’010’) or
two-byte (MDS = ’011’) address comparison
All frames with valid addresses are accepted and the bytes following the address are
transferred to the mP via RFIFOD. Additional information is available in RSTAD.
Transparent mode 0 (MDS2-0 = ’110’).
Characteristics:
no address recognition
Every received frame is stored in RFIFOD (first byte after opening flag to CRC field).
Additional information can be read from RSTAD.
Transparent mode 1 (MDS2-0 = ’111’).
Characteristics:
SAPI recognition
A comparison is performed on the first byte after the opening flag with SAP1, SAP2 and
“group” SAPI (FEH/FCH). In the case of a match, all the following bytes are stored in
RFIFOD. Additional information can be read from RSTAD.
Transparent mode 2 (MDS2-0 = ’101’).
Characteristics:
TEI recognition
A comparison is performed only on the second byte after the opening flag, with TEI1,
TEI2 and group TEI (FFH). In case of a match the rest of the frame is stored in the
RFIFOD. Additional information is available in RSTAD.
Extended transparent mode (MDS2-0 = ’100’).
Characteristics:
fully transparent
In extended transparent mode fully transparent data transmission/reception without
HDLC framing is performed i.e. without FLAG generation/recognition, CRC generation/
check, bitstuffing mechanism. This allows user specific protocol variations.
Also refer to Chapter 3.8.5.
Data Sheet
103
2003-01-30
ISAC-SX TE
PSB 3186
Description of Functional Blocks
3.8.2
Data Reception
3.8.2.1
Structure and Control of the Receive FIFO
The cyclic receive FIFO buffer with a length of 64 byte has a variable FIFO block size
(threshold) of 4, 8, 16 or 32 bytes which can be selected by setting the corresponding
RFBS bits in the EXMD register. The variable block size allows an optimized HDLC
processing concerning frame length, I/O throughput and interrupt load.
The transfer protocol between HDLC FIFO and microcontroller is block oriented with the
microcontroller as master. The control of the data transfer between the CPU and the
ISAC-SX TE is handled via interrupts (ISAC-SX TE ® Host) and commands (Host ®
ISAC-SX TE).
There are three different interrupt indications in the ISTAD registes concerned with the
reception of data:
– RPF (Receive Pool Full) interrupt, indicating that a data block of the selected length
(EXMD.RFBS) can be read from RFIFOD. The message which is currently received
exceeds the block size so further blocks will be received to complete the message.
– RME (Receive Message End) interrupt, indicating that the reception of one message
is completed, i.e. either
• a short message is received
(message length £ the defined block size (EXMD.RFBS)) or
• the last part of a long message is received
(message length > the defined block size (EXMD.RFBS))
and is stored in the RFIFOx.
– RFO (Receive Frame Overflow) interrupt, indicating that a complete frame could not
be stored in RFIFOD and is therefore lost as the RFIFOD is occupied. This occurs if
the host fails to respond quickly enough to RPF/RME interrupts since previous data
was not read by the host.
There are two control commands that are used with the reception of data:
– RMC (Receive Message Complete) command, telling the ISAC-SX TE that a data
block has been read from the RFIFOD and the corresponding FIFO space can be
released for new receive data.
– RRES (Receiver Reset) command, resetting the HDLC receiver and clearing the
receive FIFO of any data (e.g. used before start of reception). It has to be used after
a change of the message transfer mode. Pending interrupt indications of the receiver
are not cleared by RRES, but have to be cleared by reading these interrupts.
Note: The significant interrupts and commands are underlined as only these are
commonly used during a normal reception sequence.
The following description of the receive FIFO operation is illustrated in Figure 60 for a
RFIFOD block size (threshold) of 16 and 32 bytes.
Data Sheet
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PSB 3186
Description of Functional Blocks
The RFIFOD requests service from the microcontroller by setting a bit in the ISTAD
register, which causes an interrupt (RPF, RME, RFO). The microcontroller then reads
status information (RBCHD,RBCLD), data from the RFIFOD and then may change the
receive FIFO block size (EXMD.RFBS). A block transfer is completed by the
microcontroller via a receive message complete (CMDRD.RMC) command. This causes
the space of the transferred bytes being released for new data and in case the frame was
complete (RME) the reset of the receive byte counter RBC (RBCHD,RBCLD)1).
The total length of the frame is contained in the RBCHD and RBCLD registers which
contain a 12 bit number (RBC11...0), so frames up to 4095 byte length can be counted.
If a frame is longer than 4095 bytes, the RBCHD.OV (overflow) bit will be set. The least
significant bits of RBCLD contain the number of valid bytes in the last data block
indicated by RME (length of last data block £ selected block size). Table 15 shows which
RBC bits contain the number of bytes in the last data block or number of complete data
blocks respectively. If the number of bytes in the last data block is ’0’ the length of the
last received block is equal to the block size.
Table 15
Receive Byte Count with RBC11...0 in the RBCHD/RBCLD Registers
EXMD1.RFBS
Selected
block size
Number of
complete
data blocks in
bytes in the last
data block in
’00’
32 byte
RBC11...5
RBC4...0
’01’
16 byte
RBC11...4
RBC3...0
’10’
8 byte
RBC11...3
RBC2...0
’11’
4 byte
RBC11...2
RBC1...0
The transfer block size (EXMD.RFBS) is 32 bytes by default. If it is necessary to react to
an incoming frame within the first few bytes the microcontroller can set the RFIFOD block
size to a smaller value. Each time a CMDRD.RMC or CMDRD.RRES command is
issued, the RFIFOD access controller sets its block size to the value specified in
EXMD.RFBS, so the microcontroller has to write the new value for RFBS before the
RMC command. When setting an initial value for RFBS before the first HDLC activities,
a RRES command must be issued afterwards.
The RFIFOD can hold any number of frames fitting in the 64 bytes. At the end of a frame,
the RSTAD byte is always appended.
All generated interrupts are inserted together with all additional information into a wait
line to be individually passed to the host. For example if several data blocks have been
received to be read by the host and the host acknowledges the current block, a new RPF
or RME interrupt from the wait line is immediately generated to indicate new data.
1)
If RMC is omitted, then no new interrupt can be generated.
Data Sheet
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PSB 3186
Description of Functional Blocks
RAM
RAM
EXMD.RFBS=11
so after the first 4
bytes of a new frame
have been stored in the
fifo an receive pool full
interrupt ISTAD.RPF
is set.
32
RFACC
RFIFO ACCESS
CONTROLLER
16
RFBS=11
The µP has read
the 4 bytes, sets
RFBS=01 (16 bytes)
and completes the
block transfer by
an CMDRx.RMC command.
Following CMDRx.RMC
the 4 bytes of the
last block are
deleted.
32
RFACC
RFIFO ACCESS
CONTROLLER
16
RFBS=01
8
8
4
4
HDLC
Receiver
RPF
RFIFO
RBC=4h
HDLC
Receiver
EXMD.RFBS=01
RMC
µP
RAM
RAM
HDLC
Receiver
32
RSTA
RFACC
HDLC
Receiver
RFIFO ACCESS
RSTA
RSTA
16
CONTROLLER
RSTA
8
CONTROLLER
8
RME
RBC=16h
RMC
RFIFO
RPF
RBC=14h
RSTA
RSTA
µP
When the RFACC detects 16 valid bytes,
it sets an RPF interrupt. The µP reads the 16 bytes
and acknowledges the transfer by setting CMDRD.RMC.
This causes the space occupied by the 16 bytes being
released.
Data Sheet
16
RFBS=01
µP
Figure 60
RFIFO ACCESS
RFBS=01
RFIFO
The HDLC
receiver has
written further
data into the FIFO.
When a frame
is complete, a
status byte (RSTAD)
is appended.
Meanwhile two
more short frames
have been
received.
32
RFACC
After the RMC acknowledgement the
RFACC detects an RSTA byte, i.e. end of
the frame, therefore it asserts
an RME interupt and increments the
RBC counter by 2.
RFIFO Operation
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Description of Functional Blocks
Possible Error Conditions During Reception of Frames
If parts of a frame get lost because the receive FIFO is full, the Receive Data Overflow
(RDO) byte in the RSTAD byte will be set. If a complete frame is lost, i.e. if the FIFO is
full when a new frame is received, the receiver will assert a Receive Frame Overflow
(RFO) interrupt.
The microcontroller sees a cyclic buffer, i.e. if it tries to read more data than available, it
reads the same data again and again. On the other hand, if it doesn’t read or doesn’t
want to read all data, they are deleted anyway after the RMC command.
If the microcontroller reads data without a prior RME or RPF interrupt, the content of the
RFIFOD would not be corrupted, but new data is only transferred to the host as long as
new valid data is available in the RFIFOD, otherwise the last data is read again and
again.
The general procedures for a data reception sequence are outlined in the flow diagram
in Figure 61.
Data Sheet
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PSB 3186
Description of Functional Blocks
START
Receive
Message End
RME
?
Y
N
N
Receive
Pool Full
RPF
?
Y
Read Counter
RD_Count := RFBS
or
RD_Count := RBC
Read RBC
RD_Count := RBC
*
Read RD_Count
bytes from RFIFO
1)
Change Block Size
Write EXMR.RFBS
(optional)
x
Receive Message
Complete
Write RMC
1)
*
x
RBC = RBCH + RBCL register
RFBS: Refer to EXMR register
In case of RME the last byte in RFIFO contains
the receive status information RSTA
HDLC_Rflow.vsd
Figure 61
Data Reception Procedures
Figure 62 gives an example of an interrupt controlled reception sequence, supposed
that a long frame (68 byte) followed by two short frames (12 byte each) are received. The
FIFO threshold (block size) is set to 32 byte in this example:
• After 32 byte of frame 1 have been received an RPF interrupt is generated to indicate
that a data block can be read from the RFIFOD.
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Description of Functional Blocks
• The host reads the first data block from RFIFOD and acknowledges the reception by
RMC. Meanwhile the second data block is received and stored in RFIFOD.
• The second 32 byte block is indicated by RPF which is read and acknowledged by the
host as described before.
• The reception of the remaining 4 bytes plus RSTAD are indicated by RME (i.e. the
receive status is always appended to the end of the frame).
• The host gets the number of bytes (COUNT = 5) from RBCLD/RBCHD and reads out
the RFIFOD and optionally the status register RSTA. The frame is acknowledged by
RMC.
• The second frame is received and indicated by RME interrupt.
• The host gets the number of bytes (COUNT = 13) from RBCLD/RBCHD and reads out
the RFIFOD and optionally the status register. The RFIFOD is acknowledged by RMC.
• The third frame is transferred in the same way.
IOM Interface
Receive
Frame
68
Bytes
32
32
RD
32 Bytes
RPF
12
12
Bytes Bytes
4
12
12
RD
32 Bytes
RMC RPF
RD
RD
Count 5 Bytes
*
RMC RME
RD
RD
Count 13 Bytes
1)
RMC RME
*
RD
RD
Count 13 Bytes
1)
RMC RME
*
1)
RMC
CPU Interface
*
1)
The last byte contains the receive status information <RSTA>
fifoseq_rec.vsd
Figure 62
3.8.2.2
Reception Sequence Example
Receive Frame Structure
The management of the received HDLC frames as affected by the different operating
modes (see Chapter 3.8.1) is shown in Figure 63.
Data Sheet
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PSB 3186
Description of Functional Blocks
FLAG
MDS2 MDS1 MDS0
0
0
1
1
1
0
ADDR
ADDRESS
MODE
Non
Auto/16
Non
Auto/8
1
1
0
Transparent 0
1
1
1
Transparent 1
CTRL
SAP1
SAP2
SAPG
*2)
I
CONTROL DATA
CRC
FLAG
STATUS
*4)
RFIFOD
*1)
RSTAD
RFIFOD
*1)
RSTAD
RFIFOD
*1)
RSTAD
RFIFOD
*1)
RSTAD
RFIFOD
*1)
RSTAD *4)
TEI1
TEI2
TEIG
*2)
*4)
_
TEI1
TEI2
*2)
*3)
*4)
*4)
SAP1
SAP2
SAPG
*2)
1
0
1
Transparent 2
TEI1
TEI2
TEIG
*2)
Description of Symbols:
Compared with registers
Stored in FIFO/registers
*1) CRC optionally stored in RFIFOD if EXMD:RCRC=1
*2) Address optionally stored in RFIFOD if EXMD:SRA=1
*3) Start of the control field in case of an 8 bit address
*4) Content of RSTA register appended at the frameend into RFIFOD
3186_13
Figure 63
Receive Data Flow
The ISAC-SX TE indicates to the host that a new data block can be read from the
RFIFOD by means of an RPF interrupt (see previous chapter). User data is stored in the
RFIFOD and information about the received frame is available in the RBCLD and
RBCHD registers and the RSTAD byte which are listed in Table 16.
The RSTAD register is always appended in the RFIFOD as last byte to the end of a
frame.
Note: The number of bytes received in RFIFOD depends on the selected receive FIFO
threshold (EXMD.RFBS).
Data Sheet
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PSB 3186
Description of Functional Blocks
Table 16
Receive Information at RME Interrupt
Information
Register
Bit
Mode
Type of frame
(Command/
Response)
RSTAD
C/R
Non-auto mode,
2-byte address field
Transparent mode 1
Recognition of SAPI
RSTAD
SA1, 0
Non-auto mode,
2-byte address field
Transparent mode 1
Recognition of TEI
RSTAD
TA
All except
transparent mode 0
Result of CRC check
(correct/incorrect)
RSTAD
CRC
All
Valid Frame
RSTAD
VFR
All
Abort condition detected
(yes/no)
RSTAD
RAB
All
Data overflow during reception of RSTAD
a frame (yes/no)
RDO
All
Number of bytes received in
RFIFO
RBCL
RBC4-0
All
Message length
RBCLD
RBCHD
RBC11-0
All
RFIFO Overflow
RBCHD
OV
All
Data Sheet
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Description of Functional Blocks
3.8.3
Data Transmission
3.8.3.1
Structure and Control of the Transmit FIFO
The cyclic transmit FIFO buffer with a length of 64 byte has a variable FIFO block size
(threshold) of 16 or 32 bytes (programmable) which can be selected by setting the
corresponding XFBS bits in the EXMD register. There are three different interrupt
indications in the ISTAD register concerned with the transmission of data:
– XPR (Transmit Pool Ready) interrupt, indicating that a data block of up to 16 or 32 byte
can be written to the XFIFOD (fixed block size).
An XPR interrupt is generated either
• after an XRES (Transmitter Reset) command (which is issued for example for frame
abort) or
• when a data block from the XFIFOD is transmitted and the corresponding FIFO
space is released to accept further data from the host.
– XDU (Transmit Data Underrun) interrupt, indicating that the transmission of the
current frame has been aborted (seven consecutive ’1’s are transmitted) as the
XFIFOD holds no further transmit data. This occurs if the host fails to respond to an
XPR interrupt quickly enough.
– XMR (Transmit Message Repeat) interrupt, indicating that the transmission of the
complete last frame has to be repeated as a collision on the S bus has been detected
and the XFIFOx does not hold the first data bytes of the frame (collision after the 16th/
32nd byte or after the 32nd byte of the frame, respectively).
The occurence of an XDU or XMR interrupt clears the XFIFOD and an XMR interrupt
is issued together with an XDU or XMR interrupt, respectively. Data cannot be written
to the XFIFOD as long as an XDU/XMR interrupt is pending.
Three different control commands are used for transmission of data:
– XTF (Transmit Transparent Frame) command, telling the ISAC-SX TE that up to 16 or
32 byte have been written to the XFIFOD and should be transmitted. A start flag is
generated automatically.
– XME (Transmit Message End) command, telling the ISAC-SX TE that the last data
block written to the XFIFOD completes the corresponding frame and should be
transmitted. This implies that according to the selected mode a frame end (CRC +
closing flag) is generated and appended to the frame.
– XRES (Transmitter Reset) command, resetting the HDLC transmitter and clearing the
transmit FIFO of any data. After an XRES command the transmitter always sends an
abort sequence, i.e. this command can be used to abort a transmission. Pending
interrupt indications of the transmitter are not cleared by XRES, but have to be cleared
by reading these interutps.
Optionally two additional status conditions can be read by the host:
Data Sheet
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Description of Functional Blocks
– XDOV (Transmit Data Overflow), indicating that the data block size has been
exceeded, i.e. more than 16 or 32 byte were entered and data was overwritten.
– XFW (Transmit FIFO Write Enable), indicating that data can be written to the XFIFOD.
This status flag may be polled instead of or in addition to XPR.
Note: The significant interrupts and commands are underlined as only these are usually
used during a normal transmission sequence.
The XFIFOD requests service from the microcontroller by setting a bit in the ISTAD
register, which causes an interrupt (XPR, XDU, XMR). The microcontroller can then read
the status register STARD (XFW, XDOV), write data in the FIFO and it can change the
transmit FIFO block size (EXMD.XFBS) if required.
The instant of the initiation of a transmit pool ready (XPR) interrupt after different transmit
control commands is listed in Table 17.
Table 17
XPR Interrupt (availability of XFIFOD) after XTF, XME Commands
CMDRD Register
Transmit pool ready (XPR) interrupt initiated ...
XTF
as soon as the selected buffer size in the XFIFOD is available.
XTF & XME
after the successful transmission of the closing flag.
The transmitter always sends an abort sequence.
XME
as soon as the selected buffer size in the FIFO is available, two
consecutive frames share flags.
When setting XME the transmitter appends the CRC and the endflag at the end of the
frame. When XTF & XME has been set, the XFIFOD is locked until successful
transmission of the current frame, so a consecutive XPR interrupt also indicates
successful transmission of the frame whereas after XME or XTF the XPR interrupt is
asserted as soon as there is space for one data block in the XFIFOD.
The transfer block size is 32 bytes for D- and B-channel by default, but sometimes, if the
microcontroller has a high computational load, it is useful to increase the maximum
reaction time for an XPR interrupt. However, the threshold can only be changed for
D-channel. The maximum reaction time is:
tmax = (XFIFOD size - XFBS) / data transmission rate
With a selected block size of 16 bytes an XPR interrupt indicates when a transmit FIFO
space of at least 16 bytes is available to accept further data, i.e. there are still a maximum
of 48 bytes (64 bytes - 16 bytes) to be transmitted. With a 32 bytes block size the XPR
is initiated when a transmit FIFO space of at least 32 bytes is available to accept further
data, i.e. there are still a maximum of 32 bytes (64 bytes - 32 bytes) to be transmitted.
The maximum reaction time for the smaller block size is 50 % higher with the trade-off
of a doubled interrupt load. With a selected block size an XPR always indicates the
Data Sheet
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Description of Functional Blocks
available space in the XFIFOD, so any number of bytes smaller than the selected XFBS
may be stored in the FIFO during one “write block“ access cycle.
Similar to RFBS for the receive FIFO, a new setting of XFBS takes effect after the next
XTF, XME or XRES command. XRES resets the XFIFOD.
The XFIFOD can hold any number of frames fitting in the 64 bytes.
Possible Error Conditions during Transmission of Frames
If the transmitter sees an empty FIFO, i.e. if the microcontroller doesn’t react fast enough
to an XPR interrupt, an XDU (transmit data underrun) interrupt will be generated. If the
HDLC channel becomes unavailable during transmission the transmitter tries to repeat
the current frame as specified in the LAPD protocol. This is impossible after the first data
block has been sent (16 or 32 bytes), in this case an XMR transmit message repeat
interrupt is set and the microcontroller has to send the whole frame again.
Both XMR and XDU interrupts cause a reset of the XFIFOD. The XFIFOD is locked while
an XMR or XDU interrupt is pending, i.d. all write actions of the microcontroller will be
ignored as long as the microcontroller hasn’t read the ISTAD register with the set XDU,
XMR interrupts.
If the microcontroller writes more data than allowed (block size), then the data in the
XFIFOD will be corrupted and the STARD.XDOV bit is set. If this happens, the
microcontroller has to abort the transmission by CMDRD.XRES and start new.
The general procedures for a data transmission sequence are outlined in the flow
diagram in Figure 64.
Data Sheet
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PSB 3186
Description of Functional Blocks
START
N
Transmit
Pool Ready
XPR
?
Y
Write one
data block
to XFIFO
Command
XTF
N
End of
Message
?
Y
Command
XTF+XME
End
21150_25
Figure 64
Data Transmission Procedure
The following description gives an example for the transmission of a 76 byte frame with
a selected block size of 32 byte:
• The host writes 32 bytes to the XFIFOD, issues an XTF command and waits for an
XPR interrupt in order to continue with entering data.
• The ISAC-SX TE immediately issues an XPR interrupt (as remaining XFIFOD space
is not used) and starts transmission.
• Due to the XPR interrupt the host writes the next 32 bytes to the XFIFOD, followed by
the XTF command, and waits for XPR.
• As soon as the last byte of the first block is transmitted, the ISAC-SX TE releases an
XPR (XFIFOD space of first data block is free again) and continues transmitting the
second block.
• The host writes the remaining 12 bytes of the frame to the XFIFOD and issues the XTF
command together with XME to indicate that this is the end of frame.
• After the last byte of the frame has been transmitted the ISAC-SX TE releases an XPR
interrupt and the host may proceed with transmission of a new frame.
Data Sheet
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PSB 3186
Description of Functional Blocks
IOM Interface
76 Bytes
Transmit
Frame
32
WR
32 Bytes
32
WR
12 Bytes
WR
32 Bytes
XTF XPR
12
XTF
XPR
XTF+XME
XPR
CPU Interface
fifoseq_tran.vsd
Figure 65
Transmission Sequence Example
3.8.3.2
Transmit Frame Structure
The transmission of transparent frames (XTF command) is shown in Figure 66.
For transparent frames, the whole frame including address and control field must be
written to the XFIFOD. The host configures whether the CRC is generated and
appended to the frame (default) or not (selected in EXMD.XCRC).
Further, the host selects the interframe time fill signal which is transmitted between
HDCL frames (EXMD.ITF). One option is to send continuous flags (’01111110’),
however if D-channel access handling (collision resolution on the S bus) is required, the
signal must be set to idle (continuous ’1’s are transmitted). Reprogramming of ITF takes
effect only after the transmission of the current frame has been completed or after an
XRES command.
FLAG
ADDR
CTRL
ADDRESS
CONTROL
Transmit Transparent Frame
(XTF)
*
Figure 66
Data Sheet
1)
XFIFO
The CRC is generated by default.
If EXMR.XCRC is set no CRC is appended
I
DATA
CRC
FLAG
CHECKRAM
*
1)
fifoflow_tran.vsd
Transmit Data Flow
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Description of Functional Blocks
3.8.4
Access to IOM-2 Channels
By setting the enable HDLC data bits (D_EN_D, D_EN_B1, D_EN_B2) in the DCI_CR
register the HDLC controller can access the D, B1 and B2 channels or any combination
of them. In all modes (except extended transparent mode) transmission always works
frame aligned, i.e. it starts with the first selected channel, whereas reception searches
for a flag anywhere in the serial data stream.
3.8.5
Extended Transparent Mode
This non-HDLC mode is selected by setting MODE2...0 to ’100’. In extended transparent
mode fully transparent data transmission/reception without HDLC framing is performed
i.e. without FLAG generation/recognition, CRC generation/check, bitstuffing mechanism.
This allows user specific protocol variations.
Transmitter
The transmitter sends the data out of the FIFO without manipulation. Transmission is
always IOM-2 frame aligned and byte aligned, i.e. transmission starts in the first selected
channel (B1, B2, D, according to the setting of register DCI_CR in the IOM-2 Handler) of
the next IOM-2 frame.
The FIFO indications and commands are the same as in other modes.
If the microcontroller sets XTF & XME the transmitter responds with an XPR interrupt
after sending the last byte, then it returns to its idle state (sending continuous ‘1’).
If the collision detection is enabled in D-channel (MODE.DIM = ’0x1’) the stop go bit (S/
G) can be used as clear to send indication as in any other mode. If the S/G bit is set to
’1’ (stop) during transmission the transmitter responds always with an XMR (transmit
message repeat) interrupt.
If the microcontroller fails to respond to a XPR interrupt in time and the transmitter runs
out of data then it will assert an XDU (transmit data underrun) interrupt.
Receiver
The reception is IOM-2 frame aligned and byte aligned, like transmission, i.e. reception
starts in the first selected channel (B1, B2, D, according to the setting of registers
DCI_CR in the IOM-2 Handler) of the next IOM-2 frame. The FIFO indications and
commands are the same as in others modes.
All incoming data bytes are stored in the RFIFOD and is additionally made available in
RSTAD. If the FIFO is full an RFO interrupt is asserted (EXMD.SRA = ’0’).
Note: In the extended transparent mode the EXMD register has to be set to ’xxx00000’
Data Sheet
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PSB 3186
Description of Functional Blocks
3.8.6
HDLC Controller Interrupts
The cause of an interrupt related to the HDLC controller is indicated in the ISTA register
by the ICD bit. This bit points to the interrupt source of the D-channel HDLC controller in
the ISTAD register. The individual interrupt sources of the HDLC controllers during
reception and transmission of data are explained in Chapter 3.8.2.1 or Chapter 3.8.3.1
respectively.
MASK
ISTA
D-channel
ST
ST
MASKD
RME
ISTAD
RME
CIC
CIC
RPF
RPF
AUX
AUX
RFO
RFO
TRAN
TRAN
XPR
XPR
MOS
MOS
XMR
XMR
ICD
ICD
XDU
XDU
3186_16.vsd
Interrupt
Figure 67
Interrupt Status Registers of the HDLC Controllers
Each interrupt source in the ISTAD register can selectively be masked by setting the
corresponding bit in MASKD to “1”.
Data Sheet
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Description of Functional Blocks
3.9
Test Functions
The ISAC-SX TE provides test and diagnostic functions for the S-interface and the Dchannel:
• Digital loop via TLP (Test Loop, TMD register) command bit (Figure 68): The TX path
of layer 2 is internally connected with the RX path of layer 2. The output from layer 1
(S/T) on DD is ignored. This is used for testing ISAC-SX TE functionality excluding
layer 1 (loopback between XFIFOD and RFIFOD).
TMD.TLP = ’0’
Figure 68
Data Sheet
TMD.TLP = ’1’
Layer 2 Test Loops
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Description of Functional Blocks
• Test of layer-2 functions while disabling all layer-1 functions and pins associated with
them (including clocking) via bit TR_CONF0.DIS_TR. The HDLC controllers can still
operate via IOM-2. DCL and FSC pins become input.
• loop at the analog end of the S interface;
Test loop 3 is activated with the C/I channel command Activate Request Loop
(ARL). An S interface is not required since INFO3 is looped back internally to the
receiver. When the receiver has synchronized itself to this signal, the message "Test
Indication" (or "Awake Test Indication") is delivered in the C/I channel. No signal is
transmitted over the S interface.
In the test loop mode the S interface awake detector is enabled, i.e. if a level is
detected (e.g. Info 2/Info 4) this will be reported by the Resynchronization Indication
(RSY). The loop function is not effected by this condition and the internally
generated 192-kHz line clock does not depend on the signal received at the S
interface.
• transmission of special test signals on the S/T interface according to the modified AMI
code are initiated via a C/I command written in CIX0 register.
Two kinds of test signals may be sent by the ISAC-SX TE:
– single pulses and
– continuous pulses.
The single pulses are of alternating polarity, one S interface bit period wide, 0.25 ms
apart, with a repetition frequency of 2 kHz. Single pulses can be sent in all
applications. The corresponding C/I command in TE applications is TM1.
Continuous pulses are likewise of alternating polarity, one S-interface bit period
wide, but they are sent continuously. The repetition frequency is 96 kHz. Continuous
pulses may be transmitted in all applications. This test mode is entered in TE
applications with the C/I command TM2.
Data Sheet
120
2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
4
Detailed Register Description
The register mapping of the ISAC-SX TE is shown in Figure 69.
FFh
(Not used)
70h
Interrupt, General Configuration
60h
IOM-2 and MONITOR Handler
40h
Transceiver
30h
D- and C/I-channel
00h
3186_04
Figure 69
Register Mapping of the ISAC-SX TE
The register address range from 00H-2FH is assigned to the D-channel HDLC controller
and the C/I-channel handler.
The register set ranging from 30H-3FH pertains to the transceiver registers.
The address range from 40H-5BH is assigned to the IOM handler with the registers for
timeslot and data port selection (TSDP) and the control registers (CR) for the transceiver
data (TR), Monitor data (MON), HDLC/CI data (HCI) and controller access data (CDA),
serial data strobe signal (SDS), IOM interface (IOM) and synchronous transfer interrupt
(STI).
The address range from 5CH-5FH pertains to the MONITOR handler.
General interrupt and configuration registers are contained in the address range
60H-65H.
Data Sheet
121
2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
The register summaries of the ISAC-SX TE are shown in the following tables containing
the abbreviation of the register name and the register bits, the register address, the reset
values and the register type (Read/Write). A detailed register description follows these
register summaries.
The register summaries and the description are sorted in ascending order of the register
address.
D-channel HDLC, C/I-channel Handler
Name
7
6
5
4
3
2
1
0
ADDR R/WRES
RFIFOD
D-Channel Receive FIFO
00H1FH
R
XFIFOD
D-Channel Transmit FIFO
00H1FH
W
ISTAD
RME
RPF
RFO
XPR
XMR
XDU
0
0
20H
R 10H
MASKD
RME
RPF
RFO
XPR
XMR
XDU
1
1
20H
W FFH
0
21H
R 40H
STARD
XDOV XFW
0
0
RACI
0
XACI
CMDRD
RMC RRES
0
STI
XTF
0
XME XRES
21H
W 00H
0
RAC
DIM2 DIM1 DIM0
22H
R/W C0H
23H
R/W 00H
24H
R/W 00H
MODED MDS2 MDS1 MDS0
EXMD1
XFBS
TIMR1
RFBS
SRA XCRC RCRC
CNT
0
ITF
VALUE
SAP1
SAPI1
0
MHA
25H
W FCH
SAP2
SAPI2
0
MLA
26H
W FCH
RBC0
26H
R 00H
RBC8
27H
R 00H
RBCLD
RBC7
RBCHD
0
0
0
OV RBC11
TEI1
TEI1
EA1
27H
W FFH
TEI2
TEI2
EA2
28H
W FFH
RSTAD
TMD
Data Sheet
VFR
RDO
CRC
RAB
SA1
SA0
C/R
TA
28H
R 0FH
0
0
0
0
0
0
0
TLP
29H
R/W 00H
122
2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
reserved
2A-2DH
CIR0
CODR0
CIC0
CIC1
S/G
CIX0
CODX0
TBA2 TBA1 TBA0
BAS
2EH
R F3H
BAC
2EH W
FEH
CIR1
CODR1
CICW CI1E
2FH
R
FEH
CIX1
CODX1
CICW CI1E
2FH
W
FEH
Transceiver
NAME
7
6
TR_
CONF0
DIS_
TR
TR_
CONF1
0
TR_
CONF2
DIS_
TX
TR_STA
5
0
4
EN_
ICV
RINF
2
1
0
ADDR R/WRES
0
0
0
EXLP
LDD
30H
R/W 01H
0
0
x
x
x
31H
R/W
0
RLP
0
0
0
0
32H
R/W 80H
SLIP
ICV
0
FSYN
0
LD
33H
R 00H
RPLL_ EN_
ADJ SFSC
PDS
3
reserved
34H
0
0
SQR11SQR12SQR13SQR14
35H
R 40H
0
0
SQX11 SQX12SQX13 SQX14
35H
W 4FH
SQRR2 SQR21SQR22SQR23SQR24SQR31SQR32SQR33SQR34
36H
R 00H
36H
W
37H
R 00H
37H
W
SQRR1
MSYN MFEN
SQXR1
0
MFEN
reserved
SQRR3 SQR41SQR42SQR43SQR44SQR51SQR52SQR53SQR54
reserved
ISTATR
0
x
x
x
LD
RIC
SQC
SQW
38H
R 00H
MASKTR
1
1
1
1
LD
RIC
SQC
SQW
39H
R/W FFH
reserved
Data Sheet
123
3AH3BH
2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
Transceiver
NAME
7
ACFG2
6
0
5
0
4
0
3
0
2
ACL
1
LED
0
0
ADDR R/WRES
0
reserved
3CH R/W 00H
3DH3FH
IOM Handler (Timeslot , Data Port Selection,
CDA Data and CDA Control Register)
Name
7
6
5
4
3
2
1
0
ADDR R/WRES
CDA10
Controller Data Access Register (CH10)
40H
R/W FFH
CDA11
Controller Data Access Register (CH11)
41H
R/W FFH
CDA20
Controller Data Access Register (CH20)
42H
R/W FFH
CDA21
Controller Data Access Register (CH21)
43H
R/W FFH
CDA_ DPS
TSDP10
0
0
TSS
44H
R/W 00H
CDA_ DPS
TSDP11
0
0
TSS
45H
R/W 01H
CDA_ DPS
TSDP20
0
0
TSS
46H
R/W 80H
CDA_ DPS
TSDP21
0
0
TSS
47H
R/W 81H
reserved
48H4BH
TR_
TSDP_
BC1
DPS
0
0
TSS
4CH R/W
TR_
TSDP_
BC2
DPS
0
0
TSS
4DH R/W
Data Sheet
124
2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
CDA1_
CR
0
0
EN_ EN_I1 EN_I0 EN_O1EN_O0 SWAP
TBM
4EH R/W 00H
CDA2_
CR
0
0
EN_ EN_I1 EN_I0 EN_O1EN_O0 SWAP
TBM
4FH R/W 00H
IOM Handler (Control Registers, Synchronous Transfer
Interrupt Control), MONITOR Handler
Name
TR_CR
7
6
5
4
3
2
1
0
ADDR R/WRES
EN_
B2R
EN_
B1R
EN_
B2X
EN_
B1X
CS2-0
50H R/W
(CI_CS=0)
EN_
D
TRC_CR
0
0
0
0
0
CS2-0
50H R/W
(CI_CS=1)
reserved
51H
reserved
52H
DCI_CR
DPS_ EN_
D_
D_
D_
CI1 EN_D EN_B2 EN_B1
(CI_CS=0) CI1
DCIC_CR
0
CS2-0
53H R/W
0
0
0
0
CS2-0
53H R/W
EN_
MON
0
0
0
CS2-0
54H R/W
(CI_CS=1)
MON_CR DPS
SDS_CR ENS_ ENS_ ENS_
TSS TSS+1 TSS+3
55H R/W 00H
TSS
reserved
IOM_CR
STI
ASTI
Data Sheet
SPU
0
CI_CS TIC_
DIS
STOV STOV STOV STOV
21
20
11
10
0
0
0
0
56H
EN_ CLKM DIS_
BCL
OD
DIS_
IOM
57H R/W 08H
STI
21
STI
20
STI
11
STI
10
58H
R 00H
ACK
21
ACK
20
ACK
11
ACK
10
58H
W 00H
125
2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
MSTI
STOV STOV STOV STOV
21
20
11
10
SDS_
CONF
0
0
MCDA
MCDA21
0
0
STI
21
STI
20
DIOM_ DIOM_
INV SDS
MCDA20
MCDA11
STI
11
STI
10
59H R/W FFH
0
SDS_
BCL
5AH R/W 00H
MCDA10
5BH
R FFH
MOR
MONITOR Receive Data
5CH
R FFH
MOX
MONITOR Transmit Data
5CH
W FFH
R 00H
MOSR
MDR
MER
MDA
MAB
0
0
0
0
5DH
MOCR
MRE
MRC
MIE
MXC
0
0
0
0
5EH R/W 00H
MSTA
0
0
0
0
0
MAC
0
TOUT
5FH
R 00H
MCONF
0
0
0
0
0
0
0
TOUT
5FH
W 00H
Interrupt, General Configuration Registers
NAME
7
6
5
4
3
2
1
0
ADDR R/WRES
ISTA
0
0
ST
CIC
AUX TRAN MOS
ICD
60H
R 00H
MASK
1
1
ST
CIC
AUX TRAN MOS
ICD
60H
W FFH
AUXI
0
0
EAW WOV
TIN2
TIN1
0
0
61H
R 00H
AUXM
1
1
EAW WOV
TIN2
TIN1
1
1
61H
W FFH
MODE1
0
0
0
62H
R/W 00H
MODE2
0
0
0
63H
R/W 00H
ID
0
0
64H
R 01H
SRES
RES_
CI
0
64H
W 00H
TIMR2
TMD
0
65H
R/W 00H
Data Sheet
WTC1 WTC2 CFS RSS2 RSS1
0
INT_
POL
0
0
PPSDX
DESIGN
0
RES_ RES_ RES_ RES_ RES_
MON DCH IOM
TR RSTO
CNT
126
2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
Interrupt, General Configuration Registers
NAME
7
6
5
4
3
2
reserved
Data Sheet
127
1
0
ADDR R/WRES
66H6FH
2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
4.1
D-channel HDLC Control and C/I Registers
4.1.1
RFIFOD - Receive FIFO D-Channel
7
0
RFIFOD
Receive data
RD (00-1F)
A read access to any address within the range 00h-1Fh gives access to the “current”
FIFO location selected by an internal pointer which is automatically incremented after
each read access. This allows for the use of efficient “move string” type commands by
the microcontroller.
The RFIFOD contains up to 32 bytes of received data.
After an ISTAD.RPF interrupt, a complete data block is available. The block size can be
4, 8, 16 or 32 bytes depending on the EXMD2.RFBS setting.
After an ISTAD.RME interrupt, the number of received bytes can be obtained by reading
the RBCLD register.
4.1.2
XFIFOD - Transmit FIFO D-Channel
7
0
XFIFOD
Transmit data
WR (00-1F)
A write access to any address within the range 00-1FH gives access to the “current” FIFO
location selected by an internal pointer which is automatically incremented after each
write access. This allows the use of efficient “move string” type commands by the
microcontroller.
Depending on EXMD2.XFBS up to 16 or 32 bytes of transmit data can be written to the
XFIFOD following an ISTAD.XPR interrupt.
4.1.3
ISTAD - Interrupt Status Register D-Channel
Value after reset: 10H
7
ISTAD
Data Sheet
0
RME
RPF
RFO
XPR
XMR
128
XDU
0
0
RD (20)
2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
RME ... Receive Message End
One complete frame of length less than or equal to the defined block size
(EXMD1.RFBS) or the last part of a frame of length greater than the defined block size
has been received. The contents are available in the RFIFOD. The message length and
additional information may be obtained from RBCHD and RBCLD and the RSTAD
register.
RPF ... Receive Pool Full
A data block of a frame longer than the defined block size (EXMD1.RFBS) has been
received and is available in the RFIFOD. The frame is not yet complete.
RFO ... Receive Frame Overflow
The received data of a frame could not be stored, because the RFIFOD is occupied. The
whole message is lost.
This interrupt can be used for statistical purposes and indicates that the microcontroller
does not respond quickly enough to an RPF or RME interrupt (ISTAD).
XPR ... Transmit Pool Ready
A data block of up to the defined block size 16 or 32 (EXMD1.XFBS) can be written to
the XFIFOD.
An XPR interrupt will be generated in the following cases:
• after an XTF or XME command as soon as the 16 or 32 bytes in the XFIFO are
available and the frame is not yet complete
• after an XTF together with an XME command is issued, when the whole frame has
been transmitted
• after a reset of the transmitter (XRES)
• after a device reset
XMR ... Transmit Message Repeat
The transmission of the last frame has to be repeated because a collision on the S bus
has been detected after the 16th/32nd data byte of a transmit frame.
If an XMR interrupt occurs the transmit FIFO is locked until the XMR interrupt is read by
the host (interrupt cannot be read if masked in MASKD).
XDU ... Transmit Data Underrun
The current transmission of a frame is aborted by transmitting seven ’1’s because the
XFIFOD holds no further data. This interrupt occurs whenever the microcontroller has
failed to respond to an XPR interrupt (ISTAD register) quickly enough, after having
initiated a transmission and the message to be transmitted is not yet complete.
Data Sheet
129
2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
If an XDU interrupt occurs the transmit FIFO is locked until the XDU interrupt is read by
the host (interrupt cannot be read if masked in MASKD).
4.1.4
MASKD - Mask Register D-Channel
Value after reset: FFH
7
MASKD
0
RME
RPF
RFO
XPR
XMR
XDU
1
1
WR (20)
Each interrupt source in the ISTAD register can selectively be masked by setting the
corresponding bit in MASKD to ’1’. Masked interrupt status bits are not indicated when
ISTAD is read. Instead, they remain internally stored and pending until the mask bit is
reset to ’0’.
4.1.5
STARD - Status Register D-Channel
Value after reset: 40H
7
STARD
XDOV XFW
0
0
0
RACI
0
XACI
0
RD (21)
XDOV ... Transmit Data Overflow
More than 16 or 32 bytes (according to selected block size) have been written to the
XFIFOD, i.e. data has been overwritten.
XFW ... Transmit FIFO Write Enable
Data can be written to the XFIFOD. This bit may be polled instead of (or in addition to)
using the XPR interrupt.
RACI ... Receiver Active Indication
The D-channel HDLC receiver is active when RACI = ’1’. This bit may be polled. The
RACI bit is set active after a begin flag has been received and is reset after receiving an
abort sequence.
Data Sheet
130
2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
XACI ... Transmitter Active Indication
The D-channel HDLC-transmitter is active when XACI = ’1’. This bit may be polled. The
XACI-bit is active when an XTF-command is issued and the frame has not been
completely transmitted
4.1.6
CMDRD - Command Register D-channel
Value after reset: 00H
7
CMDRD
0
RMC RRES
0
STI
XTF
0
XME
XRES
WR (21)
RMC ... Receive Message Complete
Reaction to RPF (Receive Pool Full) or RME (Receive Message End) interrupt. By
setting this bit, the microcontroller confirms that it has fetched the data, and indicates that
the corresponding space in the RFIFOD may be released.
RRES ... Receiver Reset
HDLC receiver is reset, the RFIFOD is cleared of any data.
STI ... Start Timer 1
The ISAC-SX TE timer 1 is started when STI is set to one. The timer is stopped by writing
to the TIMR1 register.
Note: Timer 2 is controlled by the TIMR2 register only.
XTF ... Transmit Transparent Frame
After having written up to 16 or 32 bytes (EXMD1.XFBS) to the XFIFOD, the
microcontroller initiates the transmission of a transparent frame by setting this bit to ’1’.
The opening flag is automatically added to the message by the ISAC-SX TE (except in
the extended transparent mode where no flags are used).
XME ... Transmit Message End
By setting this bit to ’1’ the microcontroller indicates that the data block written last to the
XFIFOD completes the corresponding frame. The ISAC-SX TE terminates the
transmission by appending the CRC (if EXMD1.XCRC=0) and the closing flag sequence
to the data (except in the extended transparent mode where no such framing is used).
Data Sheet
131
2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
XRES ... Transmitter Reset
The D-channel HDLC transmitter is reset and the XFIFOD is cleared of any data. This
command can be used by the microcontroller to abort a frame currently in transmission.
Note: After an XPR interrupt further data has to be written to the XFIFOD and the
appropriate Transmit Command (XTF) has to be written to the CMDRD register
again to continue transmission, when the current frame is not yet complete (see
also XPR in ISTAD).
During frame transmission, the 0-bit insertion according to the HDLC bit-stuffing
mechanism is done automatically.
4.1.7
MODED - Mode Register
Value after reset: C0H
7
MODED
0
MDS2 MDS1 MDS0
0
RAC
DIM2
DIM1
DIM0
RD/WR (22)
MDS2-0 ... Mode Select
Determines the message transfer mode of the HDLC controller, as follows:
MDS2-0
Mode
Number of
Address
Bytes
Address Comparison
1.Byte
2.Byte
Remark
0
0
0 Reserved
0
0
1 Reserved
0
1
0 Non-Auto
mode
1
TEI1,TEI2
–
0
1
1 Non-Auto
mode
2
SAP1,SAP2,
SAPG
TEI1,TEI2,TEIG Two-byte
address
compare.
1
0
0 Extended
transparent
mode
1
1
0 Transparent –
mode 0
–
–
Data Sheet
132
One-byte
address
compare.
No address
compare.
All frames
accepted.
2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
MDS2-0
Mode
Number of
Address
Bytes
Address Comparison
1.Byte
Remark
2.Byte
1
1
1 Transparent > 1
mode 1
SAP1,SAP2,SA –
PG
1
0
1 Transparent > 1
mode 2
–
High-byte
address
compare.
TEI1,TEI2,TEIG Low-byte
address
compare.
Note: SAP1, SAP2: two programmable address values for the first received address
byte (in the case of an address field longer than 1 byte);
SAPG = fixed value FC / FEH.
TEI1, TEI2: two programmable address values for the second (or the only, in the
case of a one-byte address) received address byte; TEIG = fixed value FFH
Two different methods of the high byte and/or low byte address comparison can
be selected by setting SAP1.MHA and/or SAP2.MLA.
RAC ... Receiver Active
The D-channel HDLC receiver is activated when this bit is set to ’1’. If set to ’0’ the HDLC
data is not evaluated in the receiver.
DIM2-0 ... Digital Interface Modes
These bits define the characteristics of the IOM Data Ports (DU, DD). The DIM0 bit
enables/disables the collission detection. The DIM1 bit enables/disables the TIC bus
access. The effect of the individual DIM bits is summarized in the table below.
DIM2
DIM1
DIM0
Characteristics
0
0
Transparent D-channel, the collission detection is disabled
0
1
Stop/go bit evaluated for D-channel access handling
0
0
Last octet of IOM channel 2 used for TIC bus access
0
1
TIC bus access is disabled
1
x
Data Sheet
x
Reserved
133
2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
4.1.8
EXMD1- Extended Mode Register D-channel 1
Value after reset: 00H
7
EXMD1
0
XFBS
RFBS
SRA
XCRC RCRC
0
ITF
RD/WR (23)
XFBS … Transmit FIFO Block Size
0 … Block size for the transmit FIFO data is 32 byte
1 … Block size for the transmit FIFO data is 16 byte
Note: A change of XFBS will take effect after a receiver command (CMDRD.XME,
CMDRD.XRES, CMDRD.XTF) has been written.
RFBS … Receive FIFO Block Size
RFBS
Block Size Receive FIFO
Bit 6
Bit5
0
0
32 byte
0
1
16 byte
1
0
8 byte
1
1
4 byte
Note: A change of RFBS will take effect after a transmitter command (CMDR.RMC,
CMDR.RRES,) has been written
SRA … Store Receive Address
0 … Receive Address isn’t stored in the RFIFOD
1 … Receive Address is stored in the RFIFOD
XCRC … Transmit CRC
0 … CRC is transmitted
1 … CRC isn’t transmitted
RCRC… Receive CRC
0 … CRC isn’t stored in the RFIFOD
1 … CRC is stored in the RFIFOD
Data Sheet
134
2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
ITF… Interframe Time Fill
Selects the inter-frame time fill signal which is transmitted between HDLC-frames.
0 … idle (continuous ’1’)
1 … flags (sequence of patterns: ‘0111 1110’)
Note: ITF must be set to ’0’ for power down mode.
In applications with D-channel access handling (collision resolution), the only
possible inter-frame time fill is idle (continuous ’1’). Otherwise the D-channel on
the S/T-bus cannot be accessed
4.1.9
TIMR1 - Timer 1 Register
Value after reset: 00H
7
TIMR1
5
4
0
CNT
VALUE
RD/WR (24)
CNT ... Timer Counter
CNT together with VALUE determines the time period T after which a AUXI.TIN1
interrupt will be generated:
CNT=0...6:T = CNT x 2.048 sec + T1
with T1 = ( VALUE+1 ) x 0.064 sec
CNT=7:T = T1 = ( VALUE+1 ) x 0.064 sec
(generated periodically)
The timer can be started by setting the STI-bit in CMDRD and will be stopped when a
TIN1 interrupt is generated or the TIMR1 register is written.
Note: If CNT is set to 7, a TIN interrupt is indefinitely generated after every expiration of
T1 (i.e. T = T1).
VALUE ... Timer Value
Determines the value of the timer value T1 = ( VALUE + 1 ) x 0.064 sec.
4.1.10
SAP1 - SAPI1 Register
Value after reset: FCH
7
SAP1
Data Sheet
0
SAPI1
0
135
MHA
WR (25)
2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
SAPI1 ... SAPI1 value
Value of the first programmable Service Access Point Identifier (SAPI) according to the
ISDN LAPD protocol.
MHA... Mask High Address
0 …The SAPI address of an incomming frame is compared with SAP1, SAP2, SAPG.
1 …The SAPI address of an incomming frame is compared with SAP1 and SAPG.
SAP1 can be masked with SAP2 thereby bit positions of SAP1 are not compared
if they are set to ’1’ in SAP2.
4.1.11
SAP2 - SAPI2 Register
Value after reset: FCH
7
SAP2
0
SAPI2
0
MLA
WR (26)
SAPI2 ... SAPI2 value
Value of the second programmable Service Access Point Identifier (SAPI) according to
the ISDN LAPD-protocol.
MLA... Mask Low Address
0 …The TEI address of an incomming frame is compared with TEI1, TEI2 and TEIG.
1 …The TEI address of an incomming frame is compared with TEI1 and TEIG.
TEI1 can be masked with TEI2 thereby bit positions of TEI1 are not compared
if they are set to ’1’ in TEI2.
4.1.12
RBCLD - Receive Frame Byte Count Low D-Channel
Value after reset: 00H
7
RBCLD
0
RBC7
RBC0
RD (26)
RBC7-0 ... Receive Byte Count
Eight least significant bits of the total number of bytes in a received message (see
RBCHD register).
Data Sheet
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2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
4.1.13
RBCHD - Receive Frame Byte Count High D-Channel
Value after reset: 00H.
7
RBCHD
0
0
0
0
OV
RBC11
RBC8
RD (27)
OV ... Overflow
A ’1’ in this bit position indicates a message longer than (212 - 1) = 4095 bytes .
RBC8-11 ... Receive Byte Count
Four most significant bits of the total number of bytes in a received message (see
RBCLD register).
Note: Normally RBCHD and RBCLD should be read by the microcontroller after an
RME-interrupt in order to determine the number of bytes to be read from the
RFIFOD, and the total message length. The contents of the registers are valid only
after an RME or RPF interrupt, and remain so until the frame is acknowledged via
the RMC bit or RRES.
4.1.14
TEI1 - TEI1 Register 1
Value after reset: FFH
7
TEI1
0
TEI1
EA1
WR (27)
TEI1 ... Terminal Endpoint Identifier
In all message transfer modes except in transparent modes 0, 1 and extended
transparent mode, TEI1 is used by the ISAC-SX TE for address recognition. In the case
of a two-byte address field, it contains the value of the first programmable Terminal
Endpoint Identifier according to the ISDN LAPD-protocol.
In non-automodes with one-byte address field, TEI1 is a command address, according
to X.25 LAPB.
EA1 ... Address field Extension bit
This bit is set to ’1’ according to HDLC/LAPD.
Data Sheet
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2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
4.1.15
TEI2 - TEI2 Register
Value after reset: FFH
7
0
TEI2
TEI2
EA2
WR (28)
TEI2 ... Terminal Endpoint Identifier
In all message transfer modes except in transparent modes 0, 1 and extended
transparent mode, TEI2 is used by the ISAC-SX TE for address recognition. In the case
of a two-byte address field, it contains the value of the second programmable Terminal
Endpoint Identifier according of the ISDN LAPD-protocol.
In non-auto-modes with one-byte address field, TEI2 is a response address, according
to X.25 LAPD.
EA2 ... Address field Extension bit
This bit is to be set to ’1’ according to HDLC/LAPD.
4.1.16
RSTAD - Receive Status Register D-Channel
Value after reset: 0FH
7
RSTAD
0
VFR
RDO
CRC
RAB
SA1
SA0
C/R
TA
RD (28)
For general information please refer to Chapter 3.8.
VFR... Valid Frame
Determines whether a valid frame has been received.
The frame is valid (1) or invalid (0).
A frame is invalid when there is not a multiple of 8 bits between flag and frame end (flag,
abort).
RDO ... Receive Data Overflow
If RDO=1, at least one byte of the frame has been lost, because it could not be stored in
RFIFOD. As opposed to the ISTAD.RFO an RDO indicates that the beginning of a frame
has been received but not all bytes could be stored as the RFIFOD was temporarily full.
Data Sheet
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ISAC-SX TE
PSB 3186
Detailed Register Description
CRC ... CRC Check
The CRC is correct (1) or incorrect (0).
RAB ... Receive Message Aborted
The receive message was aborted by the remote station (1), i.e. a sequence of seven
1’s was detected before a closing flag.
SA1-0 ... SAPI Address Identification
TA ... TEI Address Identification
SA1-0 are significant in non-automode with a two-byte address field, as well as in
transparent mode 3. TA is significant in all modes except in transparent modes 0 and 1.
Two programmable SAPI values (SAP1, SAP2) plus a fixed group SAPI (SAPG of value
FCH/FEH), and two programmable TEI values (TEI1, TEI2) plus a fixed group TEI (TEIG
of value FFH), are available for address comparison.
The result of the address comparison is given by SA1-0 and TA, as follows:
Address Match with
MDS2-0
SA1
SA0
TA
1st Byte
2nd Byte
010
(Non-Auto/8
Mode)
x
x
x
x
0
1
TEI2
TEI1
-
0
011
(Non-Auto/16 0
Mode)
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
SAP2
SAP2
SAPG
SAPG
SAP1
SAP1
TEIG
TEI2
TEIG
TEI1 or TEI2
TEIG
TEI1
111
(Transparent
Mode1)
0
0
1
0
1
0
x
x
x
SAP2
SAPG
SAP1
-
101
(Transparent
Mode 2)
-
-
0
1
-
TEIG
TEI1 or TEI2
1
1
x
reserved
Note: If SAP1 and SAP2 contain identical values, the combination SAP1,2-TEIG will
only be indicated by SA1,0 = ’10’ (i.e. the value ’00’ will not occur in this case).
Data Sheet
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2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
C/R ... Command/Response
The C/R bit contains the C/R bit of the received frame (Bit1 in the SAPI address)
Note: The contents of RSTAD corresponds to the last received HDLC frame; it is
duplicated into RFIFOD for every frame (last byte of frame)
4.1.17
TMD -Test Mode Register D-Channel
Value after reset: 00H
7
TMD
0
0
0
0
0
0
0
0
TLP
RD/WR (29)
For general information please refer to Chapter 3.9.
TLP ... Test Loop
The TX path of layer-2 is internally connected with the RX path of layer-2. Data coming
from the layer 1 controller will not be forwarded to the layer 2 controller.
The setting of TLP is only valid if the IOM interface is active.
4.1.18
CIR0 - Command/Indication Receive 0
Value after reset: F3H
7
CIR0
0
CODR0
CIC0
CIC1
S/G
BAS
RD (2E)
CODR0 ... C/I Code 0 Receive
Value of the received Command/Indication code. A C/I-code is loaded in CODR0 only
after being the same in two consecutive IOM-frames and the previous code has been
read from CIR0.
CIC0 ... C/I Code 0 Change
A change in the received Command/Indication code has been recognized. This bit is set
only when a new code is detected in two consecutive IOM-frames. It is reset by a read
of CIR0.
Data Sheet
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ISAC-SX TE
PSB 3186
Detailed Register Description
CIC1 ... C/I Code 1 Change
A change in the received Command/Indication code in IOM-channel 1 has been
recognized. This bit is set when a new code is detected in one IOM-frame. It is reset by
a read of CIR0.
S/G ... Stop/Go Bit Monitoring
Indicates the availability of the upstream D-channel on the S/T interface.
1: Stop
0: Go
BAS ... Bus Access Status
Indicates the state of the TIC-bus:
0: the ISAC-SX TE itself occupies the D- and C/I-channel
1: another device occupies the D- and C/I-channel
Note: The CODR0 bits are updated every time a new C/I-code is detected in two
consecutive IOM-frames. If several consecutive valid new codes are detected and
CIR0 is not read, only the first and the last C/I code is made available in CIR0 at
the first and second read of that register, respectively.
4.1.19
CIX0 - Command/Indication Transmit 0
Value after reset: FEH
7
CIX0
0
CODX0
TBA2 TBA1 TBA0
BAC
WR (2E)
CODX0 ... C/I-Code 0 Transmit
Code to be transmitted in the C/I-channel 0.
The code is only transmitted if the TIC bus is occupied. If TIC bus is enabled but
occupied by another device, only “1s” are transmitted.
TBA2-0 ... TIC Bus Address
Defines the individual address for the ISAC-SX TE on the IOM bus.
This address is used to access the C/I- and D-channel on the IOM interface.
Note: If only one device is liable to transmit in the C/I- and D-channels of the IOM it
should always be given the address value ’7’.
Data Sheet
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2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
BAC ... Bus Access Control
Only valid if the TIC-bus feature is enabled (MODED.DIM2-0).
If this bit is set, the ISAC-SX TE will try to access the TIC-bus to occupy the C/I-channel
even if no D-channel frame has to be transmitted. It should be reset when the access
has been completed to grant a similar access to other devices transmitting in that
IOM-channel.
Note: Access is always granted by default to the ISAC-SX TE with TIC-Bus Address
(TBA2-0, STCR register) ’7’, which has the lowest priority in a bus configuration.
4.1.20
CIR1 - Command/Indication Receive 1
Value after reset: FEH
7
CIR1
0
CODR1
CICW
CI1E
RD (2F)
CODR1 ... C/I-Code 1 Receive
CICW, CI1E ... C/I-Channel Width, C/I-Channel 1 Interrupt Enable
These two bits contain the read back values from CIX1 register (see below).
4.1.21
CIX1 - Command/Indication Transmit 1
Value after reset: FEH
7
CIX1
0
CODX1
CICW
CI1E
WR (2F)
CODX1 ... C/I-Code 1 Transmit
Bits 7-2 of C/I-channel 1.
CICW... C/I-Channel Width
CICW selects between a 4 bit (’0’) and 6 bit (’1’) C/I1 channel width.
The C/I1 handler always reads and writes 6-bit values but if 4-bit is selected, the higher
two bits are ignored for interrupt generation. However in write direction the full CODX1
code is transmitted, i.e. the host must write the higher two bits to “1”.
Data Sheet
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2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
CI1E ... C/I-Channel 1 Interrupt Enable
Interrupt generation ISTA.CIC of CIR0.CIC1 is enabled (1) or masked (0).
Data Sheet
143
2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
4.2
Transceiver Registers
4.2.1
TR_CONF0 - Transceiver Configuration Register 0
Value after reset: 01H
7
TR_
CONF0
0
DIS_
TR
0
EN_
ICV
0
0
0
EXLP
LDD
RD/WR (30)
DIS_TR ... Disable Transceiver
Setting DIS_TR to “1” disables the transceiver. In order to reenable the transceiver
again, a transceiver reset must be issued (SRES.RES_TR = 1). The transceiver must
not be reenabled by setting DIS_TR from “1” to “0”.
For general information please refer to Chapter 3.3.9.
EN_ICV ... Enable Illegal Code Violation
0: normal operation
1: ICV enabled. The receipt of at least one illegal code violation within one multi-frame
is indicated by the C/I indication ’1011’ (CVR) in two consecutive IOM frames.
EXLP ... External loop
In case the analog loopback is activated with C/I = ARL the loop is a
0: internal loop next to the line pins
1: external loop which has to be closed between SR1/2 and SX1/SX2
Note: The external loop is only useful if bit DIS_TX of register TR_CONF2 is set to ’0’.
For general information please refer to Chapter 3.3.10.
LDD ... Level Detection Discard
0: Automatic clock generation after detection of any signal on the line in
power down state
1: No clock generation after detection of any signal on the line in power down state
Note: If an interrupt by the level detect circuitry is generated, the microcontroller has to
set this bit to ’0’ for an activation of the S/T interface.
For general information please refer to Chapter 3.3.8 and Chapter 3.7.6.
Data Sheet
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2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
4.2.2
TR_CONF1 - Transceiver Configuration Register 1
Value after reset: 0xH
7
TR_
CONF1
0
0
RPLL_ EN_
ADJ SFSC
0
0
x
x
x
RD/WR (31)
RPLL_ADJ ... Receive PLL Adjustment
0: DPLL tracking step is 0.5 XTAL period per S-frame
1: DPLL tracking step is 1 XTAL period per S-frame
EN_SFSC ... Enable Short FSC
0: No short FSC is generated
1: A short FSC is generated once per multi-frame (every 40th IOM frame)
x ... Undefined
The value of these bits depends on the selected mode. It is important to note that these
bits must not be overwritten to a different value when accessing this register.
4.2.3
TR_CONF2 - Transmitter Configuration Register 2
Value after reset: 80H
7
TR_
CONF2
0
DIS_
TX
PDS
0
RLP
0
0
0
0
RD/WR (32)
DIS_TX ... Disable Line Driver
0: Transmitter is enabled
1: Transmitter is disabled
For general information please refer to Chapter 3.3.9.
PDS ... Phase Deviation Select
Defines the phase deviation of the S-transmitter.
0: The phase deviation is 2 S-bits minus 7 oscillator periods plus analog delay plus
delay of the external circuitry.
Data Sheet
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2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
1: The phase deviation is 2 S-bits minus 9 oscillator periods plus analog delay plus
delay of the external circuitry.
For general information please refer to Chapter 3.3.7.
RLP ... Remote Line Loop
0: Remote Line Loop open
1: Remote Line Loop closed
For general information please refer to Chapter 3.3.10.
4.2.4
TR_STA - Transceiver Status Register
Value after reset: 00H
7
TR_STA
0
RINF
SLIP
ICV
0
FSYN
0
LD
RD (33)
RINF ... Receiver INFO
00: Received INFO 0
01: Received any signal except INFO 0,2,4
10: Reserved INFO 2
11: Received INFO 4
SLIP ... SLIP Detected
A ’1’ in this bit position indicates that a SLIP is detected in the receive or transmit path.
ICV ... Illegal Code Violation
0: No illegal code violation is detected
1: llegal code violation (ANSI T1.605) in data stream is detected
FSYN ... Frame Synchronization State
0: The S/T receiver is not synchronized
1: The S/T receiver has synchronized to the framing bit F
LD ... Level Detection
0: No receive signal has been detected on the line.
1: Any receive signal has been detected on the line.
Data Sheet
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2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
4.2.5
SQRR1 - S/Q-Channel Receive Register 1
Value after reset: 40H
7
SQRR
0
MSYN MFEN
0
0
SQR1 SQR2 SQR3 SQR4
RD (35)
For general information please refer to Chapter 3.3.2.
MSYN ... Multi-frame Synchronization State
0: The S/T receiver has not synchronized to the received FA and M bits
1: The S/T receiver has synchronized to the received FA and M bits
MFEN ... Multiframe Enable
Read-back of the MFEN bit of the SQXR register
SQR11-14 ... Received S Bits
Received S bits in frames 1, 6, 11 and 16
4.2.6
SQXR1- S/Q-Channel TX Register 1
Value after reset: 4FH
7
SQXR1
0
0
MFEN
0
0
SQX1 SQX2 SQX3 SQX4
WR (35)
MFEN ... Multiframe Enable
Used to enable or disable the multiframe structure (see Chapter 3.3.2)
0: S/T multiframe is disabled
1: S/T multiframe is enabled
Readback value in SQRR1.
SQX1-4 ... Transmitted S/Q Bits
Transmitted Q bits (FA bit position) in frames 1, 6, 11 and 16.
Data Sheet
147
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ISAC-SX TE
PSB 3186
Detailed Register Description
4.2.7
SQRR2 - S/Q-Channel Receive Register 2
Value after reset: 00H
7
SQRR2
0
SQR21 SQR22 SQR23 SQR24 SQR31 SQR32 SQR33 SQR34
RD (36)
SQR21-24, SQR31-34... Received S Bits
Received S bits in frames 2, 7, 12 and 17 (SQR21-24, subchannel 2),
and in frames 3, 8, 13 and 18 (SQR31-34, subchannel 3).
4.2.8
SQRR3 - S/Q-Channel Receive Register 3
Value after reset: 00H
7
SQRR3
0
SQR41 SQR42 SQR43 SQR44 SQR51 SQR52 SQR53 SQR54
RD (37)
SQR41-44, SQR51-54... Received S Bits
Received S bits in frames 4, 9, 14 and 19 (SQR41-44, subchannel 4),
and in frames 5, 10, 15 and 20 (SQR51-54, subchannel 5).
4.2.9
ISTATR - Interrupt Status Register Transceiver
Value after reset: 00H
7
ISTATR
0
x
x
x
x
LD
RIC
SQC
SQW
RD (38)
For all interrupts in the ISTATR register the following logical states are defined:
0: Interrupt is not acitvated
1: Interrupt is acitvated
x ... Reserved
Bits set to “1” in this bit position must be ignored.
Data Sheet
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ISAC-SX TE
PSB 3186
Detailed Register Description
LD ... Level Detection
Any receive signal has been detected on the line. This bit is set to “1” (i.e. an interrupt is
generated if not masked) as long as any receiver signal is detected on the line.
RIC ... Receiver INFO Change
RIC is activated if one of the TR_STA bits RINF or ICV has changed. This bit is reset by
reading the TR_STA register.
SQC ... S/Q-Channel Change
A change in the received S-channel has been detected. The new code can be read from
the SQRxx bits of registers SQRR1-3 within the duration of the next multiframe (5 ms).
This bit is reset by a read access to the corresponding SQRRx register.
SQW ... S/Q-Channel Writable
The S/Q channel data for the next multiframe is writable.
The register for the Q (S) bits to be transmitted (received) has to be written (read) within
the duration of the next multiframe (5 ms). This bit is reset by writing register SQXRx.
4.2.10
MASKTR - Mask Transceiver Interrupt
Value after reset: FFH
7
MASKTR
0
1
1
1
1
LD
RIC
SQC
SQW
RD/WR (39)
The transceiver interrupts LD, RIC, SQC and SQW are enabled (0) or disabled (1).
4.2.11
ACFG2 - Auxiliary Configuration Register
Value after reset: 00H
7
ACFG2
0
0
0
0
0
ACL
LED
0
0
RD/WR (3D)
Note: Although no other Auxiliary Configuration Registers are supported by ISAC-SX
TE, the name ACFG2 for this register was chosen intentionally in compliance with
ISAC-SX PEB3086.
Data Sheet
149
2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
ACL ... ACL Function Select
0: Pin ACL automatically indicates the S-bus activation status by a LOW level.
1: The output state of ACL is programmable by the host in bit LED.
Note: An LED with preresistance my directly be connected to ACL.
LED ... LED Control
If enabled (ACL = 1) the LED with preresistance connected across VDD and ACL is
switched ...
0: ... OFF (high level on pin ACL)
1: ... ON (low level on pin ACL)
Data Sheet
150
2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
4.3
IOM-2 and MONITOR Handler
4.3.1
CDAxy - Controller Data Access Register xy
7
0
CDAxy
Controller Data Access Register
RD/WR
(40-43)
Data registers CDAxy which can be accessed from the controller.
Register
Register Address
Value after Reset
CDA10
40H
FFH
CDA11
41H
FFH
CDA20
42H
FFH
CDA21
43H
FFH
4.3.2
XXX_TSDPxy - Time Slot and Data Port Selection for CHxy
7
XXX_
TSDPxy
0
DPS
0
0
TSS
RD/WR
(44-4D)
Register
Register Address
Value after Reset
CDA_TSDP10
44H
00H ( = output on B1-DD)
CDA_TSDP11
45H
01H ( = output on B2-DD)
CDA_TSDP20
46H
80H ( = output on B1-DU)
CDA_TSDP21
47H
81H ( = output on B2-DU)
TR_TSDP_BC1
4CH
00H ( = transceiver output on B1-DD)
TR_TSDP_BC2
4DH
01H ( = transceiver output on B2-DD)
This register determines the time slots and the data ports on the IOM-2 interface for the
data channels ’xy’ of the functional units ’XXX’ which are Controller Data Access (CDA)
and Transceiver (TR).
Data Sheet
151
2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
The position of B-channel data from the S-interface is programmed in TR_TSDP_BC1
and TR_TSDP_BC2.
DPS ... Data Port Selection
0: The data channel xy of the functional unit XXX is output on DD.
The data channel xy of the functional unit XXX is input from DU.
1: The data channel xy of the functional unit XXX is output on DU.
The data channel xy of the functional unit XXX is input from DD.
Note: For the CDA (controller data access) data the input is determined by the
CDA_CRx.SWAP bit. If SWAP = ’0’ the input for the CDAxy data is vice versa to
the output setting for CDAxy. If the SWAP = ’1’ the input from CDAx0 is vice versa
to the output setting of CDAx1 and the input from CDAx1 is vice versa to the output
setting of CDAx0. See controller data access description in Chapter 3.7.1.1
TSS ... Timeslot Selection
Selects one of 32 timeslots (0...31) on the IOM-2 interface for the data channels.
4.3.3
CDAx_CR - Control Register Controller Data Access CH1x
7
CDAx_
CR
0
0
0
EN_
TBM
EN_I1 EN_I0 EN_O1 EN_O0 SWAP
RD/WR
(4E-4F)
Register
Register Address
Value after Reset
CDA1_CR
4EH
00H
CDA2_CR
4FH
00H
For general information please refer to Chapter 3.7.1.1.
EN_TBM ... Enable TIC Bus Monitoring
0: The TIC bus monitoring is disabled
1: The TIC bus monitoring with the CDAx0 register is enabled. The TSDPx0 register
must be set to 08H for monitoring from DU or 88H for monitoring from DD,
respectively (this selection is only valid if IOM_CR.TIC_DIS = 0).
Data Sheet
152
2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
EN_I1, EN_I0 ... Enable Input CDAx0, CDAx1
0: The input of the CDAx0, CDAx1 register is disabled
1: The input of the CDAx0, CDAx1 register is enabled
EN_O1, EN_O0 ... Enable Output CDAx0, CDAx1
0: The output of the CDAx0, CDAx1 register is disabled
1: The output of the CDAx0, CDAx1 register is enabled
SWAP ... Swap Inputs
0: The time slot and data port for the input of the CDAxy register is defined by its own
TSDPxy register. The data port for the CDAxy input is vice versa to the output setting
for CDAxy.
1: The input (time slot and data port) of the CDAx0 is defined by the TSDP register of
CDAx1 and the input of CDAx1 is defined by the TSDP register of CDAx0. The data
port for the CDAx0 input is vice versa to the output setting for CDAx1. The data port
for the CDAx1 input is vice versa to the output setting for CDAx0. The input definition
for time slot and data port CDAx0 are thus swapped to CDAx1 and for CDAx1 to
CDAx0. The outputs are not affected by the SWAP bit.
4.3.4
TR_CR - Control Register Transceiver Data (IOM_CR.CI_CS=0)
Value after reset: F8H
7
TR_CR
0
EN_
D
EN_
B2R
EN_
B1R
EN_
B2X
EN_
B1X
CS2-0
RD/WR (50)
Read and write access to this register is only possible if IOM_CR.CI_CS = 0.
EN_D ... Enable Transceiver D-Channel Data
EN_B2R ... Enable Transceiver B2 Receive Data
EN_B1R ... Enable Transceiver B1 Receive Data
EN_B2X ... Enable Transceiver B2 Transmit Data
EN_B1X ... Enable Transceiver B1 Transmit Data
This register is used to individually enable/disable the D-channel (both RX and TX
direction) and the receive/transmit paths for the B-channel of the S-transceiver.
0: The corresponding data path to the transceiver is disabled.
1: The corresponding data path to the transceiver is enabled.
Data Sheet
153
2003-01-30
ISAC-SX TE
PSB 3186
Detailed Register Description
CS2-0 ... Channel Select for Transceiver D-channel
This register is used to select one of eight IOM channels to which the transceiver
D-channel data is related to.
Note: It should be noted that writing TR_CR.CS2-0 will also write to TRC_CR.CS2-0 and
therefore modify the channel selection for the transceiver
C/I0 data.
4.3.4.1
TRC_CR - Control Register Transceiver C/I0 (IOM_CR.CI_CS=1)
Value after reset: 00H
7
TRC_CR
0
0
0
0
0
0
CS2-0
RD/WR (50)
Write access to this register is possible if IOM_CR.CI_CS = 0 or IOM_CR.CI_CS = 1.
Read access to this register is possible only if IOM_CR.CI_CS = 1.
CS2-0 ... Channel Select for the Transceiver C/I0 Channel
This register is used to select one of eight IOM channels to which the transceiver C/I0
channel data is related to.
4.3.5
DCI_CR - Control Register for D and CI1 Handler
(IOM_CR.CI_CS=0)
Value after reset: A0H
7
DCI_CR
DPS_
CI1
0
EN_
CI1
D_
D_
D_
EN_D EN_B2 EN_B1
CS2-0
RD/WR (53)
Read and write access to this register is only possible if IOM_CR.CI_CS = 0.
DPS_CI1 ... Data Port Selection CI1 Handler Data
0: The CI1 handler data is output on DD and input from DU
1: The CI1 handler data is output on DU and input from DD
EN_CI1 ... Enable CI1 Handler Data
0: CI1 handler data access is disabled
1: CI1 handler data access is enabled
Data Sheet
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Detailed Register Description
Note: The timeslot for the C/I1 handler cannot be programmed but is fixed to IOM
channel 1.
D_EN_D ... Enable D-timeslot for D-channel controller
D_EN_B2 ... Enable B2-timeslot for D-channel controller
D_EN_B1 ... Enable B1-timeslot for D-channel controller
These bits are used to select the timeslot length for the D-channel HDLC controller
access as it is capable to access not only the D-channel timeslot. The host can
individually enable two 8-bit timeslots B1- and B2-channel (D_EN_B1, D_EN_B2) and
one 2-bit timeslot D-channel (D_EN_D) on IOM-2. The position is selected via CS2-0.
0: D-channel controller does not access timeslot data B1, B2 or D, respectively
1: D-channel controller does access timeslot data B1, B2 or D, respectively
CS2-0 ... Channel Select for D-channel controller
This register is used to select one of eight IOM channels. If enabled, the D-channel data
is connected to the corresponding timeslots of that IOM channel.
Note: It should be noted that writing DCI_CR.CS2-0 will also write to DCIC_CR.CS2-0
and therefore modify the channel selection for the data of the
C/I0 handler.
4.3.5.1
DCIC_CR - Control Register for CI0 Handler (IOM_CR.CI_CS=1)
Value after reset: 00H
7
DCIC_CR
0
0
0
0
0
0
CS2-0
RD/WR (13)
Write access to this register is possible if IOM_CR.CI_CS = 0 or IOM_CR.CI_CS = 1.
Read access to this register is possible only if IOM_CR.CI_CS = 1.
CS2-0 ... Channel Select for C/I0 Handler
This register is used to select one of eight IOM channels. If enabled, the data of the
C/I0-handler is connected to the corresponding C/I0 timeslots of that IOM channel.
Data Sheet
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Detailed Register Description
4.3.6
MON_CR - Control Register Monitor Data
Value after reset: 40H
7
MON_CR
0
DPS
EN_
MON
0
0
0
CS2-0
RD/WR (54)
For general information please refer to Chapter 3.7.3.
DPS ... Data Port Selection
0: The Monitor data is output on DD and input from DU
1: The Monitor data is output on DU and input from DD
EN_MON ... Enable Output
0: The Monitor data input and output is disabled
1: The Monitor data input and output is enabled
CS2-0 ... MONITOR Channel Selection
000: The MONITOR data is input/output on MON0 (3rd timeslot on IOM-2)
001: The MONITOR data is input/output on MON1 (7th timeslot on IOM-2)
010: The MONITOR data is input/output on MON2 (11th timeslot on IOM-2)
:
111: The MONITOR data is input/output on MON7 (31st timeslot on IOM-2)
4.3.7
SDS_CR - Control Register Serial Data Strobe
Value after reset: 00H
7
SDS_CR
0
ENS_ ENS_ ENS_
TSS TSS+1 TSS+3
TSS
RD/WR
(55)
This register is used to select position and length of the strobe signal. The length can be
any combination of two 8-bit timeslot (ENS_TSS, ENS_TSS+1) and one 2-bit timeslot
(ENS_TSS+3).
For general information please refer to Chapter 3.7.2 and Chapter 3.7.2.2.
Data Sheet
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Detailed Register Description
ENS_TSS ... Enable Serial Data Strobe of timeslot TSS
ENS_TSS+1 ... Enable Serial Data Strobe of timeslot TSS+1
0: The serial data strobe signal SDSx is inactive during TSS, TSS+1
1: The serial data strobe signal SDSx is active during TSS, TSS+1
ENS_TSS+3 ... Enable Serial Data Strobe of timeslot TSS+3 (D-Channel)
0: The serial data strobe signal SDSx is inactive during the D-channel (bit7, 6) of TSS+3
1: The serial data strobe signal SDSx is active during the D-channel (bit7, 6) of TSS+3
TSS ... Timeslot Selection
Selects one of 32 timeslots on the IOM-2 interface (with respect to FSC) during which
SDSx is active high or provides a strobed BCL clock output (see
SDS_CONF.SDS_BCL). The data strobe signal allows standard data devices to access
a programmable channel.
4.3.8
IOM_CR - Control Register IOM Data
Value after reset: 08H
7
IOM_CR
0
SPU
0
CI_CS TIC_
DIS
EN_
BCL
CLKM DIS_
OD
DIS_
IOM
RD/WR (57)
SPU ... Software Power Up
0: The DU line is normally used for transmitting data
1: Setting this bit to ’1’ will pull the DU line to low. This will enforce connected layer 1
devices to deliver IOM-clocking.
After a subsequent ISTA.CIC-interrupt (C/I-code change) and reception of the C/I-code
”PU” (Power Up indication in TE-mode) the microcontroller writes an AR or TIM
command as C/I-code in the CIX0-register, resets the SPU bit and waits for the following
CIC-interrupt.
For general information please refer to Chapter 3.7.6.
CI_CS ... C/I Channel Selection
The channel selection for D-channel and C/I-channel is done in the channel select bits
CH2-0 of register TR_CR (for the transceiver) and DCI_CR (for the D-channel controller
and C/I-channel controller).
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Detailed Register Description
0: A write access to CS2-0 has effect on the configuration of D- and C/I-channel,
whereas a read access delivers the D-channel configuration only.
1: A write access to CS2-0 has effect on the configuration of the C/I-channel only,
whereas a read access delivers the C/I-channel configuration only.
TIC_DIS ... TIC Bus Disable
0: The last octet of IOM channel 2 (12th timeslot) is used as TIC bus.
1: The TIC bus is disabled. The last octet of the last IOM time slot (TS 11) can be used
as every time slot.
EN_BCL ... Enable Bit Clock BCL
0: The BCL clock is disabled
1: The BCL clock is enabled.
CLKM ... Clock Mode
If the transceiver is disabled (DIS_TR = ’1’) the DCL from the IOM-2 interface is an input.
0: A double bit clock is connected to DCL
1: A single bit clock is connected to DCL
For general information please refer to Chapter 3.7.
DIS_OD ... Disable Open Drain Drivers
0: DU/DD are open drain drivers
1: DU/DD are push pull drivers
DIS_IOM ... Disable IOM
DIS_IOM should be set to ’1’ if external devices connected to the IOM interface should
be “disconnected“ e.g. for power saving purposes or for not disturbing the internal IOM
connection between layer 1 and layer 2. However, the ISAC-SX TE internal operation
between S-transceiver, B-channel and D-channel controller is independent of the
DIS_IOM bit.
0: The IOM interface is enabled
1: The IOM interface is disabled. The FSC, DCL clock outputs have high impedance;
clock inputs are active; DU, DD data line inputs are switched off and outputs have high
impedance; except in TE/LT-T mode the DU line is input (“0”-level causes activation), so
the DU pin must be terminated (pull up resistor).
Data Sheet
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Detailed Register Description
4.3.9
STI - Synchronous Transfer Interrupt
Value after reset: 00H
7
STI
0
STOV STOV STOV STOV
21
20
11
10
STI
21
STI
20
STI
11
STI
10
RD (58)
For all interrupts in the STI register the following logical states are applied:
0: Interrupt is not activated
1: Interrupt is activated
The interrupts are automatically reset by reading the STI register. For general
information please refer to Chapter 3.7.1.1.
STOVxy ... Synchronous Transfer Overflow Interrupt
Enabled STOV interrupts for a certain STIxy interrupt are generated when the STIxy has
not been acknowledged in time via the ACKxy bit in the ASTI register. This must be one
(for DPS=’0’) or zero (for DPS=’1’) BCL clocks before the time slot which is selected for
the STOV.
STIxy ... Synchronous Transfer Interrupt
Depending on the DPS bit in the corresponding TSDPxy register the Synchronous
Transfer Interrupt STIxy is generated two (for DPS=’0’) or one (for DPS=’1’) BCL clock
after the selected time slot (TSDPxy.TSS).
Note: ST0Vxy and ACKxy are useful for synchronizing microcontroller accesses and
receive/transmit operations. One BCL clock is equivalent to two DCL clock cycles.
4.3.10
ASTI - Acknowledge Synchronous Transfer Interrupt
Value after reset: 00H
7
ASTI
0
0
0
0
0
ACK
21
ACK
20
ACK
11
ACK
10
WR (58)
For general information please refer to Chapter 3.7.1.1.
Data Sheet
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Detailed Register Description
ACKxy ... Acknowledge Synchronous Transfer Interrupt
After an STIxy interrupt the microcontroller has to acknowledge the interrupt by setting
the corresponding ACKxy bit to “1”.
4.3.11
MSTI - Mask Synchronous Transfer Interrupt
Value after reset: FFH
7
MSTI
0
STOV STOV STOV STOV
21
20
11
10
STI
21
STI
20
STI
11
STI
10
RD/WR (59)
For the MSTI register the following logical states are applied:
0: Interrupt is not masked
1: Interrupt is masked
For general information please refer to Chapter 3.7.1.1.
STOVxy ... Synchronous Transfer Overflow for STIxy
Mask bits for the corresponding STOVxy interrupt bits.
STIxy ... Synchronous Transfer Interrupt xy
Mask bits for the corresponding STIxy interrupt bits.
4.3.12
SDS_CONF - Configuration Register for Serial Data Strobe
Value after reset: 00H
7
SDS_
CONF
0
0
0
0
0
DIOM_ DIOM_
INV
SDS
0
SDS_ RD/WR (5A)
BCL
For general information on SDS_BCL please refer to Chapter 3.7.2.
DIOM_INV ... DU/DD on IOM Timeslot Inverted
0: DU/DD are active during SDS HIGH phase and inactive during the LOW phase.
1: DU/DD are active during SDS LOW phase and inactive during the HIGH phase.
This bit has only effect if DIOM_SDS is set to ’1’ otherwise DIOM_INV is don’t care.
Data Sheet
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Detailed Register Description
DIOM_SDS ... DU/DD on IOM Controlled via SDS
0: The pin SDS and its configuration settings are used for serial data strobe only. The
IOM-2 data lines are not affected.
1: The DU/DD lines are deactivated during the during High/Low phase (selected via
DIOM_INV) of the SDS signal. The SDS timeslot is selected in SDS_CR.
SDS_BCL ... Enable IOM Bit Clock for SDS
0: The serial data strobe is generated in the programmed timeslot.
1: The IOM bit clock is generated in the programmed timeslot.
4.3.13
MCDA - Monitoring CDA Bits
Value after reset: FFH
7
MCDA
0
MCDA21
Bit7
Bit6
MCDA20
Bit7
Bit6
MCDA11
Bit7
Bit6
MCDA10
Bit7
RD (5B)
Bit6
MCDAxy ... Monitoring CDAxy Bits
Bit 7 and Bit 6 of the CDAxy registers are mapped into the MCDA register.
This can be used for monitoring the D-channel bits on DU and DD and the ’Echo bits’ on
the TIC bus with the same register
4.3.14
MOR - MONITOR Receive Channel
Value after reset: FFH
7
MOR
0
Monitor Receiver Data
RD (5C)
Contains the MONITOR data received in the IOM-2 MONITOR channel according to the
MONITOR channel protocol. The MONITOR channel (0-7) can be selected by setting the
monitor channel select bit MON_CR.MCS.
Data Sheet
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Detailed Register Description
4.3.15
MOX - MONITOR Transmit Channel
Value after reset: FFH
7
0
MOX
Monitor Transmit Data
WR (5C)
Contains the MONITOR data to be transmitted in IOM-2 MONITOR channel according
to the MONITOR channel protocol.The MONITOR channel (0-7) can be selected by
setting the monitor channel select bit MON_CR.MCS
4.3.16
MOSR - MONITOR Interrupt Status Register
Value after reset: 00H
7
MOSR
0
MDR
MER
MDA
MAB
0
0
0
0
RD (5D)
MDR ... MONITOR channel Data Received
MER ... MONITOR channel End of Reception
MDA ... MONITOR channel Data Acknowledged
The remote end has acknowledged the MONITOR byte being transmitted.
MAB ... MONITOR channel Data Abort
4.3.17
MOCR - MONITOR Control Register
Value after reset: 00H
7
MOCR
0
MRE
MRC
MIE
MXC
0
0
0
0
RD/WR (5E)
MRE ... MONITOR Receive Interrupt Enable
0: MONITOR interrupt status MDR generation is masked
1: MONITOR interrupt status MDR generation is enabled
Data Sheet
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Detailed Register Description
MRC ... MR Bit Control
Determines the value of the MR bit:
0: MR is always ’1’. In addition, the MDR interrupt is blocked, except for the first byte of
a packet (if MRE = 1).
1: MR is internally controlled by the ISAC-SX TE according to MONITOR channel
protocol.
In addition, the MDR interrupt is enabled for all received bytes according to the
MONITOR channel protocol (if MRE = 1).
MIE ... MONITOR Interrupt Enable
MONITOR interrupt status MER, MDA, MAB generation is enabled (1) or masked (0).
MXC ... MX Bit Control
Determines the value of the MX bit:
0: The MX bit is always ’1’.
1: The MX bit is internally controlled by the ISAC-SX TE according to MONITOR
channel protocol.
4.3.18
MSTA - MONITOR Status Register
Value after reset: 00H
MSTA
0
0
0
0
0
MAC
0
TOUT
RD (5F)
MAC ... MONITOR Transmit Channel Active
The data transmisson in the MONITOR channel is in progress.
TOUT ... Time-Out
Read-back value of the TOUT bit.
Data Sheet
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PSB 3186
Detailed Register Description
4.3.19
MCONF - MONITOR Configuration Register
Value after reset: 00H
MCONF
0
0
0
0
0
0
0
TOUT
WR (5F)
TOUT... Time-Out
0: The monitor time-out function is disabled
1: The monitor time-out function is enabled
Data Sheet
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Detailed Register Description
4.4
Interrupt and General Configuration
4.4.1
ISTA - Interrupt Status Register
Value after reset: 00H
7
ISTA
0
0
0
ST
CIC
AUX
TRAN MOS
ICD
RD (60)
For all interrupts in the ISTA register following logical states are applied:
0: Interrupt is not acitvated
1: Interrupt is acitvated
ICD ... HDLC Interrupt from D-channel
An interrupt originated from the HDLC controller of the D-channel has been recognized.
ST ... Synchronous Transfer
This interrupt is generated to enable the microcontroller to lock on to the IOM timing for
synchronous transfers. The source can be read from the STI register.
CIC ... C/I Channel Change
A change in C/I channel 0 or C/I channel 1 has been recognized. The actual value can
be read from CIR0 or CIR1.
AUX ... Auxiliary Interrupts
Signals an interrupt generated from external awake (pin EAW), watchdog timer overflow,
timer1 or timer2. The source can be read from the auxiliary interrupt register AUXI.
TRAN ... Transceiver Interrupt
An interrupt originated in the transceiver interrupt status register (ISTATR) has been
recognized.
MOS ... MONITOR Status
A change in the MONITOR Status Register (MOSR) has occured.
Note: A read of the ISTA register clears none of the interrupts. They are only cleared by
reading the corresponding status register.
Data Sheet
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Detailed Register Description
4.4.2
MASK - Mask Register
Value after reset: FFH
7
MASK
0
1
1
ST
CIC
AUX
TRAN MOS
ICD
WR (60)
For the MASK register following logical states are applied:
0: Interrupt is enabled
1: Interrupt is disabled
Each interrupt source in the ISTA register can selectively be masked/disabled by setting
the corresponding bit in MASK to ’1’. Masked interrupt status bits are not indicated when
ISTA is read. Instead, they remain internally stored and pending, until the mask bit is
reset to ’0’.
Note: In the event of a C/I channel change, CIC is set in ISTA even if the corresponding
mask bit in MASK is set, but no interrupt is generated.
4.4.3
AUXI - Auxiliary Interrupt Status Register
Value after reset: 00H
7
AUXI
0
0
0
EAW
WOV
TIN2
TIN1
0
0
RD (61)
For all interrupts in the ISTA register the following logical states are applied:
0: Interrupt is not acitvated
1: Interrupt is acitvated
EAW ... External Awake Interrupt
An interrupt from the EAW pin has been detected.
WOV ... Watchdog Timer Overflow
Signals the expiration of the watchdog timer, which means that the microcontroller has
failed to set the watchdog timer control bits WTC1 and WTC2 (MODE1 register) in the
correct manner. A reset pulse has been generated by the ISAC-SX TE.
TIN2, 1 ... Timer Interrupt 1, 2
An interrupt originated from timer 1 or timer 2 is recognized, i.e the timer has expired.
Data Sheet
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PSB 3186
Detailed Register Description
4.4.4
AUXM - Auxiliary Mask Register
Value after reset: FFH
7
AUXM
0
1
1
EAW
WOV
TIN2
TIN1
1
1
WR (61)
For the MASK register following logical states are applied:
0: Interrupt is enabled
1: Interrupt is disabled
Each interrupt source in the AUXI register can selectively be masked/disabled by setting
the corresponding bit in AUXM to ’1’. Masked interrupt status bits are not indicated when
AUXI is read. Instead, they remain internally stored and pending, until the mask bit is
reset to ’0’.
4.4.5
MODE1 - Mode1 Register
Value after reset: 00H
7
MODE1
0
0
0
0
WTC1 WTC2
CFS
RSS2 RSS1
RD/WR (62)
WTC1, 2 ... Watchdog Timer Control 1, 2
After the watchdog timer mode has been selected (RSS = ’11’) the watchdog timer is
started. During every time period of 128 ms the microcontroller has to program the
WTC1 and WTC2 bit in the following sequence
1.
2.
WTC1
WTC2
1
0
0
1
to reset and restart the watchdog timer.
If WTC1/2 is not written fast enough in this way, the timer expires and a WOV-interrupt
(AUXI register) together with a reset pulse is generated.
CFS ... Configuration Select
This bit determines clock relations and recovery on S/T and IOM interfaces.
Data Sheet
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Detailed Register Description
0: The IOM interface clock and frame signals are always active, "Power Down" state
included.
The states "Power Down" and "Power Up" are thus functionally identical except for the
indication: PD = 1111 and PU = 0111.
With the C/I command Timing (TIM) the microcontroller can enforce the "Power Up" state
and with C/I command Deactivation Indication (DI) the "Power Down" state is reached
again.
However, it is also possible to activate the S-interface directly with the C/I command
Activate Request (AR 8/10/L) without the TIM command.
1: The IOM interface clock and frame signals are normally inactive ("Power Down").
For activating the IOM-2 clocks the "Power Up" state can be induced by software
(IOM_CR.SPU) or by resetting CFS again.
After that the S-interface can be activated with the C/I command Activate Request (AR
8/10/L). The "Power Down" state can be reached again with the C/I command
Deactivation Indication (DI).
Note: After reset the IOM interface is always active. To reach the "Power Down" state
the CFS-bit has to be set.
For general information please refer to Chapter 3.3.8.
RSS2, RSS1... Reset Source Selection 2,1
The ISAC-SX TE reset sources for the RSTO output pin can be selected according to
the table below.
RSS
C/I Code Change
EAW
Watchdog Timer
--
--
Bit 1
Bit 0
0
0
--
0
1
(reserved)
1
0
x
x
--
1
1
--
--
x
• If RSS = ’00’ no above listed reset source is selected and therefore no reset is
generated at RSTO.
• Watchdog Timer
After the selection of the watchdog timer (RSS = ’11’) the timer is reset and started.
During every time period of 128 ms the microcontroller has to program the WTC1 and
WTC2 bits in two consecutive bit pattern (see description of the WTC1, 2 bits)
otherwise the watchdog timer expires and a reset pulse of 125 µs £ t£ 250 µs is
generated. Deactivation of the watchdog timer is only possible with a hardware reset.
Data Sheet
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Detailed Register Description
• If RSS = ’10’ is selected the following two reset sources generate a reset pulse of
125 µs £ t £ 250µs at the RSTO pin:
- External (Subscriber) Awake (EAW)
The EAW input pin serves as a request signal from the subscriber to initiate the awake
function in a terminal and generates a reset pulse (in TE mode only).
- Exchange Awake (C/I Code)
A C/I Code change generates a reset pulse.
After a reset pulse generated by the ISAC-SX TE and the corresponding interrupt (WOV
or CIC) the actual reset source can be read from the ISTA.
4.4.6
MODE2 - Mode2 Register
Value after reset: 00H
7
MODE2
0
0
0
0
0
INT_
POL
0
0
PPSDX RD/WR (63)
INT_POL ... Interrupt Polarity
Selects the polarity of the interrupt pin INT.
0: low active with open drain characteristic (default)
1: high active with push pull characteristic
PPSDX ... Push/Pull Output for SDX (SCI Interface)
0: The SDX pin has open drain characteristic
1: The SDX pin has push/pull characteristic
4.4.7
ID - Identification Register
Value after reset: 01H
7
ID
Data Sheet
0
0
0
DESIGN
169
RD (64)
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PSB 3186
Detailed Register Description
DESIGN ... Design Number
The design number allows to identify different hardware designs of the ISAC-SX TE by
software.
01H: V 1.4
(all other codes reserved)
4.4.8
SRES - Software Reset Register
Value after reset: 00H
7
SRES
0
RES_
CI
0
0
RES_ RES_ RES_ RES_ RES_
MON DCH IOM
TR RSTO
WR (64)
RES_xx ... Reset Functional Block xx
A reset can be activated on the functional block C/I-handler, Monitor channel, D-channel,
IOM handler, S-transceiver and to pin RSTO.
Setting one of these bits to “1” causes the corresponding block to be reset for a duration
of 4 BCL clock cycles, except RES_RSTO which is activated for a duration of
125 ... 250µs. The bits are automatically reset to “0” again.
4.4.9
TIMR2 - Timer 2 Register
Value after reset: 00H
7
TIMR2
0
TMD
0
CNT
RD/WR (65)
TMD ... Timer Mode
Timer 2 can be used in two different modes of operation.
0: Count Down Timer. An interrupt is generated only once after a time period of
1...63 ms.
1: Periodic Timer. An interrupt is periodically generated every 1 ... 63 ms (see CNT).
CNT ... Timer Counter
0: Timer off.
1 ... 63:Timer period = 1 ... 63 ms
Data Sheet
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Detailed Register Description
By writing ’0’ to CNT the timer is immediately stopped. A value different from that
determines the time period after which an interrupt will be generated.
If the timer is already started with a certain CNT value and is written again before an
interrupt has been released, the timer will be reset to the new value and restarted again.
An interrupt is indicated to the host in AUXI.TIN2.
Note: Reading back this value delivers back the current counter value which may differ
from the programmed value if the counter is running.
Data Sheet
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Electrical Characteristics
5
Electrical Characteristics
5.1
Absolute Maximum Ratings
Parameter
Symbol
TA
TSTG
VS
Ambient temperature under bias
Storage temperature
Input/output voltage on any pin
with respect to ground
Maximum voltage on any pin
with respect to ground
Vmax
Limit Values
Unit
min.
max.
0
+70
°C
– 55
150
°C
– 0.3
5.25
V
5.5
V
Note: Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
The supply voltage must show a monotonic rise.
Data Sheet
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Electrical Characteristics
5.2
DC Characteristics
VDD/VSS = 3.3 V ± 5%; TA = 0 to 70 °C
Parameter
Symbol
Limit Values
min.
typ.
Unit Test Condition
max.
H-input level
(except pin SR1/2)
VIH
2.0
5.5
V
L-input level
(except pin SR1/2)
VIL
– 0.3
0.8
V
H-output level
(except pin XTAL2, SX1/
2)
VOH
2.4
L-output level
(except pin XTAL2, SX1/
2)
VOL
Input leakage current
Output leakage current
(all pins except
SX1/2,SR1/2,XTAL1/2,
AUX7/6)
ILI
ILO
Input leakage current
Output leakage current
(AUX7/6)
ILI
ILO
V
(all others)
0.45
V
IOL = 6 mA
(DU, DD, C768)
IOL = 4.5 mA (ACL,
AUX7, AUX6, AD0-7)
IOL = 2 mA (all others)
50
50
±1
±1
mA
mA
0V< VIN<VDD
0V< VOUT<VDD
200
200
mA
mA
0V< VIN<VDD
0V< VOUT<VDD
(only if AUX7/6 is
input or output/opendrain; not relevant if
output/push-pull)
Power supply currentPower Down
- Clocks Off
IPD1
300
mA
- Clocks On
IPD2
3
mA
Power supply current
- S operational (96 kHz)
IOP1
30
mA
- B1= 00H, B2= FFH, D= 0 IOP2
25
mA
Data Sheet
IOH = - 4.5 mA (AD0-7)
IOH = - 400 mA
173
Inputs at VSS / VDD
No output loads
except SX1,2 (50 W)
2003-01-30
ISAC-SX TE
PSB 3186
Electrical Characteristics
5.3
Capacitances
TA = 25 °C, VDD = 3.3 V ± 5% VSSA = 0 V, VSS = 0 V, fc = 1 MHz, unmeasured pins
grounded.
Parameter
Symbol
Limit Values Unit
min.
Remarks
max.
Input Capacitance
I/O Capacitance
CIN
CI/O
7
7
pF
pF
All pins except SX1,2 and
XTAL1,2
Output Capacitance
against VSS
COUT
10
pF
pins SX1,2
Data Sheet
174
2003-01-30
ISAC-SX TE
PSB 3186
Electrical Characteristics
5.4
Oscillator Specification
Recommended Oscillator Circuits
33 pF
41
XTAL1
CL
External
Oscillator
Signal
41
XTAL1
7.68 MHz
33 pF
42
N.C.
XTAL2
42
XTAL2
CL
Crystal Oscillator Mode
Driving from External Source
ITS09659
Figure 70
Oscillator Circuits
Parameter
Symbol
Limit Values
Unit
Frequency
f
7.680
MHz
max. 100
ppm
max. 40
pF
Frequency calibration tolerance
Load capacitance
CL
Oscillator mode
fundamental
Note: It is important to note that the load capacitance depends on the recommendation
of the crystal specification. Typical values are 22 ... 33 pF.
XTAL1 Clock Characteristics (external oscillator input)
Parameter
Duty cycle
Data Sheet
Limit Values
min.
max.
1:2
2:1
175
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ISAC-SX TE
PSB 3186
Electrical Characteristics
5.5
AC Characteristics
TA = 0 to 70 °C, VDD = 3.3 V ± 5%
Inputs are driven to 2.4 V for a logical "1" and to 0.45 V for a logical "0". Timing
measurements are made at 2.0 V for a logical "1" and 0.8 V for a logical "0". The AC
testing input/output waveforms are shown in figure 71.
2.4
2.0
2.0
Device
Under
Test
Test Points
0.8
0.8
C Load = 100 pF
0.45
ITS09660
Figure 71
Data Sheet
Input/Output Waveform for AC Tests
176
2003-01-30
ISAC-SX TE
PSB 3186
Electrical Characteristics
5.6
IOM-2 Interface Timing
Data is transmitted with the rising edge of DCL and sampled with its falling edge. Below
figure shows double clock mode timing (the length of a timeslot is 2 DCL cycles),
however, the timing parameters are valid both in single and double clock mode.
Figure 72
IOM-2 Timing (TE mode)
Parameter
Symbol
Limit Values
min.
Unit
max.
60
ns
IOM output data delay
tIOD
IOM input data setup
tIIS
4
ns
IOM input data hold
tIIH
3
ns
FSC strobe delay (see note)
tFSD
-135
Strobe signal delay
BCL / FSC delay
Data Sheet
15
ns
tSDD
50
ns
tBCD
30
ns
177
2003-01-30
ISAC-SX TE
PSB 3186
Electrical Characteristics
Note: Min. value in synchronous state, max. value in non-synchronous state. This
results in a phase shift of FSC when the S-Bus gets activated, this is the FSC
signal is shifted by 135 ns.
DCL Clock Output Characteristics
2.3 V
Figure 73
Definition of Clock Period and Width
Symbol
Limit Values
Unit
Test Condition
osc ± 100 ppm
min.
typ.
max.
tP
585
651
717
ns
tWH
260
325
391
ns
tWL
260
325
391
ns
osc ± 100 ppm
osc ± 100 ppm
DCL Clock Input Characteristics
Parameter
Duty cycle
Limit Values
min.
max.
40
60
Unit
%
Note: In normal mode the IOM clocks are output only. If the transceiver is disabled
(DIS_TR = 1) the IOM clocks become input and e.g. the HDLC controller can still
operate via the IOM-2 interface.
Data Sheet
178
2003-01-30
ISAC-SX TE
PSB 3186
Electrical Characteristics
5.7
Microcontroller Interface Timing
5.7.1
Serial Control Interface (SCI) Timing
t1
t4
t2
t3
t5
CS
SCL
t6
t7
t9
SDR
t8
SDX
Figure 74
SCI Interface
Parameter
SCI Interface
Symbol
SCL cycle time
t1
200
ns
SCL high time
t2
100
ns
SCL low time
t3
100
ns
CS setup time
t4
2
ns
CS hold time
t5
10
ns
SDR setup time
t6
10
ns
SDR hold time
t7
6
ns
SDX data out delay
t8
30
ns
CS high to SDX tristate
t9
40
ns
Data Sheet
Limit Values
min.
179
Unit
max.
2003-01-30
ISAC-SX TE
PSB 3186
Electrical Characteristics
5.7.2
Parallel Microcontroller Interface Timing
Siemens/Intel Bus Mode
The data read and write timing is the same for multiplexed and non multiplexed bus
operation (Figure 75 and Figure 76). Figure 77 shows the corresponding address
timing in multiplexed mode and Figure 78 in non multiplexed mode.
Figure 75
Microprocessor Read Cycle
Figure 76
Microprocessor Write Cycle
Figure 77
Multiplexed Address Timing
Data Sheet
180
2003-01-30
ISAC-SX TE
PSB 3186
Electrical Characteristics
WR x CS or
RD X CS
t AS
A0-A7
t AH
Address
ITT09661
Figure 78
Non-Multiplexed Address Timing
Motorola Bus Mode
The Motorola Bus is non multiplexed. The data timing is shown in Figure 79 (read) and
Figure 80 (write). The corresponding address timing (for both read and write) is shown
in Figure 81.
D0-7
Figure 79
Microprocessor Read Timing
Data Sheet
181
2003-01-30
ISAC-SX TE
PSB 3186
Electrical Characteristics
R/W
t DSD
t RWD
t WW
t WI
CS x DS
t WD
t DW
D0-7
D0
- D7
Data
ITT09679
Figure 80
Data Sheet
Microprocessor Write Cycle
182
2003-01-30
ISAC-SX TE
PSB 3186
Electrical Characteristics
CS x DS
t AS
t AH
AD0
- AD7
A0-7
ITT09662
Figure 81
Non-Multiplexed Address Timing
Microprocessor Interface Timing
Parameter
Symbol
Limit Values
min.
Unit
max.
ALE pulse width
tAA
20
ns
Address setup time to ALE
tAL
5
ns
Address hold time from ALE
tLA
3
ns
Address latch setup time to WR, RD
tALS
10
ns
Address setup time
tAS
10
ns
Address hold time
tAH
3
ns
ALE guard time
tAD
15
ns
DS delay after R/W setup
tDSD
3
ns
RD pulse width
tRR
100
ns
Data output delay from RD
tRD
80
ns
Data float from RD
tDF
25
ns
RD control interval
tRI
70
ns
W pulse width
tWW
10
ns
Data setup time to W x CS
tDW
10
ns
Data hold time W x CS
tWD
2
ns
W control interval
tWI
70
ns
R/W hold from CS x DS inactive
tRWD
2
ns
Data Sheet
183
2003-01-30
ISAC-SX TE
PSB 3186
Electrical Characteristics
5.8
Reset
Parameter
Symbol
Limit Values
Unit
Test Conditions
ms
Power On/Power Down
to Power Up (Standby)
min.
Length of active
low state
tRES
4
2 x DCL
clock cycles
During Power Up (Standby)
t RES
RES
21150_26
Figure 82
Data Sheet
Reset Signal RES
184
2003-01-30
ISAC-SX TE
PSB 3186
Electrical Characteristics
5.9
S-Transceiver
Parameter
Symbol
Limit Values
min.
typ.
Unit Test Condition
max.
VDD= 3.3 V ± 5%; VSS= 0 V; TA = 0 to 70 °C
Absolute value of output VX
pulse amplitude
| VSX2 – VSX1 |
1.17
V
RL = ¥
Transmitter output
current
IX
26
mA
RL = 5.6 W
Transmitter output
impedance (SX1,2)
ZX
10
kW
0
W
Inactive or during
binary one;
during binary zero
RL = 50 W
30
kW
VDD = 3.3 V
Receiver Input
impedance (SR1,2)
Data Sheet
ZR
185
2003-01-30
ISAC-SX TE
PSB 3186
Electrical Characteristics
5.10
Recommended Transformer Specification
Parameter
Symbol
Limit Values
min.
Transformer ratio
Main inductance
Leakage inductance
typ.
max.
1:1
L
25
mH
20
mH
LL
Capacitance between C
primary and secondary
side
Copper resistance
Unit Test Condition
R
1.7
2.0
no DC current,
10 kHz
2.5 mA DC current,
10 kHz
6
µH
TE mode, 10 kHz
80
pF
1 kHz
2.3
W
Note: In TE mode, at the pulse shape measurement with a load of 400 W (e.g. K 1403
approval test “Pulse shape”) overshots might occur with a leakage inductance
greater than 6 mH.
Data Sheet
186
2003-01-30
ISAC-SX TE
PSB 3186
Electrical Characteristics
5.11
Line Overload Protection
The maximum input current for the S-transceiver lines (under overvoltage conditions) is
given as a function of the width of a rectangular input current pulse. The desctruction
limits are shown in Figure 83.
i
[A]
3
2
1.5
1
0.80
0.65
0.52
0.40
t
-8
10
-7
10
-6
10
-5
10
-4
10
-3
10
-2
10
[s]
21150_35
Figure 83
Maximum Line Input Current
Data Sheet
187
2003-01-30
ISAC-SX TE
PSB 3186
Electrical Characteristics
5.12
EMC / ESD Aspects
To improve performance with respect to EMC and ESD requirements it is recommended
to provide additional capacitors in the middle tap of the transformers (see Figure 84
below). The values for C1 and C2 should be in the range 1 ... 10 nF. They can be located
either on the chip side of the transformer (option 1) or on the S bus side (option 2), but
not on both sides.
This improves EMC immunity acording to EN55024 which is mandatory since 2001-0701.
Note: The figure does not show any other components required for protection circuit in
receive and transmit direction as this is not affected by including C1 and C2.
Test Setup
Transmitter (NT)
Ck1
Cp1
Cp2
SR1
AC
C1
C1
SR2
Ck2
C1 and C2 are also possible
at this position (option 2)
Ck3
C2
C1, C2 required to supress
common mode signals (option 1)
AC
C2
SX1
SX2
Ck4
AC
Cp3
Cp4
Test Generator
0.15MHz - 80MHz carrier
with 1 kHz, 80% amplitude
modulated signal
Figure 84
Data Sheet
21150_34
Couple Capacity: Ck1 ¹ Ck2 ¹ Ck3 ¹ Ck4
Parasitic Capacity: Cp1 ¹ Cp2 ¹ Cp3 ¹ Cp4
Transmitter (TE)
Transformer Circuitry
188
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ISAC-SX TE
PSB 3186
Package Outlines
6
Package Outlines
P-MQFP-64-1
(Plastic Metric Quad Flat Package)
GPM05220
You can find all of the current packages, types of packing, and others on the Infineon Internet Page
“Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
189
2003-01-30
ISAC-SX TE
PSB 3186
Package Outlines
P-TQFP-64-1
(Plastic Thin Quad Flat Package)
GPM05613
You can find all of the current packages, types of packing, and others on the Infineon Internet Page
“Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
190
2003-01-30
ISAC-SX TE
PSB 3186
Appendix
7
Appendix
D-channel HDLC, C/I-channel Handler
Name
7
6
5
4
3
2
1
0
ADDR R/WRES
RFIFOD
D-Channel Receive FIFO
00H1FH
R
XFIFOD
D-Channel Transmit FIFO
00H1FH
W
ISTAD
RME
RPF
RFO
XPR
XMR
XDU
0
0
20H
R 10H
MASKD
RME
RPF
RFO
XPR
XMR
XDU
1
1
20H
W FFH
0
21H
R 40H
STARD
XDOV XFW
0
0
RACI
0
XACI
CMDRD
RMC RRES
0
STI
XTF
0
XME XRES
21H
W 00H
0
RAC
DIM2 DIM1 DIM0
22H
R/W C0H
23H
R/W 00H
24H
R/W 00H
MODED MDS2 MDS1 MDS0
EXMD1
XFBS
TIMR1
RFBS
SRA XCRC RCRC
CNT
0
ITF
VALUE
SAP1
SAPI1
0
MHA
25H
W FCH
SAP2
SAPI2
0
MLA
26H
W FCH
RBC0
26H
R 00H
RBC8
27H
R 00H
RBCLD
RBC7
RBCHD
0
0
0
OV RBC11
TEI1
TEI1
EA1
27H
W FFH
TEI2
TEI2
EA2
28H
W FFH
RSTAD
TMD
VFR
RDO
CRC
RAB
SA1
SA0
C/R
TA
28H
R 0FH
0
0
0
0
0
0
0
TLP
29H
R/W 00H
reserved
2A-2DH
CIR0
CODR0
CIC0
CIX0
CODX0
TBA2 TBA1 TBA0
Data Sheet
191
CIC1
S/G
BAS
2EH
R F3H
BAC
2EH W
FEH
2003-01-30
ISAC-SX TE
PSB 3186
Appendix
CIR1
CODR1
CICW CI1E
2FH
R
FEH
CIX1
CODX1
CICW CI1E
2FH
W
FEH
Transceiver
NAME
7
6
TR_
CONF0
DIS_
TR
TR_
CONF1
0
TR_
CONF2
DIS_
TX
TR_STA
5
0
4
EN_
ICV
RINF
2
1
0
ADDR R/WRES
0
0
0
EXLP
LDD
30H
R/W 01H
0
0
x
x
x
31H
R/W
0
RLP
0
0
0
0
32H
R/W 80H
SLIP
ICV
0
FSYN
0
LD
33H
R 00H
RPLL_ EN_
ADJ SFSC
PDS
3
reserved
34H
0
0
SQR11SQR12SQR13SQR14
35H
R 40H
0
0
SQX11 SQX12SQX13 SQX14
35H
W 4FH
SQRR2 SQR21SQR22SQR23SQR24SQR31SQR32SQR33SQR34
36H
R 00H
36H
W
37H
R 00H
37H
W
SQRR1
MSYN MFEN
SQXR1
0
MFEN
reserved
SQRR3 SQR41SQR42SQR43SQR44SQR51SQR52SQR53SQR54
reserved
ISTATR
0
x
x
x
LD
RIC
SQC
SQW
38H
R 00H
MASKTR
1
1
1
1
LD
RIC
SQC
SQW
39H
R/W FFH
reserved
ACFG2
0
0
0
0
ACL
reserved
Data Sheet
192
3AH3BH
LED
0
0
3CH R/W 00H
3DH3FH
2003-01-30
ISAC-SX TE
PSB 3186
Appendix
IOM Handler (Timeslot , Data Port Selection,
CDA Data and CDA Control Register)
Name
7
6
5
4
3
2
1
0
ADDR R/WRES
CDA10
Controller Data Access Register (CH10)
40H
R/W FFH
CDA11
Controller Data Access Register (CH11)
41H
R/W FFH
CDA20
Controller Data Access Register (CH20)
42H
R/W FFH
CDA21
Controller Data Access Register (CH21)
43H
R/W FFH
CDA_ DPS
TSDP10
0
0
TSS
44H
R/W 00H
CDA_ DPS
TSDP11
0
0
TSS
45H
R/W 01H
CDA_ DPS
TSDP20
0
0
TSS
46H
R/W 80H
CDA_ DPS
TSDP21
0
0
TSS
47H
R/W 81H
reserved
48H4BH
TR_
TSDP_
BC1
DPS
0
0
TSS
4CH R/W
TR_
TSDP_
BC2
DPS
0
0
TSS
4DH R/W
CDA1_
CR
0
0
EN_ EN_I1 EN_I0 EN_O1EN_O0 SWAP
TBM
4EH R/W 00H
CDA2_
CR
0
0
EN_ EN_I1 EN_I0 EN_O1EN_O0 SWAP
TBM
4FH R/W 00H
Data Sheet
193
2003-01-30
ISAC-SX TE
PSB 3186
Appendix
IOM Handler (Control Registers, Synchronous Transfer
Interrupt Control), MONITOR Handler
Name
TR_CR
7
6
5
4
3
2
1
0
ADDR R/WRES
EN_
D
EN_
B2R
EN_
B1R
EN_
B2X
EN_
B1X
CS2-0
50H R/W
(CI_CS=0)
TRC_CR
0
0
0
0
0
CS2-0
50H R/W
(CI_CS=1)
reserved
51H
reserved
52H
DCI_CR
DPS_ EN_
D_
D_
D_
CI1 EN_D EN_B2 EN_B1
(CI_CS=0) CI1
DCIC_CR
0
CS2-0
53H R/W
0
0
0
0
CS2-0
53H R/W
EN_
MON
0
0
0
CS2-0
54H R/W
(CI_CS=1)
MON_CR DPS
SDS_CR ENS_ ENS_ ENS_
TSS TSS+1 TSS+3
55H R/W 00H
TSS
reserved
IOM_CR
STI
ASTI
MSTI
SPU
0
STOV STOV STOV STOV
21
20
11
10
0
0
0
0
STOV STOV STOV STOV
21
20
11
10
SDS_
CONF
0
MCDA
MCDA21
Data Sheet
CI_CS TIC_
DIS
0
0
0
MCDA20
56H
EN_ CLKM DIS_
BCL
OD
DIS_
IOM
57H R/W 08H
STI
21
STI
20
STI
11
STI
10
58H
R 00H
ACK
21
ACK
20
ACK
11
ACK
10
58H
W 00H
STI
21
STI
20
STI
11
STI
10
59H R/W FFH
0
SDS_
BCL
5AH R/W 00H
DIOM_ DIOM_
INV SDS
MCDA11
194
MCDA10
5BH
R FFH
2003-01-30
ISAC-SX TE
PSB 3186
Appendix
MOR
MONITOR Receive Data
5CH
R FFH
MOX
MONITOR Transmit Data
5CH
W FFH
R 00H
MOSR
MDR
MER
MDA
MAB
0
0
0
0
5DH
MOCR
MRE
MRC
MIE
MXC
0
0
0
0
5EH R/W 00H
MSTA
0
0
0
0
0
MAC
0
TOUT
5FH
R 00H
MCONF
0
0
0
0
0
0
0
TOUT
5FH
W 00H
Interrupt, General Configuration Registers
NAME
7
6
5
4
3
2
1
0
ADDR R/WRES
ISTA
0
0
ST
CIC
AUX TRAN MOS
ICD
60H
R 00H
MASK
1
1
ST
CIC
AUX TRAN MOS
ICD
60H
W FFH
AUXI
0
0
EAW WOV
TIN2
TIN1
0
0
61H
R 00H
AUXM
1
1
EAW WOV
TIN2
TIN1
1
1
61H
W FFH
MODE1
0
0
0
62H
R/W 00H
MODE2
0
0
0
63H
R/W 00H
ID
0
0
64H
R 01H
SRES
RES_
CI
0
64H
W 00H
TIMR2
TMD
0
65H
R/W 00H
WTC1 WTC2 CFS RSS2 RSS1
0
INT_
POL
0
PPSDX
DESIGN
0
RES_ RES_ RES_ RES_ RES_
MON DCH IOM
TR RSTO
CNT
reserved
Data Sheet
0
195
66H6FH
2003-01-30
ISAC-SX TE
PSB 3186
Index
A
Absolute maximum ratings 172
AC characteristics 176
ACFG2 register 149
ACKxy bits 159
ACL bit 149
Activation 67
Activation indication - pin ACL 38
Activation LED 38
Activation/deactivation of IOM-2 interface
100
Appendix 191
Applications 18
Architecture 25
ASTI register 159
AUX bit 165
AUXI register 166
AUXM register 167
B
BAC bit 141
BAS bit 140
Bus operation modes 31
C
C/I channel 93
C/R bit 138
Capacitances 174
CDA_TSDPxy registers 151
CDAx_CR register 152
CDAxy registers 151
CFS bit 167
CI_CS bit 157
CI1E bit 142
CIC bit 165
CIC1/0 bits 140
CICW bit 142
CIR0 register 140
CIR1 register 142
CIX0 register 141
CIX1 register 142
CLKM bit 157
Data Sheet
Clock generation 54
CMDR register 131
CNT bits 135, 170
CODR0 bits 140
CODR1 bits 142
CODX0 bits 141
CODX1 bits 142
Control of layer-1 57
Controller data access 72
CRC bit 138
D
D_EN_B2/1 bits 154
D_EN_D bit 154
DC characteristics 173
D-channel access control
S-bus priority mechanism 97
TIC bus 95
DCI_CR register 154
DCIC_CR register 155
Deactivation 67
Delay between IOM-2 and S 44
DESIGN bits 169
Device architecture 25
DIM2-0 bits 132
DIOM_INV bit 160
DIOM_SDS bit 160
Direct address mode 32
DIS_IOM bit 157
DIS_OD bit 157
DIS_TR bit 144
DIS_TX bit 145
DPS bit 151, 156
DPS_CI1 bit 154
E
EA1 bit 137
EA2 bit 138
EAW bit 166
Electrical characteristics 172
EN_B2/1R bits 153
EN_B2/1X bits 153
EN_BCL bit 157
196
2003-01-30
ISAC-SX TE
PSB 3186
Index
EN_CI1 bit 154
EN_D bit 153
EN_I0 bit 152
EN_I1 bit 152
EN_ICV bit 144
EN_MON bit 156
EN_O0 bit 152
EN_O1 bit 152
EN_SFSC bit 145
EN_TBM bit 152
ENS_TSSx bits 156
Exchange awake 35
EXLP bit 144
EXMD1 register 134
Extended transparent mode 117
External reset input 35
F
Features 15
FSYN bit 146
Functional blocks 25
H
HDLC controllers
Access to IOM channels 117
Data reception 104
Data transmission 112
Extended transparent mode 117
Interrupts 118
Receive frame structure 109
Test functions 119
Transmit frame structure 116
I
ICD bit 165
ICV bit 146
ID register 169
Indirect address mode 32
INT_POL bit 169
Interrupt structure 33
IOM_CR register 157
IOM-2 68
Frame structure (TE) 69
Data Sheet
Handler 70
Interface Timing 177
Monitor channel 84
ISTA register 165
ISTAD register 128
ISTATR register 148
ITF bit 134
J
Jitter 55
L
LD bit 146, 148
LDD bit 144
LED bit 149
LED output 38
Level detection 50
Logic symbol 17
Looping data 73
M
MAB bit 162
MAC bit 163
MASK register 166
MASKD register 130
MASKTR register 149
MCDA register 161
MCDAxy bits 161
MCONF register 164
MDA bit 162
MDR bit 162
MDS2-0 bits 132
MER bit 162
MFEN bit 147
MHA bit 135
Microcontroller interface timing 179
Microcontroller interfaces 27
MIE bit 162
MLA bit 136
MOCR register 162
MODE1 register 167
MODE2 register 169
MODED register 132
197
2003-01-30
ISAC-SX TE
PSB 3186
Index
MON_CR register 156
Monitor channel
Error treatment 89
Handshake procedure 86
Interrupt logic 93
Master device 91
Slave device 91
Time-out procedure 92
Monitoring data 77
MOR register 161
MOS bit 165
MOSR register 162
MOX register 162
MRC bit 162
MRE bit 162
MSTA register 163
MSTI register 160
MSYN bit 147
Multiframing 42
MXC bit 162
RDO bit 138
Receive PLL 55
Register description 121
RES_xxx bits 170
Reset generation 34
Reset source selection 34
Reset timing 184
RFBS bits 134
RFIFOD register 128
RFO bit 128
RIC bit 148
RINF bit 146
RLP bit 145
RMC bit 131
RME bit 128
RPF bit 128
RPLL_ADJ bit 145
RRES bit 131
RSS2/1 bits 167
RSTAD register 138
O
S
Oscillator 175
Oscillator clock output 56
OV bit 137
Overview 12
S/G bit 140
S/T-Interface 39
Circuitry 47
Coding 40
Delay compensation 50
External protection circuitry 47
Multiframing 42
Receiver characteristics 46
Transceiver enable/disable 51
Transmitter characteristics 45
SA1/0 bits 138
SAP1 register 135
SAP2 register 136
S-bus priority mechanism 97
SCI - serial control interface 28
SCI interface timing 179
SDS 82
SDS_BCL bit 160
SDS_CONF register 160
SDSx_CR registers 156
Serial data strobe 82
P
Package Outlines 189
Parallel microcontroller interface 31
PDS bit 145
Pin configuration 19
PPSDX bit 169
R
RAB bit 138
RAC bit 132
RACI bit 130
RBC11-8 bits 137
RBC7-0 bits 136
RBCHD register 137
RBCLD register 136
RCRC bit 134
Data Sheet
198
2003-01-30
ISAC-SX TE
PSB 3186
Index
Shifting data 73
SLIP bit 146
Software reset 35
SPU bit 157
SQC bit 148
SQR1-4 bits 147
SQR21-24 bits 148
SQR31-34 bits 148
SQR41-44 bits 148
SQR51-54 bits 148
SQRR1 register 147
SQRR2 register 148
SQRR3 register 148
SQW bit 148
SQX1-4 bits 147
SQXR1 register 147
SRA bit 134
SRES register 170
ST bit 165
STARD register 130
State machine TE mode 59
STI bit 131
STI register 159
STIxy bits 159, 160
Stop/Go bit 140
STOVxy bits 159, 160
Strobed data clock 82
Subscriber awake 35
SWAP bit 152
Synchronous transfer 78
T
TA bit 138
TBA2-0 bits 141
TEI1 register 137
TEI2 register 138
Test functions 52
Test signals 120
TIC bus 95
TIC_DIS bit 157
Timer 35
Timer 1 36
Timer 2 37
Data Sheet
TIMR1 register 135
TIMR2 register 170
TIN2/1 bits 166
TLP bit 140
TMD bit 170
TMD register 140
TOUT bit 163, 164
TR_CONF0 register 144
TR_CONF1 register 145
TR_CONF2 register 145
TR_CR register 153
TR_STA register 146
TR_TSDP_BC1/2 registers 151
TRAN bit 165
Transceiver enable/disable 51
Transformer specification 186
TRC_CR register 154
TSS bits 151, 156
Typical applications 18
V
VALUE bits 135
VFR bit 138
W
Watchdog timer 35
WOV bit 166
WTC1/2 bits 167
X
XACI bit 130
XCRC bit 134
XDOV bit 130
XDU bit 128
XFBS bit 134
XFIFOD register 128
XFW bit 130
XME bit 131
XMR bit 128
XPR bit 128
XRES bit 131
XTF bit 131
199
2003-01-30
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