ETC W83C42P

W83C42
KEYBOARD CONTROLLER
GENERAL DESCRIPTION
The W83C42 keyboard controller is programmed to support the IBM compatible personal computer
keyboard serial interface. The keyboard controller receives serial data from the keyboard, checks the
parity of the data, translates the scan code, and presents the data to the system as a byte of data in
its output buffer. The controller will interrupt the system when data is placed in its output buffer. The
byte of data will be sent to the keyboard serially with an odd parity bit automatically inserted. The
keyboard is required to acknowledge all data transmissions. No transmission should be sent to the
keyboard until acknowledge is received for the previous byte sent.
Winbond Electronics Corporation has developed a fast keyboard controller and BIOS to improve the
performance of IBM PC/AT 386DX/SX and 486DX/SX machines and their compatibles. Hardwire
methodology is used in this keyboard controller instead of software implementation, as in the
traditional 8042 keyboard BIOS. This enables the keyboard controller to respond instantly to all
commands sent from the keyboard to the CPU BIOS.
The keyboard controller enables popular programs such as AutoCAD, Microsoft Windows 3.1,
NOVELL, and other programs to run much faster.
FEATURES
•
Supports IBM PC/AT 386DX/SX and 486 DX/SX system designs
•
Runs much faster than traditional keyboard controllers
•
Host interface compatible with traditional keyboard controller
•
6MHz~12MHz operating frequency
•
Communicates with keyboard directly
•
High-reliability CMOS technology
•
Available packages: 40-pin DIP, 44-pin PLCC
IBM and PC/AT are registered trademarks of International Business Machines Corporation. 386 and 486 are trademarks of Intel
Corporation. AutoCAD is a registered trademark of Autodesk, Inc. Microsoft is a registered trademark and Windows is a trademark of
Microsoft Corporation. NOVELL is a registered trademark of Novell, Inc.
-1-
Publication Release Date: July 1994
Revision A3
W83C42
PIN CONFIGURATION
40-pin DIP
T0
1
40
VDD
XIN
2
39
T1
XOUT
3
38
P27 (KDAT)
RESET
VDD
4
37
P26 (KCLK)
5
36
P25 (IEMP)
CS
VSS
6
35
P24 (INT)
7
34
P17 (KINH)
RD
8
33
P16 (DISP)
A2
9
32
P15 (JUMP)
WR
10
31
P14 (RAM)
NC
11
30
P13
D0
12
29
P12
P11
44-pin PLCC
V
D
D
CS
V SS
RD
A2
WR
NC
NC
D0
D1
D2
D3
D1
13
28
D2
14
27
P10
D3
15
26
NC
D4
16
25
VDD
D5
17
24
P23
D6
18
23
P22
D7
19
22
P21 (GA20)
VSS
20
21
P20 (RC)
/
R
E
S
E
T
5
7 6
8
9
10
11
12
13
14
15
16
17 18 19
X
X
O
U
T
X
I
N
T
0
N
C
V
D
D
4
3
2
1
44
X
X
X
X
X
X
X
42 41 40 39
38
37
36
35
34
33
32
31
30
25 26 27 28 29
43
X
X
X
X
X
X
X
X
14
X
X
X
X
X
X
X
X
15
D
4
P
2
5
X
X
X
P
2
6
X
X
X
P
2
7
X
X
X
T
1
20 21
D
5
-2-
X
D
6
X
D
7
22 23 24
X
V
S
S
X
N
C
X
P
2
0
X
X
P
2
1
X
P
2
2
X
P
2
3
X
V
D
D
P24
P17
P16
P15
P14
NC
P13
P12
P11
P10
NC
W83C42
PIN DESCRIPTION
PIN NO.
(40-pin DIP)
PIN NO.
(44-pin PLCC)
I/O
NAME
1
2
I
T0
K/B Clock Input
2
3
I
XIN
Crystal Clock I/P
3
4
O
XOUT
Crystal Clock O/P
4
5
I
RESET
5
6
-
VDD
Optional +5V Power Supply
6
7
I
CS
Chip Select
7
8
-
VSS
Optional Ground Power
8
9
I
RD
I/O Read
9
10
I
A2
Connect to Address A2
10
11
I
WR
I/O Write
11, 26
1, 12, 13,
23, 29, 34
-
NC
Reserved
12, 13, 14,
15, 16, 17,
18, 19
14, 15, 16,
17, 18, 19,
20, 21
I/O
D0-D7
20
22
-
VSS
Ground Power Supply
21
24
O
P20
Bit 0 of Port 2 (RCB: System Reset)
22
25
O
P21
Bit 1 of Port 2 (GA20: GATE A20)
23
26
I/O
P22
Bit 2 of Port 2
24
27
I/O
P23
Bit 3 of Port 2
25
28
-
VDD
Optional +5V Power Supply
27
30
I/O
P10
Bit 0 of Port 1
28
31
I/O
P11
Bit 1 of Port 1
29
32
I/O
P12
Bit 2 of Port 1
30
33
I/O
P13
Bit 3 of Port 1
31
35
I
P14
Bit 4 of Port 1 (RAM Jumper Select)
32
36
I
P15
Bit 5 of Port 1 (JUMP)
33
37
I
P16
Bit 6 of Port 1 (Display Select)
34
38
I
P17
Bit 7 of Port 1 (K/B Inhibit Switch)
-3-
FUNCTION
Chip Reset
Data Bus D0 - D7
Publication Release Date: July 1994
Revision A3
W83C42
Pin Description, continued
PIN NO.
(40-pin DIP)
PIN NO.
(44-pin PLCC)
I/O
NAME
FUNCTION
35
39
O
P24
Bit 4 of Port 2 (OBF O/P Interrupt)
36
40
O
P25
Bit 5 of Port 2 (I/P Buffer Empty)
37
41
O
P26
Bit 6 of Port 2 (K/B Clock O/P)
38
42
O
P27
Bit 7 of Port 2 (K/B Data O/P)
39
43
I
T1
K/B Data Input
40
44
-
VDD
+5V Power Supply
BLOCK DIAGRAM
TRANSMIT
CONTROL
T0
T1
SCAN
CODE
ROM
RECEIVE
CONTROL
XOUT
XIN
HARDWIRE
CONTROL &
SELECT
LOGIC
WR
RD
CS
A2
TRANSMIT
REGISTER
STATUS
REGISTER
RESET
R64
D0- D7
DATA
BUFFER
REGISTER
W60
W64
R60
STATUS
BUFFER
REGISTER
INPUT &
OUTPUT
PORT
INPUT
BUFFER
REGISTER
INTERFACE
P10
P11
P12
P13
P14 (RAM Select)
P15 (Manufacture Mode)
P16 (Display)
P17 (KBNH)
OUTPUT
BUFFER
REGISTER
OUTPUT
PORT
INTERFACE
-4-
P20 (RC)
P21 (Gate A20)
P22
P23
P24
P25
P26 (Keyboard Clock)
P27 (Keyboard Data)
W83C42
AC TIMING
NO.
DESCRIPTION
MIN.
MAX.
UNIT
T1
Address Setup Time from WR
0
nS
T2
Address Setup Time from RD
0
nS
T3
WR Strobe Width
20
nS
T4
RD Strobe Width
20
nS
T5
Address Hold Time from WR
0
nS
T6
Address Hold Time from RD
0
nS
T7
Data Setup Time
50
nS
T8
Data Hold Time
0
nS
T9
Gate Delay Time from WR
10
nS
T10
RD to Drive Data Delay
T11
RD to Floating Data Delay
T12
Data Valid After Clock Falling (SEND)
T13
K/B Clock Period
20
µS
T14
K/B Clock Pulse Width
10
µS
T15
Data Valid Before Clock Falling (RECEIVE)
4
µS
T16
K/B ACK After Finish Receiving
20
µS
T17
RC Fast Reset Pulse Delay (8 MHz)
2
T18
RC Pulse Width (8 MHz)
6
T19
Transmit Timeout
T20
Data Valid Hold Time
0
T21
XIN/XOUT Period ( 6-12 MHz )
83
0
20
nS
20
nS
4
µS
3
µS
2
-5-
µS
mS
µS
167
nS
Publication Release Date: July 1994
Revision A3
W83C42
TIMING WAVEFORMS
Write Cycle Timing
A2, CS
T1
T5
T3
WR
ACTIVE
T8
T7
DATA IN
D0 - D7
T9
A20
OUTPUT PORT
T17
FAST RESET PULS RC
FE COMMAND
Read Cycle Timing
A2, CS
AEN
T2
T6
T4
RD
ACTIVE
T10
D0 - D7
T11
DATA OUT
-6-
T18
W83C42
Send Data to K/B
CLOCK
( KCLK )
T12
SERIAL DATA
( KDAT )
T13
T14
START
D0
D1
D2
D3
T16
D4
D5
D6
D7
P
STOP
T19
Receive Data from K/B
CLOCK
( KCLK )
T15
SERIAL DATA
( T1 )
START
D0
T13
T14
D1
D2
D3
D4
D5
D6
D7
P
STOP
T20
XIN/XOUT Clock
XIN CLK
T21
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNIT
-0 to +85
°C
Storage Temperature
-65 to +150
°C
Supply Voltage to Ground Potential
-0.3 to +7.0
V
Applied Input/Output Voltage
-0.3 to +7.0
V
50
mW
Ambient Operating Temperature
Power Dissipation
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
-7-
Publication Release Date: July 1994
Revision A3
W83C42
ELECTRICAL CHARACTERISTICS & CAPACITANCE
(Ta = 0° C to +70° C, VDD = +5V ±5%)
SYMBOL
VDD
DESCRIPTION
Power Supply
MIN.
TYP.
MAX.
UNIT
4.75
5.0
5.25
V
0
25
70
V
TA
Operating Temperature
VIH
High Level Voltage for TTL
Min. I/P
2.0
VDD
V
VIL
Low Level Voltage for TTL
Max. I/P
-0.3
0.8
V
VOH
High Level Voltage for TTL
Min. O/P
VDD -0.5
VOL
Low Level Voltage for TTL
Max. O/P
RIP
Min. I/P Resist
10K
ILI
I/P Leakage Current
-10
10
µA
ILO
O/P Leakage Current
-10
10
µA
IOL
O/P Sink Current
4
CL
O/P Load Capacity
15
V
0.5
V
Ω
mA
50
pF
STATUS REGISTER
The status register is an 8-bit read-only register at I/O address hex 64 that holds information about the
state of the keyboard controller and interface. It may be read at any time.
BIT
BIT DESCRIPTION
FUNCTION
0
Output Buffer Full
0: Output Buffer Empty
1: Output Buffer Full
1
Input Buffer Full
0: Input Buffer Empty
1: Input Buffer Full
2
System Flag
This bit may be set to 0 or 1 by writing to the system flag bit in
the command byte of the keyboard controller. It is set to 0 after
a power-on reset
3
Command/data
0: Data Byte
1: Command Byte
4
Inhibit Switch
0: Keyboard is Inhibited
1: Keyboard is Not Inhibited
5
Transmit Time Out
0: No Transmit Time Out Error
1: Transmit Time Out Error
-8-
W83C42
Status Register, continued
BIT
BIT DESCRIPTION
FUNCTION
6
Receive Time Out
0: No Receive Time Out Error
1: Receive Time Out Error
7
Parity Error
0: Odd Parity (No Error)
1: Even Parity (Error)
OUTPUT BUFFER
The output buffer is an 8-bit read-only register at I/O address hex 60. The keyboard controller uses
the output buffer to send the scan code received from the keyboard and data bytes required by
command to the system. The output buffer should be read only when the output buffer full bit in the
register is 1.
INPUT BUFFER
The input buffer is an 8-bit write-only register at I/O address hex 60 or 64. Writing to address hex 60
sets a flag that indicates a data write; writing to address hex 64 sets a flag that indicates a command
write. Data written to I/O address hex 60 are sent to the keyboard (unless the keyboard controller is
expecting a data byte) following the controller's input buffer only if the input buffer full bit in the status
register is set to 0.
I/O PORTS
The keyboard controller has two 8-bit I/O ports and two test inputs. One of the ports is assigned for
input and the other for output. The controller uses the test inputs to read the state of the keyboard's
clock line and data line.
The following figures show bit definitions for the input, output, and test-input ports.
(A) Input Port Definitions
BIT
FUNCTION
0
Undefined
1
Undefined
2
Undefined
3
Undefined
4
RAM on System Board
0: Disable 2nd 256 KB of System Board RAM
1: Enable 2nd 256 KB of System Board RAM
5
Manufacturing Jumper Installed
0: Manufacturing Jumper
1: Jumper Not Installed
-9-
Publication Release Date: July 1994
Revision A3
W83C42
Input Port Definitions, continued
BIT
FUNCTION
6
Display Type Switch
0: Primary Display Attached to Color/graphics
0: Primary Display Attached to Monochrome
7
Keyboard Inhibit Switch
0: Keyboard Inhibited
1: Keyboard Not Inhibited
(B) Output Port Definitions
BIT
FUNCTION
0
System Reset
1
Gate A20
2
Undefined
3
Undefined
4
Output Buffer Full
5
Input Buffer Empty
6
Keyboard Clock (Output)
7
Keyboard Data (Output)
(C) Test-Input Definitions
BIT
FUNCTION
0
Keyboard Clock (Input)
1
Keyboard Data (Input)
- 10 -
W83C42
COMMANDS (I/O ADDRESS HEX 64)
COMMAND
FUNCTION
20
Read Command Byte of Keyboard Controller
60
Write Command Byte of Keyboard Controller
AA
BIT
BIT DEFINITIONS
7
Reserved
6
IBM PC Compatible Mode
5
IBM PC Mode
4
Disable Keyboard
3
Inhibit Override
2
System Flag
1
Reserved
0
Enable Output Buffer Full Interrupt
Self-test
BIT
BIT DEFINITIONS
00
No Error Detected
01
K/B Clock Line is Stuck Low
02
K/B Clock Line is Stuck High
03
K/B Data Line is Stuck Low
04
K/B Data Line is Stuck High
AB
Interface Test
AD
Disable Keyboard Feature
AE
Enable Keyboard Interface
C0
Read Input Port
D0
Read Output Port
D1
Write Output Port
E0
Read Test Inputs
F0-FF
Pulse Output Port
- 11 -
Publication Release Date: July 1994
Revision A3
W83C42
APPLICATION CIRCUIT
Asynchronous
RESETB
SA2
IORB
IOWB
D0 - D7
2
X1
3
X2
4
1
39
9
6
5
8
10
RESET
T0
T1
A2
CS
VDD
RD
WR
12
13
14
15
16
17
18
19
D0
D1
D2
D3
D4
D5
D6
D7
7
VSS
VDD
25
P10
P11
P12
P13
P14
P15
P16
P17
27
28
29
30
31
32
33
34
P20
P21
P22
P23
P24/OB
P25/BF
P26/KCLK
P27/KDAT
21
22
23
24
35
36
37
38
NC
11
RAM SELECT JUMPER
MANUFACTURING MODE JUMPER
DISPLAY TYPE SWITCH
RCB
GATE A20
KEYBOARD INHIBIT SWITCH
KEYBOARD INTERRUPT
KEYBOARD CLOCK
KEYBOARD DATA
VD
D
U?A
1
U?A
2
1
2
VCC
74ALS04
KEYBOARD CLOCK
7407
U?B
3
4
7407
- 12 -
KEYBOARD DATA
W83C42
Application Circuit, continued
Synchronous
PCLK
2
3
RESETB
SA2
IORB
IOWB
D0 - D7
4
1
39
9
6
8
10
12
13
14
15
16
17
18
19
X1
X2
RESET
T0
T1
A2
CS
RD
WR
D0
D1
D2
D3
D4
D5
D6
D7
P10
P11
P12
P13
P14/RAM
P15/MOD
P16/DIS
P17/INH
27
28
29
30
31
32
33
34
P20/RCB
P21/A20
P22
P23
P24
P25
P26/KCLK
P27/KDAT
21
22
23
24
35
36
37
38
RAM SELECT JUMPER
MANFACTURING MODE JUMPER
DISPLAY TYPE SWITCH
RCB
GATE A20
KEYBOARD INHIBIT SWITCH
KEYBOARD INTERRUPT
KEYBOARD CLOCK
KEYBOARD DATA
VDD
U?A
1
U?A
2
1
74ALS04
2
VDD
KEYBOARD CLOCK
7407
U?B
3
4
KEYBOARD DATA
7407
- 13 -
Publication Release Date: July 1994
Revision A3
W83C42
PACKAGE DIMENSIONS
40-pin PDIP
Symbol
A
A1
A2
B
B1
c
D
E
E1
e1
L
D
40
21
1
0.25
0.150
0.155
0.160
3.81
3.94
4.06
0.016
0.018
0.022
0.41
0.46
0.56
0.048
0.050
0.054
1.22
1.27
1.37
0.008
0.010
0.014
0.20
0.25
0.36
2.055
2.070
52.20
52.58
0.590
0.600
0.610
14.99
15.24
15.49
0.540
0.545
0.550
13.72
13.84
13.97
0.090
0.100
0.110
2.29
2.54
2.79
0.120
0.130
0.140
3.05
3.30
3.56
15
0
0.670
16.00
16.51
17.02
0
0.630
0.650
15
0.090
2.29
Notes:
20
1. Dimensions D Max & S include mold flash or
tie bar burrs.
2. Dimension E1 does not include interlead flash.
3. Dimensions D & E1 include
. mold mismatch and
are determined at the mold parting line.
4. Dimension B1 does not include dambar
protrusion/intrusion.
5. Controlling dimension: Inches.
6. General appearance spec. should be based on
final visual inspection spec.
E
S
c
2
AA
1
A
Base Plane
Seating Plane
L
B
5.33
0.210
eA
S
1
Dimension in mm
Min. Nom. Max.
0.010
a
E
Dimension in inch
Min. Nom. Max.
e1
eA
a
B1
44-pin PLCC
HD
D
6
1
44
40
7
Symbol
39
E
E
E H
17
G
29
18
28
L
c
A A
e
b
b1
Dimension in mm
Min. Nom. Max.
0.185
4.70
0.020
0.51
0.145 0.150 0.155
3.68
3.81
3.94
0.026 0.028 0.032
0.66
0.71
0.81
0.016 0.018 0.022
0.41
0.46
0.56
0.008 0.010 0.014
0.20
0.25
0.36
0.648 0.653 0.658 16.46 16.59 16.71
0.648 0.653 0.658 16.46 16.59 16.71
0.050
BSC
1.27
0.590 0.610 0.630 14.99 15.49 16.00
0.680 0.690 0.700 17.27 17.53 17.78
0.680 0.690 0.700 17.27 17.53 17.78
0.090 0.100 0.110
2.29
2.54
0.004
1. Dimensions D & E do not include interlead
flash.
2. Dimension b1 does not include dambar
protrusion/intrusion
3. Controlling dimension: Inches
4. General appearance spec. should be based
on final visual inspection spec.
1
A
y
GD
- 14 -
BSC
0.590 0.610 0.630 14.99 15.49 16.00
Notes:
2
Seating Plane
A
A1
A2
b1
b
c
D
E
e
GD
GE
HD
HE
L
y
Dimension in inch
Min. Nom. Max.
2.79
0.10
W83C42
Headquarters
Winbond Electronics (H.K.) Ltd.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792646
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-7197006
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27516023
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2730 Orchard Parkway, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
- 15 -
Publication Release Date: July 1994
Revision A3