WED3DG6466V-D1 512MB- 64Mx64 SDRAM, UNBUFFERED FEATURES DESCRIPTION n PC100 and PC133 compatible The WED3DG6466V is a 64Mx64 synchronous DRAM module which consists of eight 64Mx8 SDRAM components in TSOP- 11 package, and one 2K EEPROM in an 8- pin TSSOP package for Serial Presence Detect which are mounted on a 144 Pin SODIMM multilayer FR4 Substrate. n Burst Mode Operation n Auto and Self Refresh capability n LVTTL compatible inputs and outputs n Serial Presence Detect with EEPROM n Fully synchronous: All signals are registered on the positive edge of the system clock n Programmable Burst Lengths: 1, 2, 4, 8 or Full Page n 3.3 volt 6 0.3v Power Supply n 144 Pin SO-DIMM JEDEC PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE) NC NC NC NC A0 A12 BA0-1 DQ0-63 CLK0,CLK1 CKE0 CS0 RAS CAS WE DQM0-7 VDD VSS SDA SCL DNU NC NC CS0\ NC NC NC NC NC NC PIN NAMES Address input (Multiplexed) Select Bank Data Input/Output Clock input Clock Enable input Chip select Input Row Address Strobe Column Address Strobe Write Enable DQM Power Supply (3.3V) Ground Serial data I/O Serial clock Do not use No Connect ** These pins should be NC in the system which does not support SPD. White Electronic Designs Corp reserves the right to change products or specifications without notice. June 2003 Rev. 0 ECO #16372 1 White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com WED3DG6466V-D1 FUNCTIONAL BLOCK DIAGRAM WE CS0 DQM0 DQM4 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 S WE S DQM DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D0 DQM1 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 WE D4 I/O 7 DQM5 DQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 S WE S DQM DQ40 DQ41 DQ42 D1 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 WE D5 DQM6 DQM2 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 S WE S DQM DQ48 DQ49 DQ50 D2 DQ51 DQ52 DQ53 DQ54 DQ55 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 WE D6 DQM7 DQM3 DQM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S WE S DQM DQ56 DQ57 DQ58 D3 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 WE D7 NOTE: DQ wiring may differ than described in this drawing, however DQ/DQMB/CKE/S relationships must be maintained as shown. *CLOCK WIRING RAS CAS CKE0 BA0-BA1 A0-A12 CLOCK INPUT RAS: SDRAM D0-D7 CAS: SDRAM D0-D7 CKE: SDRAM D0-D7 SDRAMS *CLK0 4 SDRAMS *CLK1 4 SDRAMS BA0-BA1: SDRAM D0-D7 A0-A12: SDRAM D0-D7 SERIAL PD SDA SCL VDD D0-D7 VSS D0-D7 A0 A1 A2 White Electronic Designs Corp reserves the right to change products or specifications without notice. White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com 2 June 2003 Rev. 0 ECO #16372 WED3DG6466V-D1 ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current Symbol VIN, Vout VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 8 50 Units V V °C W mA Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (Voltage Referenced to: VSS = 0V, TA = 0°C to +70°C) Parameter Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Symbol VDD VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -10 Typ Max Unit 3.3 3.6 V 3.0 VDDQ+0.3 V 0.8 V V 0.4 V 10 µA Note 1 2 IOH= -2mA IOL= -2mA 3 Note: 1. VIH (max)= 5.6V AC. The overshoot voltage duration is £ 3ns. 2. VIL (min)= -2.0V AC. The undershoot voltage duration is £ 3ns. 3. Any input 0V £ VIN £ VDDQ Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (TA = 23°C, f = 1MHz, VDD = 3.3V, VREF=1.4V 6200mV) Parameter Input Capacitance (A0-A12) Input Capacitance (RAS,CAS,WE) Input Capacitance (CKE0) Input Capacitance (CLK0) Input Capacitance (CS0) Input Capacitance (DQM0-DQM7) Input Capacitance (BA0-BA1) Data input/output capacitance (DQ0-DQ63) Data input/output capacitance (CB0-7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 Cout Cout 1 Min - Max 15 15 15 20 15 15 15 22 22 Unit pF pF pF pF pF pF pF pF pF White Electronic Designs Corp reserves the right to change products or specifications without notice. June 2003 Rev. 0 ECO #16372 3 White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com WED3DG6466V-D1 OPERATING CURRENT CHARACTERISTICS (VCC = 3.3V, TA = 0°C to +70°C) Parameter Operating Current (One bank active) Symbol ICC1 Precharge Standby Current in Power Down Mode ICC2P ICC2PS Icc2N Precharge Standby Current in Non-Power Down Mode Active standby current in power-down mode Active standby current in non power-down mode Icc2NS ICC3P ICC3PS ICC3N ICC3NS Operating current (Burst mode) ICC4 Refresh current Self refresh current ICC5 ICC6 Conditions Burst Length = 1 tRC ³ tRC(min) IOL = 0mA CKE £ VIL(max), tCC = 10ns CKE & CLK £ VIL(max), tCC = ¥ CKE ³ VIH(min), CS ³ VIH(min), tcc = 10ns Input signals are charged one time during 20 CKE ³ VIH(min), CLK £ VIL(max), tcc = ¥ Input signals are stable CKE ³ VIL(max), tCC = 10ns CKE & CLK £ VIL(max), tcc = ¥ CKE ³ VIH(min), CS ³ VIH(min), tcc = 10ns Input signals are changed one time during 20ns CKE ³ VIH(min), CLK £ VIL(max), tcc = ¥ input signals are stable Io = mA Page burst 4 Banks activated tCCD = 2CLK tRC ³ tRC(min) CKE £ 0.2V Version 133 100 1,530 1,440 50 50 mA 370 mA 200 80 80 mA 550 mA 410 mA 2,070 3,150 Units Note mA 1 60 1,620 mA 1 2,880 mA mA 2 Notes: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS (VIH/VIL = VDDQ/VssQ) White Electronic Designs Corp reserves the right to change products or specifications without notice. White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com 4 June 2003 Rev. 0 ECO #16372 WED3DG6466V-D1 Part number WED3DG6466V10D1 WED3DG6466V7D1 WED3DG6466V75D1 Speed 100MHz 133MHz 133MHz Cas Latency CL=2 CL=2 CL=3 Note: For industrial temperature range product, add an "I" to the end of the part number. PACKAGE DIMENSIONS .150 ALL DIMENSIONS ARE IN INCHES White Electronic Designs Corp reserves the right to change products or specifications without notice. June 2003 Rev. 0 ECO #16372 5 White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com WED3DG6466V-D1 REV. DATE REQUESTED BY DETAILS A 10-21-02 PAUL MARIEN CREATED 0 6-19-03 PAUL MARIEN -Add PC100 & PC133 to features on page 1 -Add disclaimer note to the bottom of each page -Add industrial temp range note to order info page 5 White Electronic Designs Corp reserves the right to change products or specifications without notice. White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com 6 June 2003 Rev. 0 ECO #16372 DATASHEET APPROVALS ECO# 16372 NEW REV 0 EDI PART NO. WED3DG6466V-D1 APPROVAL: INITIAL DATE DATE 6/19/03 CORRECTION ON PAGES JUAN GUZMAN ■ MUKESH TRIVEDI ■ PAUL MARIEN ■ LARRY WINROTH 6/19/03 6/19/03 6/19/03 DAVE KELLY MARK DOWNEY DAVE HARRISON ■ 6/19/03 TONY LEE BOB KHEDERIAN LUIS ESTELLA YES WILL THIS DATASHEET GO ON THE WEB? NO ■ IS THIS A NEW DATASHEET? ■ WILL THIS DATASHEET REPLACE AN EXISTING DATASHEET THAT’S ALREADY ON THE WEB? ■ LINE:________ FAMILY:____________ PROD.TYPE:________ ORG:___________ DENSITY:________ SPEED:__________ PKG:____________ VOLTAGE:________ IF YES, WHAT DATASHEET IS IT REPLACING? WHAT SECTION SHOULD THIS DATASHEET BE PLACED IN ON THE WEB? MEMORIES MODULES SDRAM AFTER REVIEWING OR MAKING CORRECTIONS ON THE DATASHEET (S) PLEASE SIGN-OFF ON THIS SHEET AND ,MAKE YOUR CORRECTIONS –ON THE ORIGINAL COPY(S). AFTER REVIEWING THE DATA SHEET, TEST ENGINEERING WILL COMPLETE THE SECTION BELOW. TEST PROGRAM CHANGE REQUIRED: 6/19/03 ■ YES:_________NO____________DATE:___________ TEST ENGINEER SIGNATURE___________________ IF YES, DO NOT RELEASE DATA SHEET UNTIL TEST PROGRAM CHANGE IS COMPLETED. TEST PROGRAM CHANGE COMPLETION DATE:__________ TEST PROGRAM NAME AND REVISION_________________ TEST ENGINEER SIGNATURE__________________________ FO-00342R1.DOC ECO# 14942 SHEET 1 OF 1