Revised April 2005 74VHCT373A Octal D-Type Latch with 3-STATE Outputs General Description Features The VHCT373A is an advanced high speed CMOS octal Dtype latch with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input (OE). The latches appear transparent to data when latch enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. When the OE input is HIGH, the eight outputs are in a high impedance state. Protection circuits ensure that 0V to 7V can be applied to the input and output (Note 1) pins without regard to the supply voltage. This device can be used to interface 3V to 5V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. ■ High speed: tPD 7.7 ns (typ) at TA ■ High Noise Immunity: VIH 2.0V, VIL 25qC 0.8V ■ Power Down Protection is provided on all inputs and outputs ■ Low Power Dissipation: ICC 4 PA (max) @ TA 25qC ■ Pin and Function Compatible with 74HCT373 Note 1: Outputs in OFF-State. Ordering Code: Order Number Package Number 74VHCT373AM 74VHCT373ASJ 74VHCT373AMTC 74VHCT373AN Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC20 N20A 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code Pb-Free package per JEDEC J-STD-020B. Logic Symbol Connection Diagram IEEE/IEC © 2005 Fairchild Semiconductor Corporation DS500027 www.fairchildsemi.com 74VHCT373A Octal D-Type Latch with 3-STATE Outputs July 1997 74VHCT373A Pin Descriptions Pin Names Truth Table Description Inputs Outputs D0–D7 Data Inputs LE OE Dn On LE Latch Enable Input X H X Z OE Output Enable Input H L L L O0–O7 3-STATE Outputs H L H H L L X O0 H L Z X O0 HIGH Voltage Level LOW Voltage Level High Impedance Immaterial Previous O0 before HIGH-to-LOW transition of Latch Enable Functional Description to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. The VHCT373A contains eight D-type latches with 3STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH- Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions (Note 6) 0.5V to 7.0V 0.5V to 7.0V Supply Voltage (VCC) DC Input Voltage (VIN) 4.5V to 5.5V Supply Voltage (VCC) DC Output Voltage (VOUT) 0V to 5.5V Input Voltage (VIN) 0.5V to VCC 0.5V 0.5V to 7.0V 20 mA (Note 3) (Note 4) Input Diode Current (IIK) Output Voltage (VOUT) Output Diode Current (IOK) (Note 3) 0V to VCC (Note 4) 0V to 5.5V 40qC to 85qC Operating Temperature (TOPR) r20 mA r25 mA r75 mA 65qC to 150qC (Note 5) DC Output Current (IOUT) DC VCC/GND Current (ICC) Storage Temperature (TSTG) Input Rise and Fall Time (tr, tf) VCC Lead Temperature (TL) 260qC (Soldering, 10 seconds) 5.0 r 0.5V 0 ns/V a 20 ns/V Note 2: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. Note 3: HIGH or LOW state. IOUT absolute maximum rating must be observed. OV. Note 4: When outputs are in OFF-State or when VCC Note 5: VOUT GND, V OUT ! VCC (Outputs Active). Note 6: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VCC (V) Parameter HIGH Level Input Voltage VIL LOW Level Input Voltage VOH HIGH Level Output Voltage VOL LOW Level IOZ 3-STATE Output TA Min TA Max 40qC to 85qC Min 4.5 2.0 2.0 5.5 2.0 2.0 Max 4.5 0.8 0.8 0.8 0.8 4.5 4.40 4.5 3.94 4.50 0.0 4.5 Units Conditions V 5.5 4.5 Output Voltage 25qC Typ V 4.40 V 3.80 V 0.1 0.1 V 0.36 0.44 V VIN VIH 50 PA IOH or VIL IOH 8 mA VIH 50 PA VIN IOL or VIL IOL VIN 8 mA VIH or VIL 5.5 r0.25 r2.5 PA 0 5.5 r0.1 r1.0 PA VIN 5.5V or GND OFF-State Current VOUT VCC or GND IIN Input Leakage Current ICC Quiescent Supply Current 5.5 4.0 40.0 PA VIN VCC or GND ICCT Maximum ICC/Input 5.5 1.35 1.50 mA VIN 3.4V Other Inputs IOFF Output Leakage Current 0.5 0.0 0.5 PA VOUT VCC or GND 5.5V (Power Down State) Noise Characteristics Symbol VOLP TA 25qC VCC (V) Typ Limits Quiet Output Maximum Dynamic VOL 5.0 1.2 1.6 V CL 50 pF Quiet Output Minimum Dynamic VOL 5.0 1.2 1.6 V CL 50 pF Minimum HIGH Level Dynamic Input Voltage 5.0 2.0 V CL 50 pF Maximum LOW Level Dynamic Input Voltage 5.0 0.8 V CL 50 pF Parameter Units Conditions (Note 7) VOLV (Note 7) VIHD (Note 7) VILD (Note 7) Note 7: Parameter guaranteed by design. 3 www.fairchildsemi.com 74VHCT373A Absolute Maximum Ratings(Note 2) 74VHCT373A AC Electrical Characteristics Symbol Parameter tPLH Propagation Delay Time tPHL (LE to On) tPLH Propagation Delay Time tPHL (D to On) tPZL 3-STATE Output Enable Time tPZH tPLZ VCC (V) 5.0 r 0.5 5.0 r 0.5 5.0 r 0.5 3-STATE Output Disable Time 5.0 r 0.5 Output to Output Skew 5.0 r 0.5 25qC TA Min TA 40qC to 85qC Typ Max Min Max 7.7 12.3 1.0 13.5 8.5 13.3 1.0 14.5 5.1 8.5 1.0 9.5 5.9 9.5 1.0 10.5 6.3 10.9 1.0 12.5 7.1 11.9 1.0 13.5 8.8 11.2 1.0 12.0 Units Conditions CL 15 pF CL 50 pF CL 15 pF CL 50 pF 1 k: CL 15 pF CL 50 pF 1 k: CL 50 pF ns ns ns ns RL RL tPHZ tOSLH 1.0 1.0 10 10 (Note 8) tOSHL CIN Input Capacitance 4 pF VCC Open COUT Output Capacitance 6 pF VCC 5.0V CPD Power Dissipation Capacitance 25 pF (Note 9) Note 8: Parameter guaranteed by design. tOSLH |tPLH max tPLH min |; tOSHL |tPHL max tPHL min| Note 9: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) C PD • VCC • fIN ICC/8 (per F/F). AC Operating Requirements Symbol Parameter TA VCC (V) Min 25qC Typ TA Max 40qC to 85qC Min Max Units tW(H) Minimum Pulse Width (LE) 5.0 r 0.5 6.5 8.5 ns tS Minimum Set-Up Time 5.0 r 0.5 1.5 1.5 ns tH Minimum Hold Time 5.0 r 0.5 3.5 3.5 ns www.fairchildsemi.com 4 74VHCT373A Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com 74VHCT373A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 74VHCT373A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com 74VHCT373A Octal D-Type Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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