Features • High-performance, Low-power AVR® 8-bit Microcontroller • Advanced RISC Architecture • • • • • • • – 130 Powerful Instructions – Most Single-clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier Nonvolatile Program and Data Memories – 8K Bytes of In-System Self-Programmable Flash Endurance: 10,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation – 512 Bytes EEPROM Endurance: 100,000 Write/Erase Cycles – 1K Byte Internal SRAM – Programming Lock for Software Security Peripheral Features – Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Three PWM Channels – 8-channel ADC in TQFP and MLF package Six Channels 10-bit Accuracy Two Channels 8-bit Accuracy – 6-channel ADC in PDIP package Four Channels 10-bit Accuracy Two Channels 8-bit Accuracy – Byte-oriented Two-wire Serial Interface – Programmable Serial USART – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby I/O and Packages – 23 Programmable I/O Lines – 28-lead PDIP, 32-lead TQFP, and 32-pad MLF Operating Voltages – 2.7 - 5.5V (ATmega8L) – 4.5 - 5.5V (ATmega8) Speed Grades – 0 - 8 MHz (ATmega8L) – 0 - 16 MHz (ATmega8) Power Consumption at 4 Mhz, 3V, 25°C – Active: 3.6 mA – Idle Mode: 1.0 mA – Power-down Mode: 0.5 µA 8-bit with 8K Bytes In-System Programmable Flash ATmega8 ATmega8L Summary Rev. 2486LS–AVR–10/03 Note: This is a summary document. A complete document is available on our Web site at www.atmel.com. Pin Configurations PDIP (RESET) PC6 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (XCK/T0) PD4 VCC GND (XTAL1/TOSC1) PB6 (XTAL2/TOSC2) PB7 (T1) PD5 (AIN0) PD6 (AIN1) PD7 (ICP1) PB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3) PC2 (ADC2) PC1 (ADC1) PC0 (ADC0) GND AREF AVCC PB5 (SCK) PB4 (MISO) PB3 (MOSI/OC2) PB2 (SS/OC1B) PB1 (OC1A) 32 31 30 29 28 27 26 25 PD2 (INT0) PD1 (TXD) PD0 (RXD) PC6 (RESET) PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3) PC2 (ADC2) TQFP Top View 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 PC1 (ADC1) PC0 (ADC0) ADC7 GND AREF ADC6 AVCC PB5 (SCK) 24 23 22 21 20 19 18 17 PC1 (ADC1) PC0 (ADC0) ADC7 GND AREF ADC6 AVCC PB5 (SCK) (T1) PD5 (AIN0) PD6 (AIN1) PD7 (ICP1) PB0 (OC1A) PB1 (SS/OC1B) PB2 (MOSI/OC2) PB3 (MISO) PB4 9 10 11 12 13 14 15 16 (INT1) PD3 (XCK/T0) PD4 GND VCC GND VCC (XTAL1/TOSC1) PB6 (XTAL2/TOSC2) PB7 32 31 30 29 28 27 26 25 PD2 (INT0) PD1 (TXD) PD0 (RXD) PC6 (RESET) PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3) PC2 (ADC2) MLF Top View 1 2 3 4 5 6 7 8 (T1) PD5 (AIN0) PD6 (AIN1) PD7 (ICP1) PB0 (OC1A) PB1 (SS/OC1B) PB2 (MOSI/OC2) PB3 (MISO) PB4 9 10 11 12 13 14 15 16 (INT1) PD3 (XCK/T0) PD4 GND VCC GND VCC (XTAL1/TOSC1) PB6 (XTAL2/TOSC2) PB7 2 ATmega8(L) 2486LS–AVR–10/03 ATmega8(L) Overview The ATmega8 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 1. Block Diagram XTAL1 RESET PC0 - PC6 PB0 - PB7 VCC XTAL2 GND PORTC DRIVERS/BUFFERS PORTB DRIVERS/BUFFERS PORTC DIGITAL INTERFACE PORTB DIGITAL INTERFACE MUX & ADC ADC INTERFACE PROGRAM COUNTER STACK POINTER PROGRAM FLASH SRAM TWI AGND AREF INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS TIMERS/ COUNTERS OSCILLATOR INTERNAL OSCILLATOR WATCHDOG TIMER OSCILLATOR X INSTRUCTION DECODER Y MCU CTRL. & TIMING Z CONTROL LINES ALU INTERRUPT UNIT AVR CPU STATUS REGISTER EEPROM PROGRAMMING LOGIC SPI USART + - COMP. INTERFACE PORTD DIGITAL INTERFACE PORTD DRIVERS/BUFFERS PD0 - PD7 3 2486LS–AVR–10/03 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega8 provides the following features: 8K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes of EEPROM, 1K byte of SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, a 6-channel ADC (eight channels in TQFP and MLF packages) where four (six) channels have 10-bit accuracy and two channels have 8-bit accuracy, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next Interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The Flash Program memory can be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash Section will continue to run while the Application Flash Section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System SelfProgrammable Flash on a monolithic chip, the Atmel ATmega8 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. The ATmega8 AVR is supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kits. Disclaimer 4 Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. ATmega8(L) 2486LS–AVR–10/03 ATmega8(L) Pin Descriptions VCC Digital supply voltage. GND Ground. Port B (PB7..PB0) XTAL1/ XTAL2/TOSC1/TOSC2 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator amplifier. If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is used as TOSC2..1 input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set. The various special features of Port B are elaborated in “Alternate Functions of Port B” on page 56 and “System Clock and Clock Options” on page 23. Port C (PC5..PC0) Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. PC6/RESET If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6 differ from those of the other pins of Port C. If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page 36. Shorter pulses are not guaranteed to generate a Reset. The various special features of Port C are elaborated on page 59. Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega8 as listed on page 61. RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page 36. Shorter pulses are not guaranteed to generate a reset. 5 2486LS–AVR–10/03 AVCC AVCC is the supply voltage pin for the A/D Converter, Port C (3..0), and ADC (7..6). It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. Note that Port C (5..4) use digital supply voltage, VCC. AREF AREF is the analog reference pin for the A/D Converter. ADC7..6 (TQFP and MLF Package Only) In the TQFP and MLF package, ADC7..6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels. 6 ATmega8(L) 2486LS–AVR–10/03 ATmega8(L) Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x3F (0x5F) SREG I T H S V N Z C Page 9 0x3E (0x5E) SPH – – – – – SP10 SP9 SP8 11 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 11 0x3C (0x5C) Reserved 47, 65 0x3B (0x5B) GICR INT1 INT0 – – – – IVSEL IVCE 0x3A (0x5A) GIFR INTF1 INTF0 – – – – – – 66 0x39 (0x59) TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 – TOIE0 70, 100, 120 0x38 (0x58) TIFR OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 – TOV0 71, 101, 120 0x37 (0x57) SPMCR SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN 209 0x36 (0x56) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 167 0x35 (0x55) MCUCR SE SM2 SM1 SM0 ISC11 ISC10 ISC01 ISC00 31, 64 0x34 (0x54) MCUCSR – – – – WDRF BORF EXTRF PORF 39 0x33 (0x53) TCCR0 – – – – – CS02 CS01 CS00 70 0x32 (0x52) TCNT0 Timer/Counter0 (8 Bits) 0x31 (0x51) OSCCAL Oscillator Calibration Register 0x30 (0x50) SFIOR – – – – 70 29 ACME PUD PSR2 PSR10 56, 73, 121, 189 95 0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 0x2E (0x4E) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 0x2D (0x4D) TCNT1H Timer/Counter1 – Counter Register High byte 98 99 0x2C (0x4C) TCNT1L Timer/Counter1 – Counter Register Low byte 99 0x2B (0x4B) OCR1AH Timer/Counter1 – Output Compare Register A High byte 99 0x2A (0x4A) OCR1AL Timer/Counter1 – Output Compare Register A Low byte 99 0x29 (0x49) OCR1BH Timer/Counter1 – Output Compare Register B High byte 99 0x28 (0x48) OCR1BL Timer/Counter1 – Output Compare Register B Low byte 99 0x27 (0x47) ICR1H Timer/Counter1 – Input Capture Register High byte 100 0x26 (0x46) ICR1L 0x25 (0x45) TCCR2 Timer/Counter1 – Input Capture Register Low byte 0x24 (0x44) TCNT2 Timer/Counter2 (8 Bits) 117 0x23 (0x43) OCR2 Timer/Counter2 Output Compare Register 117 FOC2 WGM20 COM21 COM20 WGM21 100 CS22 CS21 CS20 0x22 (0x42) ASSR – – – – AS2 TCN2UB OCR2UB TCR2UB 0x21 (0x41) WDTCR – – – WDCE WDE WDP2 WDP1 WDP0 UBRRH URSEL – – – 0x20(1) (0x40)(1) UBRR[11:8] 115 117 41 154 UCSRC URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL 152 0x1F (0x3F) EEARH – – – – – – – EEAR8 18 0x1E (0x3E) EEARL EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 0x1D (0x3D) EEDR EEPROM Data Register 18 18 – – – – EERIE EEMWE EEWE EERE PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 63 DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 63 0x16 (0x36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 63 0x15 (0x35) PORTC – PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 63 0x14 (0x34) DDRC – DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 63 0x1C (0x3C) EECR 0x1B (0x3B) Reserved 0x1A (0x3A) Reserved 0x19 (0x39) Reserved 0x18 (0x38) 0x17 (0x37) 18 0x13 (0x33) PINC – PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 63 0x12 (0x32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 63 0x11 (0x31) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 63 0x10 (0x30) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 0x0F (0x2F) SPDR SPI Data Register 63 128 0x0E (0x2E) SPSR SPIF WCOL – – – – – SPI2X 0x0D (0x2D) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 0x0C (0x2C) UDR 0x0B (0x2B) UCSRA RXC TXC UDRE FE DOR PE U2X MPCM 150 0x0A (0x2A) UCSRB RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 151 0x09 (0x29) UBRRL 0x08 (0x28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 190 0x07 (0x27) ADMUX REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 201 0x06 (0x26) ADCSRA ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 203 0x05 (0x25) ADCH ADC Data Register High byte 204 0x04 (0x24) ADCL ADC Data Register Low byte 204 0x03 (0x23) TWDR 0x02 (0x22) TWAR USART I/O Data Register 154 Two-wire Serial Interface Data Register TWA5 TWA4 TWA3 TWA2 126 149 USART Baud Rate Register Low byte TWA6 128 169 TWA1 TWA0 TWGCE 170 7 2486LS–AVR–10/03 Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x01 (0x21) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 169 0x00 (0x20) TWBR Notes: 8 Two-wire Serial Interface Bit Rate Register 167 1. Refer to the USART description for details on how to access UBRRH and UCSRC. 2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only. ATmega8(L) 2486LS–AVR–10/03 ATmega8(L) Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1 COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1 1 INC Rd Increment Rd ← Rd + 1 Z,N,V DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1 SER Rd Set Register Rd ← 0xFF None 1 MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2 MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2 MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2 FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << Z,C 2 FMULS Rd, Rr Fractional Multiply Signed Z,C 2 FMULSU Rd, Rr Fractional Multiply Signed with Unsigned 1 R1:R0 ← (Rd x Rr) << 1 R1:R0 ← (Rd x Rr) << 1 Z,C 2 Relative Jump PC ← PC + k + 1 None 2 Indirect Jump to (Z) PC ← Z None 2 Relative Subroutine Call PC ← PC + k + 1 None 3 ICALL Indirect Call to (Z) PC ← Z None 3 RET Subroutine Return PC ← STACK None 4 RETI Interrupt Return PC ← STACK I None BRANCH INSTRUCTIONS RJMP k IJMP RCALL k 4 CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3 1 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None Mnemonics Operands Description Operation Flags 1/2 #Clocks 9 2486LS–AVR–10/03 Instruction Set Summary (Continued) BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers Rd ← Rr None 1 MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1 LDI Rd, K Load Immediate Rd ← K None 1 LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2 LD Rd, Y Load Indirect Rd ← (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd ← (k) None 2 ST X, Rr Store Indirect (X) ← Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2 ST Y, Rr Store Indirect (Y) ← Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2 2 ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2 ST Z, Rr Store Indirect (Z) ← Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2 STS k, Rr Store Direct to SRAM (k) ← Rr None 2 Load Program Memory R0 ← (Z) None 3 LPM Rd, Z Load Program Memory Rd ← (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3 Store Program Memory (Z) ← R1:R0 None - In Port Rd ← P None 1 LPM SPM IN Rd, P OUT P, Rr Out Port P ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1 BSET s Flag Set SREG(s) ← 1 SREG(s) 1 BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) ← T None 1 SEC Set Carry C←1 C 1 CLC Clear Carry C←0 C 1 SEN Set Negative Flag N←1 N 1 CLN Clear Negative Flag N←0 N 1 SEZ Set Zero Flag Z←1 Z 1 CLZ Clear Zero Flag Z←0 Z 1 SEI Global Interrupt Enable I←1 I 1 CLI Global Interrupt Disable I← 0 I 1 SES Set Signed Test Flag S←1 S 1 CLS Clear Signed Test Flag S←0 S 1 SEV Set Twos Complement Overflow. V←1 V 1 CLV Clear Twos Complement Overflow V←0 V 1 SET Set T in SREG T←1 T 1 Mnemonics 10 Operands Description Operation Flags #Clocks ATmega8(L) 2486LS–AVR–10/03 ATmega8(L) Instruction Set Summary (Continued) CLT Clear T in SREG T←0 T 1 SEH Set Half Carry Flag in SREG H←1 H 1 CLH Clear Half Carry Flag in SREG H←0 H 1 MCU CONTROL INSTRUCTIONS NOP SLEEP WDR No Operation Sleep Watchdog Reset (see specific descr. for Sleep function) (see specific descr. for WDR/timer) None None None 1 1 1 11 2486LS–AVR–10/03 Ordering Information Speed (MHz) Power Supply Ordering Code Package Operation Range 8 2.7 - 5.5 ATmega8L-8AC ATmega8L-8PC ATmega8L-8MC 32A 28P3 32M1-A Commercial (0°C to 70°C) ATmega8L-8AI ATmega8L-8PI ATmega8L-8MI 32A 28P3 32M1-A Industrial (-40°C to 85°C) ATmega8-16AC ATmega8-16PC ATmega8-16MC 32A 28P3 32M1-A Commercial (0°C to 70°C) ATmega8-16AI ATmega8-16PI ATmega8-16MI 32A 28P3 32M1-A Industrial (-40°C to 85°C) 16 Note: 12 4.5 - 5.5 This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. ATmega8(L) 2486LS–AVR–10/03 ATmega8(L) Package Type 32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP) 28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Micro Lead Frame Package (MLF) 13 2486LS–AVR–10/03 Packaging Information 32A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 8.75 9.00 9.25 D1 6.90 7.00 7.10 E 8.75 9.00 9.25 E1 6.90 7.00 7.10 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 e NOTE Note 2 Note 2 0.80 TYP 10/5/2001 R 14 2325 Orchard Parkway San Jose, CA 95131 TITLE 32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. REV. 32A B ATmega8(L) 2486LS–AVR–10/03 ATmega8(L) 28P3 D PIN 1 E1 A SEATING PLANE L B2 B1 A1 B (4 PLACES) 0º ~ 15º REF e E C COMMON DIMENSIONS (Unit of Measure = mm) eB Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). MIN NOM MAX – – 4.5724 A1 0.508 – – D 34.544 – 34.798 E 7.620 – 8.255 E1 7.112 – 7.493 B 0.381 – 0.533 B1 1.143 – 1.397 B2 0.762 – 1.143 L 3.175 – 3.429 C 0.203 – 0.356 eB – – 10.160 SYMBOL A e NOTE Note 1 Note 1 2.540 TYP 09/28/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 28P3 REV. B 15 2486LS–AVR–10/03 32M1-A D D1 1 2 3 0 Pin 1 ID E1 SIDE VIEW E TOP VIEW A3 A2 A1 A 0.08 C P COMMON DIMENSIONS (Unit of Measure = mm) D2 Pin 1 ID 1 2 3 P E2 SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A2 – 0.65 1.00 A3 b 0.20 REF 0.18 D L D2 3.25 4.75BSC 2.95 e Notes: 1. JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. 3.10 5.00 BSC E1 E2 0.30 4.75 BSC 2.95 E BOTTOM VIEW 0.23 5.00 BSC D1 e b NOTE 3.10 3.25 0.50 BSC L 0.30 0.40 0.50 P – – 0 – – 0.60 12o 01/15/03 R 16 2325 Orchard Parkway San Jose, CA 95131 TITLE 32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm Micro Lead Frame Package (MLF) DRAWING NO. 32M1-A REV. C ATmega8(L) 2486LS–AVR–10/03 ATmega8(L) Erratas The revision letter in this section refers to the revision of the ATmega8 device. ATmega8 Rev. D, E, F, and G • CKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32 KHz Oscillator is Used to Clock the Asynchronous Timer/Counter2 1. CKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32 KHz Oscillator is Used to Clock the Asynchronous Timer/Counter2 When the internal RC Oscillator is used as the main clock source, it is possible to run the Timer/Counter2 asynchronously by connecting a 32 KHz Oscillator between XTAL1/TOSC1 and XTAL2/TOSC2. But when the internal RC Oscillator is selected as the main clock source, the CKOPT Fuse does not control the internal capacitors on XTAL1/TOSC1 and XTAL2/TOSC2. As long as there are no capacitors connected to XTAL1/TOSC1 and XTAL2/TOSC2, safe operation of the Oscillator is not guaranteed. Problem fix/Workaround Use external capacitors in the range of 20 - 36 pF on XTAL1/TOSC1 and XTAL2/TOSC2. This will be fixed in ATmega8 Rev. G where the CKOPT Fuse will control internal capacitors also when internal RC Oscillator is selected as main clock source. For ATmega8 Rev. G, CKOPT = 0 (programmed) will enable the internal capacitors on XTAL1 and XTAL2. Customers who want compatibility between Rev. G and older revisions, must ensure that CKOPT is unprogrammed (CKOPT = 1). 17 2486LS–AVR–10/03 Datasheet Change Log for ATmega8 This document contains a log on the changes made to the datasheet for ATmega8. Changes from Rev. 2486K-08/03 to Rev. 2486L-10/03 All page numbers refers to this document. 1. Removed “Preliminary” and TBDs from the datasheet. 2. Renamed ICP to ICP1 in the datasheet. 3. Removed instructions CALL and JMP from the datasheet. 4. Updated tRST in Table 15 on page 36, VBG in Table 16 on page 40, Table 100 on page 238 and Table 102 on page 240. 5. Replaced text “XTAL1 and XTAL2 should be left unconnected (NC)” after Table 9 in “Calibrated Internal RC Oscillator” on page 28. Added text regarding XTAL1/XTAL2 and CKOPT Fuse in “Timer/Counter Oscillator” on page 30. 6. Updated Watchdog Timer code examples in “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 43. 7. Removed bit 4, ADHSM, from “Special Function IO Register – SFIOR” on page 56. 8. Added note 2 to Figure 103 on page 211. 9. Updated item 4 in the “Serial Programming Algorithm” on page 232. 10. Added tWD_FUSE to Table 97 on page 233 and updated Read Calibration Byte, Byte 3, in Table 98 on page 234. 11. Updated Absolute Maximum Ratings* and DC Characteristics in “Electrical Characteristics” on page 236. Changes from Rev. 2486J-02/03 to Rev. 2486K-08/03 All page numbers refers to this document. 1. Updated VBOT values in Table 15 on page 36. 2. Updated “ADC Characteristics” on page 242. 3. Updated “ATmega8 Typical Characteristics” on page 243. 4. Updated “Erratas” on page 17. Changes from Rev. 2486I-12/02 to Rev. 2486J-02/03 All page numbers refers to this document. 1. Improved the description of “Asynchronous Timer Clock – clkASY” on page 24. 2. Removed reference to the “Multipurpose Oscillator” application note and the “32 kHz Crystal Oscillator” application note, which do not exist. 18 ATmega8(L) 2486LS–AVR–10/03 ATmega8(L) 3. Corrected OCn waveforms in Figure 38 on page 88. 4. Various minor Timer 1 corrections. 5. Various minor TWI corrections. 6. Added note under “Filling the Temporary Buffer (Page Loading)” on page 212 about writing to the EEPROM during an SPM Page load. 7. Removed ADHSM completely. 8. Added section “EEPROM Write during Power-down Sleep Mode” on page 21. 9. Removed XTAL1 and XTAL2 description on page 5 because they were already described as part of “Port B (PB7..PB0) XTAL1/ XTAL2/TOSC1/TOSC2” on page 5. 10. Improved the table under “SPI Timing Characteristics” on page 240 and removed the table under “SPI Serial Programming Characteristics” on page 235. 11. Corrected PC6 in “Alternate Functions of Port C” on page 59. 12. Corrected PB6 and PB7 in “Alternate Functions of Port B” on page 56. 13. Corrected 230.4 Mbps to 230.4 kbps under “Examples of Baud Rate Setting” on page 155. 14. Added information about PWM symmetry for Timer 2 in “Phase Correct PWM Mode” on page 111. 15. Added thick lines around accessible registers in Figure 76 on page 165. 16. Changed “will be ignored” to “must be written to zero” for unused Z-pointer bits under “Performing a Page Write” on page 212. 17. Added note for RSTDISBL Fuse in Table 87 on page 219. 18.Updated drawings in “Packaging Information” on page 14. Changes from Rev. 2486H-09/02 to Rev. 2486I-12/02 1.Added errata for Rev D, E, and F on page 17. Changes from Rev. 2486G-09/02 to Rev. 2486H-09/02 1.Changed the Endurance on the Flash to 10,000 Write/Erase Cycles. Changes from Rev. 2486F-07/02 to Rev. 2486G-09/02 All page numbers refers to this document. 1 Updated Table 103, “ADC Characteristics,” on page 242. 19 2486LS–AVR–10/03 Changes from Rev. 2486E-06/02 to Rev. 2486F-07/02 All page numbers refers to this document. 1 Changes in “Digital Input Enable and Sleep Modes” on page 53. 2 Addition of OCS2 in “MOSI/OC2 – Port B, Bit 3” on page 57. 3 The following tables has been updated: Table 51, “CPOL and CPHA Functionality,” on page 129, Table 59, “UCPOL Bit Settings,” on page 154, Table 72, “Analog Comparator Multiplexed Input(1),” on page 191, Table 73, “ADC Conversion Time,” on page 196, Table 75, “Input Channel Selections,” on page 202, and Table 84, “Explanation of Different Variables used in Figure 103 and the Mapping to the Z-pointer,” on page 217. 5 Changes in “Reading the Calibration Byte” on page 229. 6 Corrected Errors in Cross References. Changes from Rev. 2486D-03/02 to Rev. 2486E-06/02 All page numbers refers to this document. 1 Updated Some Preliminary Test Limits and Characterization Data The following tables have been updated: Table 15, “Reset Characteristics,” on page 36, Table 16, “Internal Voltage Reference Characteristics,” on page 40, DC Characteristics on page 236, Table , “ADC Characteristics,” on page 242. 2 Changes in External Clock Frequency Added the description at the end of “External Clock” on page 30. Added period changing data in Table 99, “External Clock Drive,” on page 238. 3 Updated TWI Chapter More details regarding use of the TWI bit rate prescaler and a Table 65, “TWI Bit Rate Prescaler,” on page 169. Changes from Rev. 2486C-03/02 to Rev. 2486D-03/02 All page numbers refers to this document. 1 Updated Typical Start-up Times. The following tables has been updated: Table 5, “Start-up Times for the Crystal Oscillator Clock Selection,” on page 26, Table 6, “Start-up Times for the Low-frequency Crystal Oscillator Clock Selection,” on page 26, Table 8, “Start-up Times for the External RC Oscillator Clock Selection,” on page 27, and Table 12, “Start-up Times for the External Clock Selection,” on page 30. 2 Added “ATmega8 Typical Characteristics” on page 243. Changes from Rev. 2486B-12/01 to Rev. 2486C-03/02 All page numbers refers to this document. 1 Updated TWI Chapter. More details regarding use of the TWI Power-down operation and using the TWI as Master with low TWBRR values are added into the datasheet. Added the note at the end of the “Bit Rate Generator Unit” on page 166. 20 ATmega8(L) 2486LS–AVR–10/03 ATmega8(L) Added the description at the end of “Address Match Unit” on page 166. 2 Updated Description of OSCCAL Calibration Byte. In the datasheet, it was not explained how to take advantage of the calibration bytes for 2, 4, and 8 MHz Oscillator selections. This is now added in the following sections: Improved description of “Oscillator Calibration Register – OSCCAL” on page 29 and “Calibration Byte” on page 220. 3 Added Some Preliminary Test Limits and Characterization Data. Removed some of the TBD’s in the following tables and pages: Table 3 on page 24, Table 15 on page 36, Table 16 on page 40, Table 17 on page 42, “TA = -40×C to 85×C, VCC = 2.7V to 5.5V (unless otherwise noted)” on page 236, Table 99 on page 238, and Table 102 on page 240. 4 Updated Programming Figures. Figure 104 on page 221 and Figure 112 on page 231 are updated to also reflect that AVCC must be connected during Programming mode. 5 Added a Description on how to Enter Parallel Programming Mode if RESET Pin is Disabled or if External Oscillators are Selected. Added a note in section “Enter Programming Mode” on page 223. 21 2486LS–AVR–10/03 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. © Atmel Corporation 2003. All rights reserved. Atmel ® and combinations thereof, AVR®, and AVR Studio ® are the registered trademarks of Atmel Corporation or its subsidiaries. Microsoft ®, Windows®, Windows NT®, and Windows XP ® are the registered trademarks of Microsoft Corporation. Other terms and product names may be the trademarks of others Printed on recycled paper. 2486LS–AVR–10/03