CY28372 SiS 746 AMD Athlon™/AMD Duron™ Clock Synthesizer Features • One differential CPU clock (opendrain) • One singled-ended CPU clock (opendrain) • Supports AMD Athlon/Duron CPU • SMBus support with readback capabilities • 3.3V and 2.5V power supply • Spread Spectrum electromagnetic interference (EMI) reduction • Eight copies of PCI clocks • One 48-MHz USB clock • 48-pin SSOP package • Two copies of ZCLK clocks • One 48-MHz/24-MHz programmable SIO clock Block Diagram XIN XOUT XTAL OSC **FS0:3 ZCLK REF PCI AGP IOAPIC 48M 24_48M x2 x2 x3 x8 x2 x2 x1 x1 Pin Configuration VDD_REF REF0:2 PLL Ref Freq VDD_CPU CPUT1 Divider Network CPUT0, CPUC0 VDD_Z ~ PLL 1 CPU ZCLK0:1 CPU_STP# VDD_APIC VDD_PCI PCIF0:1 2 PCI0:5 PCI_STP# PLL2 VDD_AGP AGP0:1 Fract. Aligner VDD_48 48 MHz PD# 24_48MHz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CY28372 APIC0:1 VDD_REF **FS0/REF0 **FS1/REF1 REF2 GND_REF XIN XOUT GND_Z ZCLK0 ZCLK1 VDD_Z *PCI_STP# VDD_PCI **FS2/PCIF0 *FS3/PCIF1 PCI0 PCI1 GND_PCI VDD_PCI PCI2 PCI3 PCI4 PCI5 GND_PCI 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDD_APIC IOAPIC1 IOAPIC0 GND_APIC CPU_STP#* CPUT1 VDD_CPU GND_CPU CPUT0 CPUC0 VDD_CPU GNDA VDDA SCLK SDATA PD#* GND_AGP AGP0 AGP1 VDD_AGP VDD_48 48MHZ 24_48MHZ GND_48 2 SDATA SCLK SSOP-48 I2C Logic * : Internal Pull-up 150k ** : Internal Pull-down 150k Cypress Semiconductor Corporation Document #: 38-07533 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised September 20, 2004 CY28372 Pin Description Pin #. Name Type 6 XIN I Crystal Connection or External Reference Frequency Input. This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Description 7 XOUT O Crystal Connection. Connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. 4 REF2 O Reference Clock. 14.31818 reference outputs. 2, 3 REF[0:1]/ FS[0:1] O Reference Clock. 14.31818 reference outputs. I Frequency Select. Sampled upon power-on to determine device operating frequency. 14, 15 PCIF[0:1]/ FS[2:3] O Free-running PCI. Independent of PCI_STP#. I Frequency Select. Sampled upon power-on to determine device operating frequency. 16, 17, 20, 21, 22, 23 PCI [0:5] O PCI Clock. 12 PCI_STP# I PCI Stop. Stops all PCI clocks 40 39 CPUT0 CPUC0 O Differential CPU Outputs. 43 CPUT1 O “True” Clock of Differential CPU Outputs. For chipset host bus 44 CPU_STP# I CPU Stop. Stops all CPU clocks 9, 10 ZCLK[0:1] O MuTIOL Clock Outputs. 46, 47 IOAPIC[0:1] O IOAPIC. 2.5 V clock outputs 27 48MHz O 48-MHz Clock. USB clock outputs 26 24_48MHz O 24-MHz or 48-MHz Clock. Selectable SIO clock outputs. Default output frequency is 24 MHz, but can be configured for 48 MHz through I2C. 31, 30 AGP[0:1] O AGP Clock. 34 SDATA I/O I2C Data. 5v tolerant 35 SCLK I I2C Clock.5v tolerant 33 PD# I Power-down Control. Turns off all clock outputs and shuts down device 36 VDDA PWR 3.3V Analog Power/Ground. Power supply for core logic, PLL circuitry 37 GNDA PWR 1, 5, 8, 11, 13, 18, 19, 24, 25, 28, 29, 32 VDD_REF, GND_REF, GND_Z, VDD_Z, VDD_PCI, GND_PCI, GND_48, VDD_48, VDD_AGP, GND_AGP PWR 3.3V Power and Ground. Power supply for respective output buffers. 38, 41, 42 48, 45 VDD_CPU, GND_CPU, VDD_APIC, GND_APIC PWR 2.5V Power and Ground. Power supply for respective output buffers. Document #: 38-07533 Rev. *A Page 2 of 18 CY28372 Table 1. Frequency Selection Table Input Conditions Output Frequency FS(3:0) CPU (MHz) ZCLK (MHz) AGP (MHz) PCI (MHz) VCO Freq. (MHz) 0 0000 133.3 66.7 66.7 33.3 400.0 0 0001 133.3 66.7 50.0 33.3 400.0 0 0010 133.3 100.0 66.7 33.3 400.0 0 0011 133.3 100.0 50.0 33.3 400.0 0 0100 133.3 133.3 66.7 33.3 400.0 0 0101 133.3 133.3 50.0 33.3 400.0 0 0110 133.3 166.6 66.7 33.3 666.5 0111 133.3 166.6 55.5 33.3 666.5 1000 100.0 66.7 66.7 33.3 400.0 I2C Option (byte 4, bit 2) 0 0 (default) 0 1001 100.0 66.7 50.0 33.3 400.0 0 1010 100.0 100.0 66.7 33.3 400.0 0 1011 100.0 100.0 50.0 33.3 400.0 0 1100 100.0 133.3 66.7 33.3 400.0 0 1101 100.0 133.3 50.0 33.3 400.0 0 1110 111.0 166.5 66.6 33.3 666.1 0 1111 111.0 166.5 55.5 33.3 666.1 1 0000 114.5 95.4 63.6 31.8 572.5 1 0001 120.0 100.0 66.7 33.3 600.0 1 0010 133.3 83.3 66.7 33.3 666.5 1 0011 133.3 111.1 74.1 33.3 666.5 1 0100 133.3 133.3 83.3 33.3 666.5 1 0101 145.7 116.6 64.8 32.4 582.8 1 0110 150.0 100.0 66.7 33.3 600.0 1 0111 166.6 111.1 66.7 33.3 666.5 1 1000 111.1 133.3 66.7 33.3 666.5 1 1001 137.4 137.4 68.7 34.4 549.6 1 1010 144.9 144.9 64.4 32.2 579.5 1 1011 150.0 150.0 66.7 33.3 600.0 1 1100 155.1 124.1 68.9 34.5 620.3 1 1101 166.6 133.3 66.7 33.3 666.5 1 1110 180.1 135.1 67.6 33.8 540.4 1 1111 200.0 133.3 66.7 33.3 400.0 Serial Data Interface Data Protocol To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. Document #: 38-07533 Rev. *A Page 3 of 18 CY28372 The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 2. Command Code Definition Bit Description 7 0 = Block read or block write operation, 1 = Byte read or byte write operation (6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 Description Start Block Read Protocol Bit 1 Slave address – 7 bits 2:8 Description Start Slave address – 7 bits 9 Write = 0 9 Write = 0 10 Acknowledge from slave 10 Acknowledge from slave 11:18 19 20:27 28 29:36 37 38:45 Command Code – 8 bits '00000000' stands for block operation 11:18 Command Code – 8 bits '00000000' stands for block operation Acknowledge from slave 19 Acknowledge from slave Byte Count – 8 bits 20 Repeat start Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave Data byte 2 – 8 bits 21:27 Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave 30:37 38 Byte count from slave – 8 bits 46 Acknowledge from slave .... ...................... .... Data Byte (N–1) –8 bits 47 .... Acknowledge from slave 48:55 .... Data Byte N –8 bits 56 Acknowledge .... Acknowledge from slave .... Data bytes from slave/Acknowledge .... Stop .... Data byte N from slave – 8 bits .... Not Acknowledge .... Stop 39:46 Acknowledge Data byte from slave – 8 bits Acknowledge Data byte from slave – 8 bits Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 Description Start Slave address – 7 bits Byte Read Protocol Bit 1 2:8 Description Start Slave address – 7 bits 9 Write = 0 9 Write = 0 10 Acknowledge from slave 10 Acknowledge from slave 11:18 19 20:27 Command Code – 8 bits '1xxxxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed 11:18 Command Code – 8 bits '1xxxxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave 19 Acknowledge from slave Data byte from master – 8 bits 20 Repeat start Document #: 38-07533 Rev. *A Page 4 of 18 CY28372 Table 4. Byte Read and Byte Write Protocol (continued) Byte Write Protocol Bit Byte Read Protocol Description 28 Acknowledge from slave 29 Stop Bit 21:27 Description Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave 30:37 Data byte from slave – 8 bits 38 Not Acknowledge 39 Stop Device Configuration Map Data Bytes 0 to 3: Reserved for ZDB Registers Byte 4 Bit @Pup Name Bit 7 1 Frequency Select Register (FS3) Bit 6 0 Frequency Select Register (FS2) Bit 5 0 Frequency Select Register (FS1) Bit 4 0 Frequency Select Register (FS0) Description [7..4] CPU ZCLK AGPPCI 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 133.3 133.3 133.3 133.3 133.3 133.3 133.3 133.3 100.0 100.0 100.0 100.0 100.0 100.0 111.0 111.0 66.7 66.7 100.0 100.0 133.3 133.3 166.6 166.6 66.7 66.7 100.0 100.0 133.3 133.3 166.5 166.5 66.733.3 50.033.3 66.733.3 50.033.3 66.733.3 50.033.3 66.733.3 55.533.3 66.733.3 50.033.3 66.733.3 50.033.3 66.733.3 50.033.3 66.633.3 55.533.3 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 114.5 120.0 133.3 133.3 133.3 145.7 150.0 166.6 111.1 137.4 144.9 150.0 155.1 166.6 180.1 200.0 95.4 100.0 83.3 111.1 133.3 116.6 100.0 111.1 133.3 137.4 144.9 150.0 124.1 133.3 135.1 133.3 63.631.8 66.733.3 66.733.3 74.133.3 83.333.3 64.832.4 66.733.3 66.733.3 66.733.3 68.734.4 64.432.2 66.733.3 68.934.5 66.733.3 67.633.8 66.733.3 Bit2 = 0 Bit2 = 1 Bit 3 0 FS_Override Frequency Selection Source: 0 = Select through hardware strapping, latched inputs 1 = Select through I2C Bit 2 0 Frequency Select Register Most significant bit of I2C Frequency Select Register Bit 1 1 Spread Spectrum Control 0 = Normal, 1 = Spread Spectrum enable Bit 0 0 Output Disable 0 = Normal, 1 = three-state all outputs Byte 5 Bit @Pup Bit 7 0 Reserved Name Reserved Bit 6 0 Reserved Reserved Bit 5 0 Reserved Reserved Bit 4 0 Reserved Reserved Document #: 38-07533 Rev. *A Description Page 5 of 18 CY28372 Byte 5 (continued) Bit @Pup Name Bit 3 HW Latched FS3 input Bit 2 HW Latched FS2 input Bit 1 HW Latched FS1 input Bit 0 HW Latched FS0 input Description Latched FS[3:0] inputs. These bits are read-only. Byte 6 Bit @Pup Name Description Bit 7 0 Reserved Reserved Bit 6 0 Reserved Reserved Bit 5 0 PCIF0 PCIF0 functionality when PCI_STP# is LOW 0: Free running, 1: Stop Bit 4 0 PCIF1 PCIF1 functionality when PCI_STP# is LOW 0: Free running, 1: Stop Bit 3 1 CPUT0/CPUC0 CPU[T/C]0 functionality when CPU_STP# is LOW 0: Free running, 1: Stop (three-state) Bit 2 0 CPUT1 CPUT1 functionality when CPU_STP# is LOW 0: Free running, 1: Stop (three-state) Bit 1 1 CPUT0/CPUC0 CPU[T/C]0 Output Enable/Disable Bit 0 1 CPUT1 CPUT1 Output Enable/Disable Byte 7 Bit @Pup Bit 7 1 Name PCIF1 Description PCIF1 Output Enable/Disable Bit 6 1 PCIF0 PCIF0 Output Enable/Disable Bit 5 1 PCI_5 PCI_5 Output Enable/Disable Bit 4 1 PCI_4 PCI_4 Output Enable/Disable Bit 3 1 PCI_3 PCI_3 Output Enable/Disable Bit 2 1 PCI_2 PCI_2 Output Enable/Disable Bit 1 1 PCI_1 PCI_1 Output Enable/Disable Bit 0 1 PCI_0 PCI_0 Output Enable/Disable Byte 8 Bit Bit 7 @Pup 1 Name Pin Description Vendor_ID3 Bit[3] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit 6 0 Vendor_ID2 Bit[2] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit 5 0 Vendor _ID1 Bit[1] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit 4 0 Vendor _ID0 Bit[0] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit 3 0 Revision_ID3 Revision ID bit[3] Bit 2 0 Revision_ID2 Revision ID bit[2] Bit 1 0 Revision_ID1 Revision ID bit[1] Bit 0 0 Revision_ID0 Revision ID bit[0] Byte 9 Bit @Pup Name Description Bit 7 1 PD# Power-down Enable Bit 6 0 Reserved Reserved Bit 5 1 48MHz 48-MHz Output Control Document #: 38-07533 Rev. *A Page 6 of 18 CY28372 Byte 9 (continued) Bit Bit 4 Bit 3 @Pup 1 0 Name Description 24_48MHz 24_48MHz Output Control 24_48MHz 24-MHz or 48-MHz Select 0: 24MHz, 1: 48MHz Spread Spectrum control bit (0 = down spread, 1 = center spread) Bit 2 0 SS2 Bit 1 0 SS1 Bit 0 0 SS0 SS[2:0] 000 001 010 011 100 101 110 111 Spread Mode Down Down Down Down Center Center Center Center Spread% 0, -0.50 (default) +0.12, -0.62 +0.25, -0.75 +0.50, -1.00 +0.25, -0.25 +0.37, -0.37 +0.50, -0.50 +0.75, -0.75 Byte 10 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 @Pup 1 1 1 1 1 1 1 1 Name IOAPIC_1 IOAPIC_0 REF_1 REF_0 ZCLK_1 ZCLK_0 AGP_1 AGP_0 Description IOAPIC_1 Output Control IOAPIC_0 Output Control REF_1 Output Control REF_0 Output Control ZCLK_1 Output Control ZCLK_0 Output Control AGP_1 Output Control AGP_0 Output Control Byte 11 Bit @Pup Bit 7 0 Reserved Name Vendor Test Mode (always program to 0) Bit 6 0 Reserved Vendor Test Mode (always program to 0) Bit 5 0 Reserved Vendor Test Mode (always program to 0) 3V66 Frequency Fractional Aligner: These bits determine the 3V66 fixed frequency. This option does not incorporate spread spectrum. Bit 4 0 3V66 Fract_Align4 Bit 3 0 3V66 Fract_Align3 Bit 2 0 3V66 Fract_Align2 Bit 1 0 3V66 Fract_Align1 Bit 0 0 3V66 Fract_Align0 Document #: 38-07533 Rev. *A Description Fract_Align3V66 (MHz)PCI (MHz) 00000 Off Off(default) 0000166.533.2 0001067.533.7 0001168.534.3 0010069.534.8 0010170.635.3 0011071.635.8 0011172.636.3 0100073.636.8 0100174.737.3 0101075.737.8 0101176.738.4 0110077.738.9 0110178.739.4 0111079.839.9 0111180.840.4 1000081.840.9 1000182.841.4 1001083.941.9 1001184.942.4 1010085.943.0 1010186.943.5 1011088.044.0 1011189.044.5 1100090.045.0 1100191.045.5 1101092.046.0 1101193.146.5 1110094.147.0 1110195.147.6 1111096.148.1 1111197.248.6 Page 7 of 18 CY28372 Byte 12 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 @Pup 0 0 0 0 0 0 Name REF_2 Reserved Reserved DARAG2 DARAG1 DARAG0 Description REF_2 Output Control (default: off) Reserved Reserved Dial-a-Ratio AGP[0:1]. Programming these bits allow modifying the frequency ratio of the AGP(1:0), PCI(5:0) and PCIF(0:1) clocks relative to the VCO. (the ratio of AGP to PCI is retained at 2:1) DARAG[2:0] 000 001 010 011 100 101 110 111 Bit 1 0 Fixed_PCI_SEL Bit 0 0 Fixed_3V66_SEL VC0/AGP Ratio - (Frequency Selection Default) 6 8 9 10 12 12 12 PCI output frequency select mode (valid only when Fixed_3V66_SEL = 1) 0 = Use Frequency Selection Table settings 1 = Use Fractional Aligner settings (default) 3V66 and PCI output frequency select mode 0 = Use Frequency Selection Table settings (default) 1 = Use Fractional Aligner settings Byte 13 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 @Pup 0 0 0 0 0 0 0 0 Name Reserved N6 (MSB) N5 N4 N3 N2 N1 N0 (LSB) Description Reserved Dial-a-Frequency® Control Register N. These bits are for programming the PLL’s internal N register. This access allows the user to modify the CPU frequency with great accuracy. All other synchronous clocks (clocks that are generated from the same PLL, such as PCI, remain at their existing ratios relative to the CPU clock. (should be written together with Control Register R) @Pup 0 0 0 0 0 0 0 0 Name Reserved R5 (MSB) R4 R3 R2 R1 R0 (LSB) R & N Select Pin Description Reserved Dial-a-Frequency Control Register R These bits are for programming the PLL’s internal R register. This access allows the user to modify the CPU frequency with great accuracy. All other synchronous clocks (clocks that are generated from the same PLL, such as PCI, remain at their existing ratios relative to the CPU clock. (should be written together with Control Register N) Byte 14 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Document #: 38-07533 Rev. *A R and N register mux selection. 0 = R and N values come from the ROM. 1 = data is loaded from the DAF registers into R and N. Page 8 of 18 CY28372 Dial-A-Frequency Feature SMBus Dial-a-Frequency feature is available in this device via Byte13 and Byte14. P is a large value PLL constant that depends on the frequency selection achieved through the hardware selectors (FS). P value may be determined from the following table. FS(4:0) 00000, 00001, 00010, 00011, 00100, 00101, 11110 00110, 00111, 10000, 10001, 10010, 10011, 10100 01000, 01001, 01010, 01011, 01100, 01101, 10101, 10110, 10111, 11001, 11010, 11011,11100, 11101 01110, 01111, 11000 11111 Table 5. Maximum Lumped Capacitive Output Loads Clock Max Load Unit PCI, PCIF 20 pF AGP 30 pF 24_48MHz, 48MHz 20 pF REF 30 pF 20 pF IOAPIC CPUT0/CPUC0 See Figure 7 CPUT1 See Figure 7 P 127993333 76796000 95995000 63996667 191990000 PD# (Power-down) Clarification The PD# (Power-down) pin is used to shut off ALL clocks prior to shutting off power to the device. PD# is an asynchronous active LOW input. This signal is synchronized internally to the device powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. When PD# is low, all clocks are driven to a LOW value and held there and the VCO and PLLs are also powered down. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the low ‘stopped’ state. PD# – Assertion PD# CPUT0 Tri-state CPUC0 Tri-state PCI USB,24_48MHz REF Figure 1. Power-down Assertion Timing Waveforms Document #: 38-07533 Rev. *A Page 9 of 18 CY28372 PD# – Deassertion After the clock chip internal PLL is powered up and locked, all outputs will be enabled within a few clock cycles of each other, with the first to last active clock taking no more than two full PCI clock cycles. 1.2 ms PD# CPUT Driven CPUC Driven PCI 33MHz 3V66 USB 48MHz REF 14.318MHz Figure 2. Power Down Deassertion Timing Waveforms Table 6. PD# Functionality PD# CPUT CPUC AGP PCIF/PCI 48MHz 1 Normal Normal Normal Normal Normal 0 Float Float Low Low Low CPU_STP# Clarification The CPU_STP# signal is an active LOW input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. CPU_STP# CPU_STP# – Assertion CPUT When CPU_STP# pin is asserted, all CPUT/C outputs that are set with the SMBus configuration to be stoppable via assertion of CPU_STP# will be stopped after being sampled by two rising CPUC clock edges. The final state of the stopped CPU signals is CPUT = CPUC = three-state. CPUC three-state three-state Figure 3. CPU_STP# Assertion Waveform CPU_STP# Deassertion The deassertion of the CPU_STP# signal will cause all CPUT/C outputs that were stopped to resume normal operation in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produced when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPUC clock cycles. Document #: 38-07533 Rev. *A Page 10 of 18 CY28372 PCI_STP# Assertion The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ns (tsetup). The PCIF clocks will not be affected by this pin if their control bits in the SMBus register are set to allow them to be free running. CPU_STP# CPUT CPUC three-state three-state CPUTint CPUCint Figure 4. CPU_STP# Deassertion Waveform t setup PCI_STP# PCIF 33M PCI 33M Figure 5. PCI_STP# Assertion Waveform PCI_STP# - Deassertion The deassertion of the PCI_STP# signal will cause all PCI and stoppable PCIF clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transitions to a high level. tsetup PCI_STP# PCIF PCI Figure 6. PCI_STP# Deassertion Waveform Document #: 38-07533 Rev. *A Page 11 of 18 CY28372 Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD Core Supply Voltage –0.5 4.6 V VDDA Analog Supply Voltage –0.5 4.6 V VIN Input Voltage Relative to V SS –0.5 VDD + 0.5 VDC TS Temperature, Storage Non-functional –65 +150 °C TA Temperature, Operating Ambient Functional 0 70 °C TJ Temperature, Junction Functional – 150 °C ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 ØJC Dissipation, Junction to Case Mil-Spec 883E Method 1012.1 ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) UL–94 Flammability Rating At 1/8 in. MSL Moisture Sensitivity Level 2000 – V 15 °C/W 45 °C/W V–0 1 Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. DC Electrical Specifications Parameter Description Conditions 3.3V ± 5% Min. Max. Unit 3.135 3.465 V VDD, VDDA 3.3 Operating Voltage CIN Input Pin Capacitance 2 5 pF COUT Output Pin Capacitance 3 6 pF LIN Pin Inductance – 7 nH IDD Dynamic Supply Current – 280 mA IPD Power-down Supply Current PD# Asserted – 1 mA CXTAL Crystal Pin Capacitance 30 42 pF VXIH XIN High Voltage 0.7VDD VDD V VXIL XIN Low Voltage 0 0.3VDD V Min. Max. Unit 47.5 52.5 % All frequencies at maximum value Measured from the XIN or XOUT pin to ground AC Electrical Specifications Parameter TDC Description XIN Duty Cycle Conditions Crystal The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification TPERIOD XIN Period When Xin is driven from an external clock source 69.841 71.0 ns TR / TF XIN Rise and Fall Times Measured between 0.3VDD and 0.7VDD – 10.0 ns TCCJ XIN Cycle to Cycle Jitter As an average over 1-µs duration – 500 ps TDC CPUT0 and CPUC0 Duty Cycle TPERIOD CPUT0/CPUC0 Measured at crossing point VOX 45 55 % 100-MHz CPUT and CPUC Period Measured at crossing point VOX 9.8 10.2 ns TPERIOD 133-MHz CPUT and CPUC Period Measured at crossing point VOX 7.35 7.65 ns TSKEW Any CPU to CPU Clock Skew Measured at crossing point VOX – 150 ps TCCJ CPU Cycle to Cycle Jitter Measured at crossing point VOX – 150 ps Document #: 38-07533 Rev. *A Page 12 of 18 CY28372 AC Electrical Specifications (continued) Parameter Description Conditions Min. Max. Unit Measured from Vol= 0.175 to Voh = 0.525V 0.5 2.0 V/ns 600 800 mv TR / TF CPUT and CPUC Rise and Fall Times VOX Crossing Point Voltage at 0.7V Swing TDC CPUT1 Duty Cycle CPUT1 Measured at crossing point VOX 45 55 % TPERIOD 100MHz CPUT1 Period Measured at crossing point VOX 9.8 10.2 ns TPERIOD 133MHz CPUT1 Period Measured at crossing point VOX 7.35 7.65 ns TCCJ CPUT1 Cycle to Cycle Jitter Measured at crossing point VOX – 150 ps TR / TF CPUT and CPUC Rise and Fall Times Measured from VOL= 0.175 to VOH = 0.525V 0.5 2.0 V/ns TDC IOAPIC Duty Cycle IOAPIC Measured at crossing point VOX 45 55 % TPERIOD 100MHz IOAPIC Period Measured at crossing point VOX 69 70 ns TPERIOD 133MHz IOAPIC Period Measured at crossing point VOX 69 70 ns TSKEW Any IOAPIC clock to any IOPIC Clock Skew Measured at crossing point VOX – 250 ps THIGH IOAPIC High Time 25.5 – TLOW IOAPIC Low Time 25.3 – TCCJ IOAPIC Cycle to Cycle Jitter Measured at crossing point VOX – 500 ps TR / TF IOAPIC Rise and Fall Times Measured from Vol= 0.175 to Voh = 0.525V 0.4 1.6 V/ns TDC AGP Duty Cycle AGP Measured at crossing point VOX 45 55 % TPERIOD 100-MHz AGP Period Measured at crossing point VOX 15.0 15.3 ns TPERIOD 133-MHz AGP Period Measured at crossing point VOX 15.0 15.3 ns TSKEW(UNBUF- Any AGP clock to any AGP Clock Skew Measured at crossing point VOX – 250 ps 5.25 – ns FERED) THIGH AGP High Time TLOW AGP Low Time 5.25 – ns TCCJ AGP Cycle to Cycle Jitter Measured at crossing point VOX – 250 ps TR / TF AGP Rise and Fall Times Measured from Vol = 0.175 to Voh = 0.525V 0.5 1.6 ns TDC ZCLK Duty Cycle ZCLK Measured at crossing point VOX 45 55 % TSKEW Any ZCLK clock to any ZCLK Clock Skew Measured at crossing point VOX – 175 ps TCCJ ZCLK Cycle to Cycle Jitter Measured at crossing point VOX – 250 ps TR / TF ZCLK Rise and Fall Times Measured from Vol= 0.175 to Voh = 0.525V 0.5 1.6 ns TDC PCI and PCIF Duty Cycle PCI/PCIF Measured at crossing point VOX 45 55 % TPERIOD 100-MHz PCI and PCIF Period Measured at crossing point VOX 30.0 – ns TPERIOD 133-MHz PCI and PCIF Period Measured at crossing point VOX 30.0 – ns TSKEW Any PCI and PCIF clock to any PCI and Measured at crossing point VOX PCIF Clock Skew – 500 ps THIGH PCI and PCIF High Time 12.0 – ns TLOW PCI and PCIF Low Time 12.0 – ns Document #: 38-07533 Rev. *A Page 13 of 18 CY28372 AC Electrical Specifications (continued) Conditions Min. Max. Unit TCCJ Parameter PCI and PCIF Cycle to Cycle Jitter Description Measured at crossing point VOX – 500 ps TR / TF PCI and PCIF Rise and Fall Times Measured from Vol= 0.175 to Voh = 0.525V 0.5 2.0 ns TDC 48M Duty Cycle 48M Measurement at 1.5V 45 55 % TPERIOD 133-MHz 48M Period Measurement at 1.5V 20.829 20.834 ns TPERIOD 133-MHz 48 M Period Measurement at 1.5V 20.829 20.834 ns TR / TF 48M Rise and Fall Times Measured between 0.4V and 2.4V 1.0 2.0 ns TCCJ 48M Cycle to Cycle Jitter Measurement at 1.5V – 350 ps TDC 24M Duty Cycle 24M Measurement at 1.5V 45 55 % TPERIOD 100-MHz 24M Period Measurement at 1.5V 41.66 41.67 ns TPERIOD 133-MHz 24M Period Measurement at 1.5V 41.66 41.67 ns TR / TF 24M Rise and Fall Times Measured between 0.4V and 2.4V 1.0 2.0 ns TCCJ 24M Cycle to Cycle Jitter Measurement at 1.5V – 500 ps TDC REF Duty Cycle REF Measurement at 1.5V 45 55 % TPERIOD REF Period Measurement at 1.5V 69.841 71.0 ns TR / TF REF Rise and Fall Times Measured between 0.4V and 2.4V 1.0 4.0 ns TCCJ REF Cycle to Cycle Jitter Measurement at 1.5V – 1000 ps TSTABLE ENABLE/DISABLE and SETUP All Clock Stabilization from Power-up – 1.5 ms TSS Stopclock Set-up Time 10.0 – ns TSH Stopclock Hold Time 0 – ns TODIS Output Disable Delay (all outputs) 1.0 10.00 ns TOENB Output Enable Delay (all outputs) 1.0 10.00 ns Document #: 38-07533 Rev. *A Page 14 of 18 CY28372 Test and Measurement Set-up For Differential CPU Output Signals The following diagram shows lumped test load configurations for the differential Host Clock Outputs. VDD_CPU 6 8Ω T PCB C P U T /C M eas urem ent P o int 5pF V D D _C P U 75Ω TPCB CPUCS M ea surem e nt P oint 5pF Figure 7. CPUCLK Test Load Configuration O u tp u t u n d e r T e s t P ro b e Load Cap 3 .3 V s ig n a l s tD C - - 3 .3 V 2 .4 V 1 .5 V 0 .4 V 0V Tr Tf Figure 8. Lumped Load For Single-Ended Output Signals (for AC Parameters Measurement) Table 7. Group Timing Relationship and Tolerances Offset (Typical) Tolerance (or Range) Conditions Notes CPU to AGP 2 ns 1 – 4 ns CPU leads – CPU to Z 2 ns 1 – 4 ns CPU leads – CPU to PCI 2 ns 1 – 4 ns CPU leads – Document #: 38-07533 Rev. *A Page 15 of 18 CY28372 Ordering Information Ordering Code Package Type Operating Range CY28372OC 48-pin Small Shrunk Outline Package (SSOP) Commercial, 0°C to 70°C CY28372OCT 48-pin Small Shrunk Outline Package (SSOP) – Tape and Reel Commercial, 0°C to 70°C CY28372OXC 48-pin Small Shrunk Outline Package (SSOP) Commercial, 0°C to 70°C CY28372OXCT 48-pin Small Shrunk Outline Package (SSOP) – Tape and Reel Commercial, 0°C to 70°C Lead Free Layout Example VDD33 FB C1 VDD25 C2 G C2 G G G C3 C3 C3 G C3 C1 G 1 V 2 3 4 5 6 7 8 9 10 11 V 12 13 V 14 15 16 17 18 19 V 20 21 22 23 24 48 47 46 45 44 43 V 42 41 40 39 V 38 37 V 36 35 34 33 32 31 30 V 29 V 28 27 26 25 V G G G G CY28372 G G FB G G G G G G G C3 C3 G C3 G C3 G C3 G G C3 FB = Dale ILB1206 - 300 (300 Ω @ 100 MHz) Cermaic Caps C1 = 10 - 22 µF G = VIA to GND plane layer C2 = .005 µF C3 = .1µF V = VIA to respective supply plane layer Note: Each supply plane or strip should have a ferrite bead and capacitors All bypass caps = .1-µf ceramic * For use with onboard video using 48 MHz for Dot Clock or connect to VDDQ3 Document #: 38-07533 Rev. *A Page 16 of 18 CY28372 Package Diagram 48-lead Shrunk Small Outline Package O48 51-85061-*C Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Athlon and Duron are trademarks of Advanced Micro Devices, Inc. Dial-A-Frequency is a registered trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07533 Rev. *A Page 17 of 18 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY28372 Document History Page Document Title: CY28372 SiS 746 AMD Athlon™/AMD Duron™ Clock Synthesizer Document Number: 38-07533 Issue Date Orig. of Change REV. ECN NO. ** 125162 04/25/03 RGL New data sheet *A 266732 See ECN RGL Added Lead-Free devices Document #: 38-07533 Rev. *A Description of Change Page 18 of 18