CYM1861AV33 2,048K x 32 3.3V Static RAM Module Features chip selects are used to independently enable the four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. • High-density 3.3V 64-megabit SRAM module • 32-bit Standard Footprint supports densities from 16K × 32 through 2M × 32 • High-speed SRAMs — Access time of 20 ns • 72 pins • Available in SIMM format The CYM1861AV33 is designed for use with standard 72-pin SIMM sockets. The pinout is downward compatible with the 64-pin JEDEC SIMM module family (CYM1821, CYM1831, CYM1836, and CYM1841). Thus, a single motherboard design can be used to accommodate memory depth ranging from 16K words (CYM1821) to 2,048K words (CYM1861AV33). The CYM1861AV33 is offered in vertical SIMM configuration and is available with tin-lead edge contacts. Functional Description The CYM1861AV33 is a high-performance 3.3V 64-megabit static RAM module organized as 2,048K words by 32 bits. This module is constructed from sixteen 1,024K × four SRAMs in SOJ packages mounted on an epoxy laminate substrate. Four Presence detect pins (PD0–PD3) are used to identify module memory density in applications where modules with alternate word depths can be interchanged. Logic Block Diagram Pin Configuration ZIP/SIMM Top View A0–A19 OE Buffer PD0 – PD1 – PD 2 – PD3 – 20 OPEN GND GND OPEN WE 4 1M x 4 SRAM 4 4 1M x 4 SRAM 4 CS1 –CS 4 A20 MUX 4:8 4 1M x 4 SRAM 4 4 1M x 4 SRAM 4 I/O4 – I/O7 1M x 4 SRAM I/O0 – I/O3 I/O12 – I/O15 4 4 4 I/O8 – I/O11 1M x 4 SRAM 4 I/O20 – I/O23 I/O16 –I/O19 1M x 4 SRAM 4 I/O28 – I/O31 I/O24 –I/O27 1M x 4 SRAM 4 4 4 I/O4 – I/O7 I/O0 – I/O3 NC PD3 PD0 I/O0 I/O1 I/O2 I/O3 VCC A7 A8 A9 I/O4 I/O5 I/O6 I/O7 WE A14 CS1 CS3 A16 I/O12– I/O15 GND I/O8 – I/O11 I/O16 I/O17 I/O18 I/O19 A10 I/O20 – I/O23 A11 I/O16 –I/O19 A12 A13 I/O20 I/O21 I/O28 – I/O31 I/O22 I/O23 I/O24 –I/O27 GND A19 NC 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 33 35 NC PD2 GND PD1 I/O8 I/O9 I/O10 I/O11 A0 A1 A2 I/O12 I/O13 I/O14 I/O15 GND A15 CS2 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 CS4 A17 OE I/O24 I/O25 I/O26 I/O27 A3 A4 A5 VCC A6 I/O28 I/O29 I/O30 I/O31 A18 A20 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 Selection Guide CY1861AV33-20 20 2400 1050 Maximum Access Time Maximum Operating Current Maximum Standby Current Cypress Semiconductor Corporation Document #: 38-05297 Rev. ** • 3901 North First Street • CY1861AV33-25 25 2400 1050 San Jose • Unit ns mA mA CA 95134 • 408-943-2600 Revised August 20, 2002 CYM1861AV33 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................–55°C to +125°C Ambient Temperature with Power Applied............................................... –10°C to +85°C DC Voltage Applied to Outputs in High-Z State................................................ –0.5V to +VCC DC Input Voltage ............................................–0.5V to +4.6V Operating Range Range Commercial Ambient Temperature 0°C to +70°C Test Conditions Min. Supply Voltage to Ground Potential ............... –0.5V to +4.6V VCC 3.3 V + 10% –5% Electrical Characteristics Over the Operating Range Parameter Description VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 4.0 mA VOL Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Load Current IOZ ICC Max. Unit 2.4 V 2.2 0.4 V VCC + 0.3 V –0.3V 0.8 V GND < VI < VCC –10 +10 µA Output Leakage Current GND < VO < VCC, Output Disabled –20 +20 µA VCC Operating Supply Current VCC = Max., IOUT = 0 mA, CSN < VIL 2400 mA ISB1 Automatic CS Power-down Current[1] Max. VCC, CS > VIH, Min. Duty Cycle = 100% 1050 mA ISB2 Automatic CS Power-down Current[1] Max. VCC, CS > VCC − 0.2V, VIN > VCC − 0.2V, or VIN < 0.2V 500 mA Capacitance[2] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. Unit 7 pF 14 pF AC Test Loads and Waveforms R1 589 Ω R1 589 Ω 3.3V ALL INPUT PULSES 3.3V OUTPUT R2 434 Ω 30 pF INCLUDING JIG AND SCOPE OUTPUT 90% OUTPUT THÉVENIN 250 Ω R2 434 Ω 5 pF INCLUDING JIG AND SCOPE (a) Equivalent to: 3.3V GND 90% 10% 10% < 5 ns < 5 ns (b) EQUIVALENT 1.40V Notes: 1. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 2. Tested on a sample basis. Document #: 38-05297 Rev. ** Page 2 of 7 CYM1861AV33 Switching Characteristics Over the Operating Range[3] CY1861AV33-20 Parameter Description Min. Max. CY1861AV33-25 Min. Max. Unit Read Cycle tRC Read Cycle Time 20 25 tAA Address to Data Valid tOHA Data Hold from Address Change tACS CS LOW to Data Valid 20 25 ns tDOE OE LOW to Data Valid 12 15 ns tLZOE OE LOW to Low-Z tHZOE OE HIGH to High-Z 20 3 25 3 0 3 ns ns 4 10 [4] ns ns 12 7 ns tLZCS CS LOW to Low-Z tHZCS CS HIGH to High-Z[4, 5] 10 12 ns ns tPD CS HIGH to Power-down 20 25 ns Write Cycle[6] tWC Write Cycle Time 20 25 ns tSCS CS LOW to Write End 17 20 ns tAW Address Set-up to Write End 17 20 ns tHA Address Hold from Write End 3 3 ns tSA Address Set-up to Write Start 2 2 ns tPWE WE Pulse Width 15 20 ns tSD Data Set-up to Write End 12 15 ns tHD Data Hold from Write End 2 2 ns tLZWE WE HIGH to Low-Z 3 tHZWE WE LOW to High-Z[5] 0 3 12 0 ns 12 ns Switching Waveforms Read Cycle No. 1[7, 8] t RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Notes: 3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 4. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed and not 100% tested. 5. tHZCS and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ± 500 mV from steady-state voltage. 6. The internal Write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write. 7. WE is HIGH for Read cycle. Document #: 38-05297 Rev. ** Page 3 of 7 CYM1861AV33 Switching Waveforms (continued) Read Cycle No. 2 [7, 9] t RC CS tACS OE tHZOE tDOE tHZCS tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID DATA OUT tLZCS tPD tPU ICC V CC SUPPLY CURRENT 50% 50% ISB Write Cycle No. 1 (WE Controlled) [6] tWC ADDRESS tSCS CS tAW tSA tHA tPWE WE tSD DATA IN DATA VALID tHZWE DATA OUT tHD tLZWE HIGH IMPEDANCE DATA UNDEFINED Notes: 8. Device is continuously selected, CS = VIL, and OE = VIL. 9. Address valid prior to or coincident with CS transition LOW. Document #: 38-05297 Rev. ** Page 4 of 7 CYM1861AV33 Switching Waveforms (continued) Write Cycle No. 2 (CS Controlled) [6,10] tWC ADDRESS tSCS tSA CS tAW tHA tPWE WE tSD DATA IN tHD DATA VALID tHZWE HIGH IMPEDANCE DATA OUT DATA UNDEFINED Truth Table CS WE OE H X X High-Z Inputs/Output Deselect/Power-down Mode L H L Data Out Read L L X Data In Write L H H High-Z Deselect Ordering Information Speed (ns) Ordering Code Package Type Package Type Operating Range 20 CYM1861AV33PM-20C PM48 72-pin Plastic SIMM Module Commercial 25 CYM1861AV33PM-25C PM48 72-pin Plastic SIMM Module Commercial Note: 10. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 38-05297 Rev. ** Page 5 of 7 CYM1861AV33 Package Diagram 72-pin Plastic SIMM Module 51-41322-*D All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05297 Rev. ** Page 6 of 7 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CYM1861AV33 Document Title: CYM1861AV33 2,048K x 32 3.3V Static RAM Module Document Number: 38-05297 REV. ECN NO. Issue Date Orig. of Change ** 117909 08/22/02 MEG Document #: 38-05297 Rev. ** Description of Change New Data Sheet Page 7 of 7