81A CYM1481A 2048K x 8 SRAM Module Features are constructed from four 512K x 8 SRAMs in plastic surface-mount packages on an epoxy laminate board with pins. On-board decoding selects one of the SRAMs from the high-order address lines, keeping the remaining devices in standby mode for minimum power consumption. • High-density 16-megabit SRAM modules • High-speed CMOS SRAMs — Access time of 70 ns • Low active power — 605 mW (max.), 2M x 8 • Double-sided SMD technology • TTL-compatible inputs and outputs • Small footprint SIP — PCB layout area of 0.72 sq. in. • 2V data retention (L version) An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When MS and WE inputs are both LOW, data on the eight data input/output pins is written into the memory location specified on the address pins. Reading the device is accomplished by selecting the device and enabling the outputs MS and OE active LOW while WE remains inactive or HIGH. Under these conditions, the content of the location addressed by the information on the address pins is present on the eight data input/output pins. Functional Description The CYM1481A is a high-performance 16-megabit static RAM module organized as 2048K words by 8 bits. These modules The input/output pins remain in a high-impedance state unless the module is selected, outputs are enabled, and write enable (WE) is HIGH. Logic Block Diagram Pin Configuration SIP Top View A0–A 18 512K x 8 SRAM 19 OE WE A 19–A 20 2 512K x 8 SRAM 1 of 4 DECODER MS 512K x 8 SRAM 512K x 8 SRAM 8 1481-1 A19 VCC WE I/O2 I/O3 I/O0 A1 A2 A3 A4 GND I/O5 A10 A11 A5 A13 A14 A20 MS A15 A16 A12 A18 A6 I/O1 GND A0 A7 A8 A9 I/O7 I/O4 I/O6 A17 I/O0–I/O 7 VCC OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 / Selection Guide CYM1481A Maximum Access Time (ns) 70 85 100 120 Maximum Operating Current (mA) 110 110 110 110 Maximum Standby Current (mA) 64 64 64 64 Cypress Semiconductor Corporation Document #: 38-05074 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised September 4, 2001 CYM1481A Maximum Ratings (Above which the useful life may be impaired.) DC Input Voltage–0.3V to +7.0V Storage Temperature –55°C to +125°C Output Current into Outputs (LOW)20 mA Ambient Temperature with Power Applied0°C to +70°C Operating Range Range Ambient Temperature VCC Commercial 0°C to +70°C 5V ± 10% Supply Voltage to Ground Potential–0.3V to +7.0V DC Voltage Applied to Outputs in High Z State–0.3V to +7.0V Electrical Characteristics Over the Operating Range 1481A Parameter Description Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = –1.0 mA 2.4 V VOL Output LOW Voltage VCC = Min., IOL = 2.0 mA 0.4 V VIH Input HIGH Voltage 2.2 VCC + 0.3 V VIL Input LOW Voltage –0.3 0.8 V IIX Input Load Current GND < VI < VCC –20 +20 µA IOZ Output Leakage Current GND < VO < VCC, Output Disabled –20 +20 µA ICC VCC Operating Supply Current VCC = Max., MS < VIL, IOUT = 0 mA 110 mA ISB1 Automatic MS Power-Down Current Max. VCC, MS > VIH, Min. Duty Cycle = 100% 64 mA ISB2 Automatic MS Power-Down Current Max. VCC, MS > VCC – 0.2V, VIN > VCC – 0.2V, or VIN < 0.2V Standard 32 mA L Version –100, –120 500 µA L Version –85 1600 µA Capacitance[1] Parameter Description CINA Input Capacitance (A0–16, OE, WE) CINB Input Capacitance (A17–20, MS) COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V CYM1481AM ax. Unit 125 pF 25 pF 165 pF Note: 1. Tested on a sample basis. Document #: 38-05074 Rev. ** Page 2 of 9 CYM1481A AC Test Loads and Waveforms R1 2530 Ω R1 2530Ω 5V 5V OUTPUT OUTPUT R2 2830Ω 100 pF INCLUDING JIG AND SCOPE ALL INPUT PULSES 3.0V 90% R2 2830Ω 5 pF GND Equivalent to: (b) 1481-2 10% < 10 ns INCLUDING JIG AND SCOPE (a) 90% 10% < 10 ns 1481-3 1481-4 THÉVENIN EQUIVALENT OUTPUT 1340Ω 2.64V Switching Characteristics Over the Operating Range[2] 1481A-70 Parameter Description Min. Max. 1481A–85 Min. Max. 1481A–100 1481A–120 Min. Min. Max. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tAMS MS LOW to Data Valid 70 85 100 120 ns tDOE OE LOW to Data Valid 40 45 50 60 ns tLZOE OE LOW to Low Z tHZOE 70 85 70 5 OE HIGH to High Z [4] tLZMS MS LOW to Low Z tHZMS MS HIGH to High Z[3, 4] 85 10 5 [3] 100 5 100 10 5 30 10 120 10 ns 45 10 35 ns ns 5 35 30 ns 10 5 30 30 120 ns ns 45 ns [5] WRITE CYCLE tWC Write Cycle Time 70 85 100 120 ns tSMS MS LOW to Write End 65 75 90 100 ns tAW Address Set-Up to Write End 65 75 90 100 ns tHA Address Hold from Write End 5 7 7 7 ns tSA Address Set-Up to Write Start 0 5 5 5 ns tPWE WE Pulse Width 65 65 75 85 ns tSD Data Set-Up to Write End 30 35 40 45 ns tHD Data Hold from Write End 0 5 5 5 ns [3] tHZWE WE LOW to High Z tLZWE WE HIGH to Low Z 30 5 30 5 35 5 40 5 ns ns Notes: 2. Test conditions assume signal transition time of 10 µs or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, output loading of 1 TTL load, and 100-pF load capacitance. 3. tHZOE, tHZMS, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage. 4. At any given temperature and voltage condition, tHZMS is less than tLZMS for any given device. These parameters are guaranteed and not 100% tested. 5. The internal write time of the memory is defined by the overlap of MS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-05074 Rev. ** Page 3 of 9 CYM1481A Data Retention Characteristics (L Version Only) 1481A-70 Parameter Description Test Conditions Min. VDR VCC for Retention Data ICCDR Data Retention Current VDR = 3.0V, MS > VCC – 0.2V, Chip Deselect to Data VIN > VCC – 0.2V or VIN Retention Time < 0.2V Operation Recovery Time tCDR[6] tR Max. 2 1481A–100 148A1–120 1481A–85 Min. Max. Min. 2 800 Max. Unit 250 µA 2 800 V 0 0 0 ns 5 5 5 ns Data Retention Waveform DATA RETENTION MODE VCC 4.5V VDR > 2V tCDR 4.5V tR VDR VIH CS VIH 1481-6 Switching Waveforms Read Cycle No. 1[7, 8] tRC ADDRESS tAA tOHA DATAOUT PREVIOUS DATA VALID DATA VALID 1481-7 Notes: 6. Guaranteed, not tested. 7. Device is continuously selected. OE, MS = VIL. 8. Address valid prior to or coincident with MS transition LOW. Document #: 38-05074 Rev. ** Page 4 of 9 CYM1481A Switching Waveforms (continued) Read Cycle No. 2 [8, 9] tRC MS tAMS OE tHZOE tDOE tHZMS tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID DATA OUT tLZMS 1481-8 [5, 10] Write Cycle No. 1 tWC ADDRESS tSMS MS tAW tSA tHA tPWE WE tSD DATA IN DATA VALID tHZWE DATA I/O tHD tLZWE HIGH IMPEDANCE DATA UNDEFINED 1481-9 Notes: 9. WE is HIGH for read cycle. 10. Data I/O is high impedance if OE = VIH. Document #: 38-05074 Rev. ** Page 5 of 9 CYM1481A Switching Waveforms (continued) Write Cycle No. 2 [5, 10, 11] tWC ADDRESS tSA tSMS MS tAW tHA tPWE WE tSD DATA IN tHD DATA VALID tHZWE DATA I/O HIGH IMPEDANCE DATA UNDEFINED 1481-10 Note: 11. If MS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 38-05074 Rev. ** Page 6 of 9 CYM1481A Truth Table MS WE OE Input/Outputs Mode H X X High Z Deselect/Power-Down L H L Data Out Read L L X Data In Write L H H High Z Deselect Ordering Information Speed (ns) 70 Ordering Code CYM1481APS-70C Package Type Package Type Operating Range PS10 36-Pin SIP Module Commercial PS10 36-Pin SIP Module Commercial PS10 36-Pin SIP Module Commercial PS10 36-Pin SIP Module Commercial CYM1481ALPS-70C 85 CYM1481APS–85C CYM1481ALPS–85C 100 CYM1481APS–100C CYM1481ALPS–100C 120 CYM1481APS–120C CYM1481ALPS–120C Document #: 38-05074 Rev. ** Page 7 of 9 CYM1481A Package Diagram 36-Pin SIP Module PS10 Document #: 38-05074 Rev. ** Page 8 of 9 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CYM1481A Document Title: CYM1481A 2048K x 8 SRAM Module Document Number: 38-05074 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 107267 09/15/01 SZV Change from Spec number: 38-M-00041 to 38-05074 Document #: 38-05074 Rev. ** Page 9 of 9