DIV100 ® ANALOG DIVIDER FEATURES APPLICATIONS ● HIGH ACCURACY: 0.25% Maximum Error, 40:1 Denominator Range ● TWO-QUADRANT OPERATION Dedicated Log-Antilog Technique ● EASY TO USE Laser-trimmed to Specified Accuracy No External Resistors Needed ● LOW COST ● DIP PACKAGE ● DIVISION ● SQUARE ROOT ● RATIOMETRIC MEASUREMENT ● PERCENTAGE COMPUTATION ● TRANSDUCER AND BRIDGE LINEARIZATION ● AUTOMATIC LEVEL AND GAIN CONTROL ● VOLTAGE CONTROLLED AMPLIFIERS ● ANALOG SIMULATION DESCRIPTION The DIV100 is a precision two-quadrant analog divider offering superior performance over a wide range of denominator input. Its accuracy is nearly two orders of magnitude better than multipliers used for division. It consists of four operational amplifiers and logging transistors integrated into a single monolithic circuit and a laser-trimmed, thin-film resistor network. The electrical characteristics of these devices offer the user guaranteed accuracy without the need for external adjustment — the DIV100 is a complete, single package analog divider. 7 VREF Output For those applications requiring higher accuracy than the DIV100 specifies, the capability for optional adjustment is provided. These adjustments allow the user to set scale factor, feedthrough, and outputreferred offsets for the lowest total divider error. The DIV100 also gives the user a precision, temperature-compensated reference voltage for external use. Designers of industrial process control systems, analytical instruments, or biomedical instrumentation will find the DIV100 easy to use and also a low cost, but highly accurate solution to their analog divider applications. 4 Q1 8 14 3kΩ +VCC Q3 6 VREF Common 10 + A1 A3 5 – Q2 1 D Input –VCC 9 A2 12 11 3 A4 2 Output 13 N Input International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • © 1980 Burr-Brown Corporation • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 PDS-427B Printed in U.S.A. October, 1993 SPECIFICATIONS ELECTRICAL At TA = +25°C and VCC = ±15VDC, unless otherwise specified. DIV100HP PARAMETER CONDITIONS MIN TYP MAX MIN vs Supply Warm-up TIme to Rated Performace AC PERFORMANCE Small-Signal Bandwidth 0.5% Amplitude Error 0.57° Vector Error Full-Power Bandwidth Slew Rate Settling Time Overload Recovery INPUT CHARACTERISTICS Input Voltage Range Numerator Denominatior Input Resistance OUTPUT CHARACTERISTICS Full-Scale Output Rated Output Voltage Current Current Limit Positive Negative OUTPUT NOISE VOLTAGE fB = 10Hz to 10kHz D = +10V D = +250mV TEMPERATURE RANGE Specification Operating Temperature Storage MAX MIN TYP MAX UNITS 0.2 * * * * 0.25 * * % FSO(1) % FSO/°C % FSO/°C % FSO/% Minutes RL ≥ 10kΩ 0.25V ≤ D ≤ 10V, N ≤ |D| 1V ≤ D ≤ 10V, N ≤ |D| 0.25V ≤ D ≤ 1V, N ≤ |D| 0.25V ≤ D ≤ 10V, N ≤ |D| 0.7 0.02 0.06 0.15 5 D = +10V –3dB Small-Signal Small-Signal VO = ±10V, IO = ±5mA VD = ±10V, IO = ±5mA ε = 1%, ∆VO = 20V 50% Output Overload N ≤ |D| D ≥ +250mV Either Input IO = ±5mA VO = ±10V 1.0 0.05(2) 0.2(2) 0.3 * * * * 350 15 1000 30 2 15 4 0.5 * * * * * * * * * ±10 ±10 * * 25 * * * * * * * kHz kHz Hz kHz V/µs µs µs * V V kΩ * * * ±10 * * V ±10 ±5 * * * * V mA 15 19 20(2) 23(2) * * * * mA mA * * * * µVrms mVrms N = 0V 370 1 REFERENCE VOLTAGE CHARACTERISTICS, RL ≥ 10MΩ Output Voltage Initial At 25°C vs Supply Temperature Coefficient Output Resistance POWER SUPPLY REQUIREMENTS Rated Voltage Operating Range Quiescent Current Postive Supply Negative Supply TYP VO = 10N/D TRANSFER FUNCTION ACCURACY Total Error Initial vs Temperature DIV100KP DIV100JP Derated Performance 6.5(2) ±12 6.8 ±25 ±50 3 ±15 5 8 Derated Performance 0 –25 –40 7.1(2) * ±20 * * * * * * * * * * 7(2) 10(2) +70 +85 +85 * * * * * * * * * * * * * * * * * * * * * V µV/V ppm/°C kΩ * VDC VDC * * mA mA * * * °C °C °C *Same as DIV100HP. NOTES: (1) FSO is the abbreviation for Full Scale Output. (2) This parameter is untested and is not guaranteed. This specifcation is established to a 90% confidence level. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® DIV100 2 PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Bottom View Supply ........................................................................................... ±20VDC Internal Power Dissipation(1) .......................................................... 600mW Input Voltage Range(2) ................................................................. ±20VDC Storage Temperature Range ........................................... –40°C to +85°C Operating Temperature Range ......................................... –25°C to 85°C Lead Temperature (soldering, 10s) ............................................... +300°C Output Short-Circuit Duration(1, 3) ............................................ Continuous Junction Temperature .................................................................... +175°C DIP +VCC 14 1 Gain Error Adjust Numerator (N) Input 13 2 Output Output Offset Adjust 12 3 –VCC N Input Offset Adjust 11 4 D Input Offset Adjust Common 10 5 Internally Connected to Pin 1 Denominator (D) Input 9 6 Internally Connected to Pin 14 Refererence Voltage 8 7 Internally Connected to Pin 8 NOTES: (1) See General Information section for discussion. (2) For supply voltages less than ±20VDC, the absolute maximum input voltage is equal to the supply voltage. (3) Short-circuit may be to ground only. Rating applies to an ambient temperature of +38°C at rated supply voltage. PACKAGE INFORMATION ORDERING INFORMATION MODEL TEMPERATURE RANGE TOTAL INITIAL ERROR (% FSO) DIV100HP DIV100JP DIV100KP 0°C to +70°C 0°C to +70°C 0°C to +70°C 1.0 0.5 0.25 MODEL PACKAGE PACKAGE DRAWING NUMBER(1) DIV100HP DIV100JP DIV100KP 14-Pin DIP 14-Pin DIP 14-Pin DIP 105 105 105 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. TYPICAL PERFORMANCE CURVES TA = +25°C, VCC = ±15VDC, unless otherwise specified. TOTAL ERROR vs DENOMINATOR VOLTAGE TOTAL ERROR vs AMBIENT TEMPERATURE 1 3 D = |N| 2.4 Total Error (% FSO) Total Error (% FSO) –10V ≤ N ≤ +10V –Numerator +Numerator 0.10 Denominator = 0.25V 1.8 1.2 0.6 Denominator = 1V to 10V 0.01 0 0.1 1 10 –5 Denominator Voltage (V) 40 25 55 70 Ambient Temperature (°C) FREQUENCY RESPONSE vs DENOMINATOR VOLTAGE TOTAL ERROR vs OUTPUT CURRENT 1M 0.6 0.5 Small-Signal Bandwidth (–3dB), VOUT = 100mVp-p 100k Frequency (Hz) Total Error (% FSO) 10 0.4 0.3 +10V Output Full-Power Bandwidth, VOUT = 20Vp-p, RL = 2kΩ 10k 1k 0.2 –10V Output 100 0.1 0 2 4 6 8 10 0.1 1 10 Denominator Voltage (V) Output Current (mA) ® 3 DIV100 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VCC = ±15VDC, unless otherwise specified. AMPLITUDE ERROR vs NUMERATOR FREQUENCY SMALL-SIGNAL FREQUENCY RESPONSE 0 10 D = +10V Amplitude Error (%) Amplitude (dB) N = ±1pk D = +10V D = 0.25V –5 –10 N = 2Vp-p –15 1 0.1 0.01 –20 1K 100k 10k 100 1M NONLINEARITY vs DENOMINATOR VOLTAGE 100k NONLINEARITY vs NUMERATOR FREQUENCY 0.10 5 D = +10V N = 20 sin ωt 0.06 Nonlinearity (% FSO) N = D sin ωt ω = 2π 10Hz VOUT = 10 sin ωt 0.08 Nonlinearity (% FSO) 10k 1k Numerator Frequency (Hz) Frequency (Hz) 0.04 0.02 0.01 1 0.10 0 0.1 1 10 10 100 Denominator Voltage (V) 1k 10k 100k Numerator Frequency (Hz) DENOMINATOR FEEDTHROUGH vs DENOMINATOR FREQUENCY LARGE STEP RESPONSE 40 15 D = +10V CL = 20pF RL = 2kΩ 10 20 D = 0.25V Output Voltage (V) Denominator Feedthrough (dB) N = 0.0 Volts 0 –20 D = 1V D = 10V –40 5 0 –5 –10 –15 –60 1k 100 10k 100k 1M 0 Frequency (Hz) 40 Time (µs) ® DIV100 20 4 60 80 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VCC = ±15VDC, unless otherwise specified. LARGE SIGNAL STEP RESPONSE TRANSIENT RESPONSE 10 150 D = +250mV CL = 20pF RL = 2kΩ D = +10V CL = 20pF 100 Output Voltage (mV) Output (V) 5 0 –5 50 0 –50 –100 –10 –150 0 50 100 150 200 0 10 20 Time (µs) TRANSIENT RESPONSE Output (V) 10Hz to 10kHz Output Noise (mVrms) D = +250mV CL = 20pF 0 –50 –100 0 50 100 150 10 1 N = 10V N = 0V 0.1 200 0.1 1 Time (µs) 10 Denominator Voltage (V) POWER SUPPLY REJECTION vs DENOMINATOR VOLTAGE QUIESCENT CURRENT vs AMBIENT TEMPERATURE 12 80 f = 60Hz Quiescent Supply Current (mA) Power Supply Rejection (dB) 40 OUTPUT NOISE vs DENOMINATOR VOLTAGE 100 50 30 Time (µs) 70 Positive Supply 60 Negative Supply 50 40 10 Negative Supply 8 6 Positive Supply 4 2 30 0.1 1 0 10 Denominator Voltage (V) 10 20 30 40 50 60 70 Ambient Temperature (°C) ® 5 DIV100 DEFINITIONS 0.5% AMPLITUDE ERROR At high frequencies the input-to-output relationship is a complex function that produces both a magnitude and vector error. The 0.5% amplitude error is the frequency at which the magnitude of the output drops 0.5% from its DC value. TRANSFER FUNCTION The ideal transfer function for the DIV100 is: VOUT = 10N/D where: N = Numerator input voltage D = Denominator input voltage 10 = Internal scale factor 0.57° VECTOR ERROR The 0.57° vector error is the frequency at which a phase error of 0.01 radians occurs. This is the most sensitive measure of dynamic error of a divider. Figure 1 shows the operating region over the specified numerator and denominator ranges. Note that below the minimum denominator voltage (250mV) operation is undefined. 10 VOUT = 10V Numerator Voltage (V) 8 VOUT = 8V Constant VOUT Lines 6 VOUT = 6V 4 VOUT = 4V 2 VOUT = 2V 0 1 2 3 4 5 6 7 8 –2 –4 LINEARITY Defining linearity for a nonlinear device may seem unnecessary; however, by keeping one input constant the output becomes a linear function of the remaining input. The denominator is the input that is held fixed with a divider. Nonlinearities in a divider add harmonic distortion to the output in the amount of: Percent Nonlinearity Percent Distortion ≈ √2 9 VOUT = 0V VOUT = –2V VOUT = –4V DMIN –6 VOUT = –6V –8 VOUT = –8V FEEDTHROUGH FIGURE 1. Operating Region. Feedthrough is the signal at the output for any value of denominator within its rated range, when the numerator input is zero. Ideally, the output should be zero under this condition. ACCURACY Accuracy is specified as a percentage of full-scale output (FSO). It is derived from the total error specification. GENERAL INFORMATION –10 Denominator Voltage (V) VOUT = –10V WIRING PRECAUTIONS In order to prevent frequency instability due to lead inductance of the power supply lines, each power supply should be bypassed. This should be done by connecting a 10µF tantalum capacitor in parallel with a 1000pF ceramic capacitor from the +VCC and –VCC pins to the power supply common. The connection of these capacitors should be as close to the DIV100 as practical. TOTAL ERROR Total error is the deviation of the actual output from the ideal quotient 10N/D expressed in percent of FSO (10V); e.g., for the DIV100K: VOUT (ACTUAL) = VOUT (IDEAL) ±total error, where: Total error = 0.25%, FSO = 25mV. It represents the sum of all error terms normally associated with a divider: numerator nonlinearity, denominator nonlinearity, scale-factor error, output-referred numerator and denominator offsets, and the offset due to the output amplifier. Individual errors are not specified because it is their sum that affects the user’s application. CAPACITIVE LOADS Stable operation is maintained with capacitive loads of up to 1000pF, typically. Higher capacitive loads can be driven if a 22Ω carbon resistor is connected in series with the DIV100’s output. SMALL-SIGNAL BANDWIDTH Small-signal bandwidth is the frequency the output drops to 70% (–3dB) of its DC value. The input signal must be low enough in amplitude to keep the divider’s output from becoming slew-rate limited. A rule-of-thumb is to make the output voltage 100mVp-p, when testing this parameter. Small-signal bandwidth is directly proportional to denominator magnitude as described in the Typical Performance Curves. OVERLOAD PROTECTION The DIV100 can be protected against accidental power supply reversal by putting a diode (1N4001 type) in series with each power supply line as shown in Figure 2. This precaution is necessary only in power systems that momentarily reverse polarity during turn-on or turn-off. If this protection circuit is used, the accuracy of the DIV100 will be degraded by the power supply sensitivity specifica- ® DIV100 6 As an example of how to use this model, consider this problem: +VCC Determine the highest ambient temperature at which the DIV100 may be operated with a continuous short circuit to ground. VCC = ±15VDC. DIV100 PD(MAX) = 600mW. TJ(MAX) = +175°C. TA = TJ(MAX) – PDQ (θ2 + θ3) – PDX(SHORT – CIRCUIT) (θ1 + θ2 + θ 3) = 175°C – 18°C – 119°C = 38°C –VCC FIGURE 2. Overload Protection Circuit. PD(ACTUAL) = PDQ + PDX(SHORT – CIRCUIT) ≤ PD(MAX) = 255mW + 345mW = 600mW tion. No other overload protection circuit is necessary. Inputs are internally protected against overvoltages and they are current-limited by at least a 10kΩ series resistor. The output is protected against short circuits to power supply common only. The conclusion is that the device will withstand a shortcircuit up to TA = +38°C without exceeding either the 175°C or 600mW absolute maximum limits. STATIC SENSITIVITY No special handling is required. The DIV100 does not use MOS-type transistors. Furthermore, all external leads are protected by resistors against low energy electrostatic discharge (ESD). LIMITING OUTPUT VOLTAGE SWING The negative output voltage swing should be limited to ±11V, maximum, to prevent polarity inversion and possible system instability. This should be done by limiting the input voltage range. INTERNAL POWER DISSIPATION Figure 3 is the thermal model for the DIV100 where: THEORY OF OPERATION PDQ = Quiescent power dissipation = |+VCC | I+QUIESCENT + |–VCC | I–QUIESCENT The DIV100 is a log-antilog divider consisting of four operational amplifiers and four logging transistors integrated into a single monolithic circuit. Its basic principal of operation can be seen by an analysis of the circuit in Figure 4. PDX = Worst case power dissipation in the output transistor = VCC2/4RLOAD (for normal operation) = VCC IOUTPUT LIMIT (for short-circuit) TJ = Junction temperature (output loaded) TJ* = Junction temperature (no load) TC = Case temperature TA = Ambient temperature θ = Thermal resistance The logarithmic equation for a bipolar transistor is: VBE = VT ln (IC/IS), where: VT = kT/q k = Boltzmann’s constant = 1.381 x 10–23 T = Absolute temperature in degrees Kelvin q = Electron charge = 1.602 x 10–19 IC = Collector current IS = Reverse saturation current This model is a multiple power source model to provide a more accurate simulation. The model in Figure 3 must be used in conjunction with the DIV100’s absolute maximum ratings of internal power dissipation and junction temperature to determine the derated power dissipation capability of the package. Q1 VREF TJ* (1) Q3 RX RD TJ VD V3 θ 1 = 275°C/W V1 θ 2 = 20°C/W PDQ TC PDX RO VN θ 3 = 50°C/W TA RN Q2 V2 VO Q4 FIGURE 3. DIV100 Thermal Model. FIGURE. 4 One-Quadrant Log-Antilog Divider. ® 7 DIV100 R11 7 VREF Output R1 3kΩ 8 VREF Common 10 D Input –VCC 4 Q1 R2 (RX) 14 R7 (RD) A1 + Q3 6 V1 A3 R3 V3 R5 11 1 Q4 R4 9 5 R12 (RO) Q2 – (RN) R6 R13 A2 +VCC 12 V2 R8 3 A4 Rg 2 Output R10 N 13 Input FIGURE 5. DIV100 Two-Quadrant Log-Antilog Circuit. Applying equation (1) to the four logging transistors gives: Still another limitation is that the value of the N input must always be equal to or less than the absolute value of the D input. From equation (3) it can be seen that if this limitation is not met, VO will try to be greater than the 10V output voltage limit of A4. For Q1: VBE = VB – VE = VT[ ln(VREF/RX – ln IS] This leads to: V1 = –VT[ ln(VREF/RX – ln IS] A limitation that may not be obvious is the effect of source resistance. If the numerator or denominator inputs are driven from a source with more than 10Ω of output resistance, the resultant voltage divider will cause a significant output error. This voltage divider is formed by the source resistance and the DIV100 input resistance. With RSOURCE = 10Ω and RINPUT (DIV100) = 25kΩ an error of 0.04% results. This means that the best performance of the DIV100 is obtained by driving its inputs from operational amplifiers. For Q2: V1 – V2 = VT[ ln(VN/RN) – ln IS] For Q3: V3 = –VT[ ln (VD/RD) – ln IS] We have now taken the logarithms of the input voltage VREF, VN, and VD. Applying equation (1) to Q4 gives: V3 – V2 = VT [ ln (VO/RO) – ln IS]. Note that the reference voltage is brought out to pins 7 and 8. This gives the user a precision, temperature-compensated reference for external use. Its open-circuit voltage is +6.8VDC, typically. Its Thevenin equivalent resistance is 3kΩ. Since the output resistance is a relatively high value, an operational amplifier is necessary to buffer this source as shown in Figure 6. The external amplifier is necessary because current drawn through the 3kΩ resistor will effect the DIV100 scale factor. Assume VT and IS are the same for all four transistors (a reasonable assumption with a monolithic IC). Solving this last equation in terms of the previously defined variables and taking the antilogarithm of the result yields: VO = VREF VN RO RD VD RX RN (2) In the DIV100 VREF = 6.6V, RO = RN = RD, and RX is such that the transfer function is: (3) VO = 10N/D where: N = Numerator Voltage D = Denominator Voltage 7 DIV100 Figure 5 is a more detailed circuit diagram for the DIV100. In addition to the circuitry included in Figure 3, it also shows the resistors (R3, R4, R8, R9, and R10) used for level-shifting. This converts the DIV100 to a two-quadrant divider. VREF OPA177 FIGURE 6. Buffered Precision Voltage Reference. The implementation of the transfer function in equation (3) is done using devices with real limitations. For example, the value of the D input must always be positive. If it isn’t, Q3 will no longer conduct, A3 will become open loop, and its output and the DIV100 output will saturate. This limitation is further restricted in that if the D input is less than +250mV the errors will become substantial. It will still function, but its accuracy will be less. OPTION ADJUSTMENTS Figure 7 shows the connections to make to adjust the DIV100 for significantly better accuracy over its 40-to-1 denominator range. ® DIV100 8 8 The adjustment procedure is: The advantage of using the DIV100 can be illustrated from the example shown in Figure 9. 1. Begin with R1, R2, and R3 set to their mid-position. The LVDT (Linear Variable Differential Transformer) weigh cell measures the force exerted on it by the weight of the material in the container. Its output is a voltage proportional to: 2. With |N| = D = 10.000V, ±1mV, adjust R 1 for VO = +10.000V, ±1mV. This sets the scale factor. 3. Set D to the minimum expected denominator voltage. With N = –D, adjust R2 for VO = –10.000V. This adjusts the output referred denominator offset errors. W= 4. With D still at its minimum expected value, make N = D. Adjust R3 for VO = 10.000V. This adjusts the output referred offset errors. where: W = Weight of material F = Force g = Acceleration due to gravity a = Acceleration (acting on body of weight W) 5. Repeat steps 2-4 until the best accuracy is obtained. +VCC –VCC 14 10 3 9 D VO = 10N/D 2 Container DIV100 13 N Fg a R1 20kΩ 1 11 4 10MΩ Force LVDT Weigh Cell 12 10MΩ Control Signal 1.5MΩ Sample/ Hold WINITIAL WINSTANTANEOUS D DIV100 N VOUT FIGURE 9. Weighing System - Fractional Loss. +VCC –VCC R2 10kΩ +VCC In a fractional loss weighting system, the initial value of the material can be determined by the volume of the container and the density of the material. If this value is then held on the D-input to the DIV100 for some time interval, the DIV100 output will be a measure of the instantaneous fractional loss: –VCC R3 10kΩ FIGURE 7. Connection Diagram for Optional Adjustments. Loss (L) = WINSTANTANEOUS/WINITIAL TYPICAL APPLICATIONS Note that by using the DIV100 in this application the common physical parameters of g and a have been eliminated from the measurement, thus eliminating the need for precise system calibration. CONNECTION DIAGRAM Figure 8 is applicable to each application discussed in this section, except the square root mode. +VCC RSOURCE RSOURCE N D 14 The output from a ratiometric measuring system may also be used as a feedback signal in an adaptive process control system. A common application in the chemical industry is in the ratio control of a gas and liquid flow as illustrated in Figure 10. –VCC 10 3 1 13 DIV100 9 2 RSOURCE < 10Ω PERCENTAGE COMPUTATION A variation of the direct ratiometric measurements previously discussed is the need for percentage computation. In Figure 11, the DIV100 output varies as the percent deviation of the measured variable to the standard. VOUT RLOAD ≥ 2kΩ FIGURE 8. Connection Diagram—Divide Mode. TIME AVERAGING The circuit in Figure 12 overcomes the fixed averaging interval and crude approximation of more conventional time averaging schemes. RATIOMETRIC MEASUREMENT The DIV100 is useful for ratiometric measurements such as efficiency, elasticity, stress, strain, percent distortion, impedance magnitude, and fractional loss or gain. These ratios may be made for instantaneous, average, RMS, or peak values. BRIDGE LINEARIZATION The bridge circuit in Figure 13 is fundamental to pressure, force, strain and electrical measurements. It can have one or ® 9 DIV100 Flow-Ratio Receiver-Controller Primary Flow Transmitter (uncontrolled flow) FrC G = 10 VA Measured Variable N VO = Secondary Flow Transmitter (controlled flow) VB DIV100 Anhydrous Hydrochloric Gas D Standard (1% per volt) Absorption Tower Liquid Hydrochloric Acid X 100 Instrumentation Amplifier VB Water Manual (VA –VB) FIGURE 11. Percentage Computation. Ratio-Setting Control Signal Σ DIV100 Error Controller Measurement and Transmission Measurement and Transmission Integrator X Final Control Element N VOUT = X = Reset Control DIV100 T Xdt O Process Ramp Generator D Secondary Variable (controlled) Primary Variable (uncontrolled) FIGURE 12. Time Averaging Computation Circuit. FIGURE 10. Ratio Control of Water to Hydrochloric Gas. more active arms whose resistance is a function of the physical quantity, property, or condition that is being measured; e.g., force of compression. For the sake of explanation, the bridge in Figure 13 has only one active arm. VEX = Excitation Voltage R R A The differential output voltage VBA is: VBA = VB – VA –VEXδ 2(2 + δ) B FIGURE 13. Bridge Circuit. Bridge linearization is accomplished using the circuit in Figure 14. The instrumentation amplifier converts the differential output to a single-ended voltage needed to drive the divider. The voltage-divider string makes the numerator and denominator voltages: N= D= –VEXδ RIN (2R1 + 3RIN)(2 + δ) 2VEX RID (2R1 + 3RID)(2 + δ) +VEX 2R1 R D Instrumentation Amplifier R VA ; and, R1 VO DIV100 R , respectively, RS = R(1 + δ) VB R1 G = 1V/V N RIN = DIV100 numerator input resistance RID = DIV100 denominator input resistance R1 = 1kΩ Applying these voltages to the DIV100 transfer function gives: (2R1 + 3RID)(RINδ) 10 , VO = 10N/D = (2R1 + 3RIN)(2RID) 2R1 FIGURE 14. Bridge Linearization Circuit. which reduces to: VO = –5δ if the divider’s input resistances are equal. ® DIV100 RS = R (1 + δ) R , a nonlinear function of the resistance change in the active arm. This nonlinearity limits the useful span of the bridge to perhaps ±10% variation in the measured parameter. where: 1 T 10 The nonlinearity of the bridge has been eliminated and the circuit output is independent of variations in the excitation voltage. VCONTROL VOUT(s) D DIV100 10N/D N AUTOMATIC GAIN CONTROL A simple AGC circuit using the DIV100 is shown in Figure 15. The numerator voltage may vary both positive and negative. The divider’s output is half-wave rectified and filtered by D1, R3, and C2. It is then compared to the DC reference voltage. If a difference exists, the integrator sends a control signal to the denominator input to maintain a constant output, thus compensating for input voltage changes. R2 OPA627 C R1 VIN(s) VCONTROL ≥ +250mV VOLTAGE-CONTROLLED FILTER Figure 16 shows how to use the DIV100 in the feedback loop of an integrator to form a voltage-controlled filter. The FIGURE 16. Voltage-Controlled Filter. SQUARE ROOT VN N VO DIV100 VOUT = 10N 10N/D D N N ≥ +100mV 13 D1 1 C1 DIV100 12 R3 R2 OPA627 47pF 9 C2 VOUT 2 22Ω R1 Positive DC Reference Voltage FIGURE 17. Connection Diagram for Square Root Mode. FIGURE 15. Automatic Gain Control Circuit. transfer function is: VOUT(S) VIN(S) = K τS + 1 where: K = –R2/R1 τ= 10 R2 C VCONTROL This circuit may be used as a single-pole low-pass active filter whose cutoff frequency is linearily proportional to the circuit’s control voltage. ® 11 DIV100