a FEATURES High Accuracy 0.1% Typical Error High Speed 10 MHz Full-Power Bandwidth 450 V/s Slew Rate 200 ns Settling to 0.1% at Full Power Low Distortion –80 dBc from Any Input Third-Order IMD Typically –75 dBc at 10 MHz Low Noise 94 dB SNR, 10 Hz to 20 kHz 70 dB SNR, 10 Hz to 10 MHz Direct Division Mode 2 MHz BW at Gain of 100 APPLICATIONS High Performance Replacement for AD534 Multiply, Divide, Square, Square Root Modulator, Demodulator Wideband Gain Control, RMS-DC Conversion Voltage-Controlled Amplifiers, Oscillators, and Filters Demodulator with 40 MHz Input Bandwidth PRODUCT DESCRIPTION The AD734 is an accurate high speed, four-quadrant analog multiplier that is pin-compatible with the industry-standard AD534 and provides the transfer function W = XY/U. The AD734 provides a low-impedance voltage output with a fullpower (20 V pk-pk) bandwidth of 10 MHz. Total static error (scaling, offsets, and nonlinearities combined) is 0.1% of full scale. Distortion is typically less than –80 dBc and guaranteed. The low capacitance X, Y and Z inputs are fully differential. In most applications, no external components are required to define the function. The internal scaling (denominator) voltage U is 10 V, derived from a buried-Zener voltage reference. A new feature provides the option of substituting an external denominator voltage, allowing the use of the AD734 as a two-quadrant divider with a 1000:1 denominator range and a signal bandwidth that remains 10 MHz to a gain of 20 dB, 2 MHz at a gain of 40 dB and 200 kHz at a gain of 60 dB, for a gain-bandwidth product of 200 MHz. The advanced performance of the AD734 is achieved by a combination of new circuit techniques, the use of a high speed complementary bipolar process and a novel approach to lasertrimming based on ac signals rather than the customary dc methods. The wide bandwidth (>40 MHz) of the AD734’s input stages and the 200 MHz gain-bandwidth product of the multiplier core allow the AD734 to be used as a low distortion 10 MHz, 4-Quadrant Multiplier/Divider AD734 CONNECTION DIAGRAM 14-Lead DIP (Q Package and N Package) X INPUT X1 1 14 VP POSITIVE SUPPLY X2 2 13 DD DENOMINATOR DISABLE U0 3 DENOMINATOR INTERFACE Y INPUT AD734 12 W OUTPUT U1 4 TOP VIEW 11 Z1 (Not to Scale) 10 Z2 U2 5 Z INPUT Y1 6 9 ER REFERENCE VOLTAGE Y2 7 8 VN NEGATIVE SUPPLY demodulator with input frequencies as high as 40 MHz as long as the desired output frequency is less than 10 MHz. The AD734AQ and AD734BQ are specified for the industrial temperature range of –40°C to +85°C and come in a 14-lead ceramic DIP. The AD734SQ/883B, available processed to MIL-STD-883B for the military range of –55°C to +125°C, is available in a 14-lead ceramic DIP. PRODUCT HIGHLIGHTS The AD734 embodies more than two decades of experience in the design and manufacture of analog multipliers, to provide: 1. A new output amplifier design with more than twenty times the slew-rate of the AD534 (450 V/µs versus 20 V/µs) for a full power (20 V pk-pk) bandwidth of 10 MHz. 2. Very low distortion, even at full power, through the use of circuit and trimming techniques that virtually eliminate all of the spurious nonlinearities found in earlier designs. 3. Direct control of the denominator, resulting in higher multiplier accuracy and a gain-bandwidth product at small denominator values that is typically 200 times greater than that of the AD534 in divider modes. 4. Very clean transient response, achieved through the use of a novel input stage design and wide-band output amplifier, which also ensure that distortion remains low even at high frequencies. 5. Superior noise performance by careful choice of device geometries and operating conditions, which provide a guaranteed 88 dB of dynamic range in a 20 kHz bandwidth. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD734–SPECIFICATIONS (T = +25ⴗC, +V = VP = +15 V, –V = VN = –15 V, R ≥ 2 k⍀) A S S L TRANSFER FUNCTION ( X1 − X 2 )(Y1 − Y 2 ) − ( Z1 − Z2 ) (U1 −U2 ) W = AO Parameter MULTIPLIER PERFORMANCE Transfer Function Total Static Error1 Over TMIN to TMAX vs. Temperature vs. Either Supply Peak Nonlinearity THD2 Feedthrough Noise (RTO) Spectral Density Total Output Noise DIVIDER PERFORMANCE (Y = 10 V) Transfer Function Gain Error X Input Clipping Level U Input Scaling Error3 (Output to 1%) INPUT INTERFACES (X, Y, & Z) 3 dB Bandwidth Operating Range X Input Offset Voltage Conditions A Min Typ Max B Min Typ Max S Min Typ Max Units W = XY/10 0.1 0.4 1 0.004 0.01 0.05 0.05 0.025 –58 –55 –60 –57 –85 –60 –85 –66 W = XY/10 0.1 0.25 0.6 0.003 0.01 0.05 0.05 0.025 –66 –63 –80 –74 –85 –70 –85 –76 W = XY/10 0.1 0.4 1.25 0.004 0.01 0.05 0.05 0.025 –58 –55 –60 –57 –85 –60 –85 –66 % % %/°C %/V % % dBc dBc dBc dBc dBc dBc –10 V ≤ X, Y ≤ 10 V TMIN to T MAX ± VS = 14 V to 16 V –10 V ≤ X ≤ +10 V, Y = +10 V –10 V ≤ Y ≤ +10 V, X = +10 V X = 7 V rms, Y = +10 V, f ≤ 5 kHz TMIN to T MAX Y = 7 V rms, X = +10 V, f ≤ 5 kHz TMIN to T MAX X = 7 V rms, Y = nulled, f ≤ 5 kHz Y = 7 V rms, X = nulled, f ≤ 5 kHz X=Y=0 100 Hz to 1 MHz 10 Hz to 20 kHz TMIN to T MAX 1.0 –94 TMIN to T MAX U = 1 V to 10 V Step, X = 1 V W = XY/U 1 1.25 × U 0.3 1 100 Differential or Common Mode 40 ± 12.5 40 ± 12.5 40 ± 12.5 15 25 10 12 20 50 TMIN to T MAX Z Input Offset Voltage Input Resistance Input Capacitance TMIN to T MAX f ≤ 1 kHz TMIN to T MAX f = 5 kHz 54 50 70 TMIN to T MAX Differential Differential DENOMINATOR INTERFACES (U0, U1, & U2) Operating Range Denominator Range Interface Resistor U1 to U2 OUTPUT AMPLIFIER (W) Output Voltage Swing Open-Loop Voltage Gain Dynamic Response 3 dB Bandwidth Slew Rate Settling Time To 1% To 0.1% Short-Circuit Current POWER SUPPLIES, ± VS Operating Supply Range Quiescent Current –88 –85 W = XY/U 1 1.25 × U 0.15 0.65 100 Y Input Offset Voltage CMRR Input Bias Current (X, Y, Z Inputs) 1.0 –94 –88 –85 W = XY/U 1 1.25 × U 0.3 0.8 100 Y = 10 V, U = 100 mV to 10 V Y ≤ 10 V TMIN to T MAX Z Input PSRR (Either Supply) 1.0 –94 –88 –85 70 85 50 66 56 70 300 400 70 85 50 15 25 10 12 20 90 54 50 70 150 300 70 85 50 300 500 50 2 50 2 50 2 VN to VP-3 1000:1 28 VN to VP-3 1000:1 28 VN to VP-3 1000:1 28 ± 12 TMIN to T MAX X = Y = 0, Input to Z From X or Y Input, CL ≤ 20 pF W ≤ 7 V rms 5 15 5 6 10 50 ± 12 72 8 ± 12 72 10 450 8 10 450 8 µV/√Hz dBc dBc % V % % ns MHz V mV mV mV mV mV mV dB dB dB nA nA kΩ pF V kΩ 72 V dB 10 450 MHz V/µs 125 200 50 80 ns ns mA 9 ± 16.5 12 V mA +20 V or –20 V Output Step TMIN to T MAX 20 125 200 50 TMIN to T MAX ±8 6 9 80 20 ± 16.5 ± 8 12 6 125 200 50 80 9 ± 16.5 ± 8 12 6 20 NOTES 1 Figures given are percent of full scale (e.g., 0.01% = 1 mV). 2 dBc refers to deciBels relative to the full-scale input (carrier) level of 7 V rms. 3 See Figure 10 for test circuit. All min and max specifications are guaranteed. Specifications subject to change without notice. –2– REV. C AD734 ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Internal Power Dissipation2 for TJ max = 175°C . . . . . . . . . . . . . . . . . . . . . . . . 500 mW X, Y and Z Input Voltages . . . . . . . . . . . . . . . . . . . . VN to VP Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite Storage Temperature Range Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Operating Temperature Range AD734A, B (Industrial) . . . . . . . . . . . . . . . –40°C to +85°C AD734S (Military) . . . . . . . . . . . . . . . . . . –55°C to +125°C Lead Temperature Range (soldering 60 sec) . . . . . . . . +300°C Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 V ORDERING GUIDE Model Temperature Range Package Package Description Option AD734AN AD734BN AD734AQ AD734BQ AD734SQ/883B AD734SCHIPS –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –55°C to +125°C –55°C to +125°C Plastic DIP Plastic DIP Cerdip Cerdip Cerdip Die NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. 2 14-Lead Ceramic DIP: θ JA = 110°C/W. CHIP DIMENSIONS & BONDING DIAGRAM Dimensions shown in inches and (mm). (Contact factory for latest dimensions.) REV. C –3– N-14 N-14 Q-14 Q-14 Q-14 AD734 X1 X2 XIF X = X1 – X2 DD DENOMINATOR CONTROL U XZ U ∑ XY/U – Z AO ER W WIF U0 U1 is typically less than 5 mV, which corresponds to a bias current of only 100 nA. This low bias current ensures that mismatches in the sources resistances at a pair of inputs does not cause an offset error. These currents remain low over the full temperature range and supply voltages. HIGH-ACCURACY TRANSLINER MULTIPLIER CORE ∞ The common-mode range of the X, Y and Z inputs does not fully extend to the supply rails. Nevertheless, it is often possible to operate the AD734 with one terminal of an input pair connected to either the positive or negative supply, unlike previous multipliers. The common-mode resistance is several megohms. AD734 Ru U2 Y1 Y2 Z1 YIF Y = Y1 – Y2 Z = Z1 – Z 2 ZIF Z2 Figure 1. AD734 Block Diagram FUNCTIONAL DESCRIPTION Figure 1 is a simplified block diagram of the AD734. Operation is similar to that of the industry-standard AD534 and in many applications these parts are pin-compatible. The main functional difference is the provision for direct control of the denominator voltage, U, explained fully on the following page. Internal signals are actually in the form of currents, but the function of the AD734 can be understood using voltages throughout, as shown in this figure. Pins are named using upper-case characters (such as X1, Z2) while the voltages on these pins are denoted by subscripted variables (for example, X1, Z2). The AD734’s differential X, Y and Z inputs are handled by wideband interfaces that have low offset, low bias current and low distortion. The AD734 responds to the difference signals X = X1 – X2, Y = Y1 – Y2 and Z = Z1 – Z2, and rejects common-mode voltages on these inputs. The X, Y and Z interfaces provide a nominal full-scale (FS) voltage of ± 10 V, but, due to the special design of the input stages, the linear range of the differential input can be as large as ± 17 V. Also unlike previous designs, the response on these inputs is not clipped abruptly above ± 15 V, but drops to a slope of one half. The full-scale output of ± 10 V can be delivered to a load resistance of 1 kΩ (although the specifications apply to the standard multiplier load condition of 2 kΩ). The output amplifier is stable driving capacitive loads of at least 100 pF, when a slight increase in bandwidth results from the peaking caused by this capacitance. The 450 V/µs slew rate of the AD734’s output amplifier ensures that the bandwidth of 10 MHz can be maintained up to the full output of 20 V pk-pk. Operation at reduced supply voltages is possible, down to ±8 V, with reduced signal levels. Available Transfer Functions The uncommitted (open-loop) transfer function of the AD734 is ( X1 − X 2 )(Y1 − Y 2 ) W = AO − ( Z1 − Z 2 ) , U (1) where AO is the open-loop gain of the output op-amp, typically 72 dB. When a negative feedback path is provided, the circuit will force the quantity inside the brackets essentially to zero, resulting in the equation (X1 – X2)(Y1 – Y2) = U (Z1 – Z 2) (2) This is the most useful generalized transfer function for the AD734; it expresses a balance between the product XY and the product UZ. The absence of the output, W, in this equation only reflects the fact that we have not yet specified which of the inputs is to be connected to the op amp output. The bipolar input signals X and Y are multiplied in a translinear core of novel design to generate the product XY/U. The denominator voltage, U, is internally set to an accurate, temperature-stable value of 10 V, derived from a buried-Zener reference. An uncalibrated fraction of the denominator voltage U appears between the voltage reference pin (ER) and the negative supply pin (VN), for use in certain applications where a temperature-compensated voltage reference is desirable. The internal denom-inator, U, can be disabled, by connecting the denominator disable Pin 13 (DD) to the positive supply pin (VP); the denom-inator can then be replaced by a fixed or variable external volt-age ranging from 10 mV to more than 10 V. Most of the functions of the AD734 (including division, unlike the AD534 in this respect) are realized with Z1 connected to W. So, substituting W in place of Z1 in the above equation results in an output. W = ( X1 − X 2 )(Y1 − Y 2 ) + Z U 2. (3) The free input Z2 can be used to sum another signal to the output; in the absence of a product signal, W simply follows the voltage at Z2 with the full 10 MHz bandwidth. When not needed for summation, Z2 should be connected to the ground associated with the load circuit. We can show the allowable polarities in the following shorthand form: The high-gain output op-amp nulls the difference between XY/U and an additional signal Z, to generate the final output W. The actual transfer function can take on several forms, depending on the connections used. The AD734 can perform all of the functions supported by the AD534, and new functions using the direct-division mode provided by the U-interface. ± X )( ±Y ) + ± Z. ( ±W ) = ( ( +U ) Each input pair (X1 and X2, Y1 and Y2, Z1 and Z2) has a differential input resistance of 50 kΩ; this is formed by “real” resistors (not a small-signal approximation) and is subject to a tolerance of ± 20%. The common-mode input resistance is several megohms and the parasitic capacitance is about 2 pF. (4) In the recommended direct divider mode, the Y input is set to a fixed voltage (typically 10 V) and U is varied directly; it may have any value from 10 mV to 10 V. The magnitude of the ratio X/U cannot exceed 1.25; for example, the peak X-input for U = 1 V is ± 1.25 V. Above this level, clipping occurs at the positive and negative extremities of the X-input. Alternatively, The bias currents associated with these inputs are nulled by laser-trimming, such that when one input of a pair is optionally ac-coupled and the other is grounded, the residual offset voltage –4– REV. C AD734 After temperature-correction (block TC), the reference voltage is applied to transistor Qd and trimmed resistor Rd, which generate the required reference current. Transistor Qu and resistor Ru are not involved in setting up the internal denominator, and their associated control pins U0, U1 and U2 will normally be grounded. The reference voltage is also made available, via the 100 kΩ resistor Rr, at Pin 9 (ER); the purpose of Qr is explained below. the AD734 can be operated using the standard (AD534) divider connections (Figure 8), when the negative feedback path is established via the Y2 input. Substituting W for Y2 in Equation (2), we get W =U ( Z2 − Z1) + Y . ( X1 − X 2 ) 1 (5) In this case, note that the variable X is now the denominator, and the above restriction (X/U ≤ 1.25) on the magnitude of the X input does not apply. However, X must be positive in order for the feedback polarity to be correct. Y1 can be used for summing purposes or connected to the load ground if not needed. The shorthand form in this case is ±Z ( ±W ) = ( +U ) ((+ X )) + ( ±Y ). When the control pin DD (denominator disable) is connected to VP, the internal source of Iu is shut off, and the collector current of Qu must provide the denominator current. The resistor Ru is laser-trimmed such that the multiplier denominator is exactly equal to the voltage across it (that is, across pins U1 and U2). Note that this trimming only sets up the correct internal ratio; the absolute value of Ru (nominally 28 kΩ) has a tolerance of ± 20%. Also, the alpha of Qu, (typically 0.995) which might be seen as a source of scaling error, is canceled by the alpha of other transistors in the complete circuit. (6) In some cases, feedback may be connected to two of the available inputs. This is true for the square-rooting connections (Fig-ure 9), where W is connected to both X1 and Y2. Setting X1 = W and Y 2 = W in Equation (2), and anticipating the possibility of again providing a summing input, so setting X2 = S and Y1 = S, we find, in shorthand form ( ±W ) = ( +U )( + Z ) + ( ±S ). In the simplest scheme (Figure 3), an externally-provided control voltage, VG, is applied directly to U0 and U2 and the resulting voltage across Ru is therefore reduced by one VBE . For example, when VG = 2 V, the actual value of U will be about 1.3 V. This error will not be important in some closed-loop applications, such as automatic gain control (AGC), but clearly is not acceptable where the denominator value must be welldefined. When it is required to set up an accurate, fixed value of U, the on-chip reference may be used. The transistor Qr is provided to cancel the VBE of Qu, and is biased by an external resistor, R2, as shown in Figure 4. R1 is chosen to set the desired value of U and consists of a fixed and adjustable resistor. (7) This is seen more generally to be the geometric-mean function, since both U and Z can be variable; operation is restricted to one quadrant. Feedback may also be taken to the U-interface. Full details of the operation in these modes is provided in the appropriate section of this data sheet. Direct Denominator Control NOMINALLY 356mA for U = 10V Iu Iu VG U2 Rr 100kV ER 9 NC Qr VN U2 8 –VS Figure 3. Low-Accuracy Denominator Control Iu U0 3 4 Rr 100kV NC 5 U2 DD 13 R2 ER Ru 28kV +VS VP 14 AD734 Qu U1 LINK TO DISABLE Qd TC Rd NOM 22.5kV 9 ER 9 Qr NOM 8V VN 8 –VS Figure 4. Connections for a Fixed Denominator Qr Table I shows useful values of the external components for setting up nonstandard denominator values. NOM 8V 8 VN 5 NEGATIVE SUPPLY Figure 2. Denominator Control Circuitry REV. C ~60mA Rr 100kV U1 4 Ru 28kV DD 13 Qu U1 NC 4 5 R1 Qu AD734 Ru 28kV 13 DD U0 3 U0 3 14 VP AD734 +VS VP 14 A valuable new feature of the AD734 is the provision to replace the internal denominator voltage, U, with any value from +10 mV to +10 V. This can be used (1) to simply alter the multiplier scaling, thus improve accuracy and achieve reduced noise levels when operating with small input signals; (2) to implement an accurate two-quadrant divider, with a 1000:1 gain range and an asymptotic gain-bandwidth product of 200 MHz; (3) to achieve certain other special functions, such as AGC or rms. Figure 2 shows the internal circuitry associated with denominator control. Note first that the denominator is actually proportional to a current, Iu, having a nominal value of 356 µA for U = 10 V, whereas the primary reference is a voltage, generated by a buriedZener circuit and laser-trimmed to have a very low temperature coefficient. This voltage is nominally 8 V with a tolerance of ± 10%. –5– AD734 Table I. Component Values for Setting Up Nonstandard Denominator Values 5V 3V 2V 1V R1 (Fixed) 34.8 kΩ 64.9 kΩ 86.6 kΩ 174 kΩ R1 (Variable) 20 kΩ 20 kΩ 50 kΩ 100 kΩ X – INPUT 610V FS R2 120 kΩ 220 kΩ 300 kΩ 620 kΩ Y – INPUT 610V FS The denominator can also be current controlled, by grounding Pin 3 (U0) and withdrawing a current of Iu from Pin 4 (U1). The nominal scaling relationship is U = 28 × Iu, where u is expressed in volts and Iu is expressed in milliamps. Note, however, that while the linearity of this relationship is very good, it is subject to a scale tolerance of ± 20%. Note that the common mode range on Pins 3 through 5 actually extends from 4 V to 36 V below VP, so it is not necessary to restrict the connection of U0 to ground if it should be desirable to use some other voltage. The output ER may also be buffered, re-scaled and used as a general-purpose reference voltage. It is generated with respect to the negative supply line Pin 8 (VN), but this is acceptable when driving one of the signal interfaces. An example is shown in Figure 12, where a fixed numerator of 10 V is generated for a divider application. There, Y2 is tied to VN but Y1 is 10 V above this; therefore the common-mode voltage at this interface is still 5 V above VN, which satisfies the internal biasing requirements (see Specifications table). OPERATION AS A MULTIPLIER All of the connection schemes used in this section are essentially identical to those used for the AD534, with which the AD734 is pin-compatible. The only precaution to be noted in this regard is that in the AD534, Pins 3, 5, 9, and 13 are not internally connected and Pin 4 has a slightly different purpose. In many cases, an AD734 can be directly substituted for an AD534 with immediate benefits in static accuracy, distortion, feedthrough, and speed. Where Pin 4 was used in an AD534 application to achieve a reduced denominator voltage, this function can now be much more precisely implemented with the AD734 using alternative connections (see Direct Denominator Control, page 5). 1 X1 VP 14 2 X2 DD 13 NC 3 U0 W 12 4 U1 Z1 11 5 U2 Z2 10 6 Y1 ER 9 NC 7 Y2 VN 8 0.1mF (X1 – X2)(Y1 – Y2) + Z2 W= 10V LOAD L GROUND Z2 OPTIONAL L 0.1mF SUMMING INPUT ±10V FS –15V Figure 5. Basic Multiplier Circuit of 32 Hz. When a tighter control of this frequency is needed, or when the HP corner is above about 100 kHz, an external resistor should be added across the pair of input nodes. At least one of the two inputs of any pair must be provided with a dc path (usually to ground). The careful selection of ground returns is important in realizing the full accuracy of the AD734. The Z2 pin will normally be connected to the load ground, which may be remote, in some cases. It may also be used as an optional summing input (see Equations (3) and (4), above) having a nominal FS input of ± 10 V and the full 10 MHz bandwidth. In applications where high absolute accuracy is essential, the scaling error caused by the finite resistance of the signal source(s) may be troublesome; for example, a 50 Ω source resistance at just one input will introduce a gain error of –0.1%; if both the X- and Y-inputs are driven from 50 Ω sources, the scaling error in the product will be –0.2%. Provided the source resistance(s) are known, this gain error can be completely compensated by including the appropriate resistance (50 Ω or 100 Ω, respectively, in the above cases) between the output W (Pin 12) and the Z1 feedback input (Pin 11). If Rx is the total source resistance associated with the X1 and X2 inputs, and Ry is the total source resistance associated with the Y1 and Y2 inputs, and neither Rx nor Ry exceeds 1 kΩ, a resistance of Rx+Ry in series with pin Z1 will provide the required gain restoration. Pins 9 (ER) and 13 (DD) should be left unconnected in this application. The U-inputs (Pins 3, 4 and 5) are shown connected to ground; they may alternatively be connected to VN, if desired. In applications where Pin 2 (X2) happens to be driven with a high-amplitude, high-frequency signal, the capacitive coupling to the denominator control circuitry via an ungrounded Pin 3 can cause high-frequency distortion. However, the AD734 can be operated without modification in an AD534 socket, and these three pins left unconnected, with the above caution noted. Operation from supplies down to ± 8 V is possible. The supply current is essentially independent of voltage. As is true of all high speed circuits, careful power-supply decoupling is important in maintaining stability under all conditions of use. The decoupling capacitors should always be connected to the load ground, since the load current circulates in these capacitors at high frequencies. Note the use of the special symbol (a triangle with the letter ‘L’ inside it) to denote the load ground. +15V AD734 X – INPUT 610V FS Standard Multiplier Connections Figure 5 shows the basic connections for multiplication. The X and Y inputs are shown as optionally having their negative nodes grounded, but they are fully differential, and in many applications the grounded inputs may be reversed (to facilitate interfacing with signals of a particular polarity, while achieving some desired output polarity) or both may be driven. VP 14 2 X2 DD 13 NC 3 U0 Y – INPUT 610V FS The AD734 has an input resistance of 50 kΩ ± 20% at the X, Y, and Z interfaces, which allows ac-coupling to be achieved with moderately good control of the high-pass (HP) corner frequency; a capacitor of 0.1 µF provides a HP corner frequency 0.1mF 1 X1 L W 12 4 U1 Z1 11 5 U2 Z2 10 6 Y1 ER 9 7 Y2 VN 8 I W = (X1 – X2) (Y1 – Y2) 10V RS NC 0.1mF –15V L LOAD Denominator +15V AD734 L 1 1 + RS 50kV I W 610mA MAX FS 610V MAXIMUM LOAD VOLTAGE Figure 6. Conversion of Output to a Current –6– REV. C AD734 Current Output R2 1.6kV It may occasionally be desirable to convert the output voltage to a current. In correlation applications, for example, multiplication is followed by integration; if the output is in the form of a current, a simple grounded capacitor can perform this function. Figure 6 shows how this can be achieved. The op amp forces the voltage across Z1 and Z2, and thus across the resistor RS, to be the product XY/U. Note that the input resistance of the Z interface is in shunt with RS, which must be calculated accordingly. R1 1.6kV Esinωt C L 3 U0 W 12 R3 13kV 4 U1 Z1 11 E cos2ωt/10V R4 4.32kV 5 U2 Z2 10 6 Y1 ER 9 7 Y2 VN 8 NC 0.1mF 2 L OPERATION AS A DIVIDER The AD734 supports two methods for performing analog division. The first is based on the use of a multiplier in a feedback loop. This is the standard mode recommended for multipliers having a fixed scaling voltage, such as the AD534, and will be described in this Section. The second uses the AD734’s unique capability for externally varying the scaling (denominator) voltage directly, and will be described in the next section. Feedback Divider Connections Figure 8 shows the connections for the standard (AD534) divider mode. Feedback from the output, W, is now taken to the Y2 (inverting) input, which, provided that the X-input is positive, establishes a negative feedback path. Y1 should normally be connected to the ground associated with the load circuit, but may optionally be used to sum a further signal to the output. If desired, the polarity of the Y-input connections can be reversed, with W connected to Y1 and Y2 used as the optional summation input. In this case, either the polarity of the X-input connections must be reversed, or the X-input voltage must be negative. When the input is a sine wave, a squarer behaves as a frequencydoubler, since (8) Equation (8) shows a dc term at the output which will vary strongly with the amplitude of the input, E. This dc term can be avoided using the connection shown in Figure 7, where an RC-network is used to generate two signals whose product has no dc term. The output is AD734 (9) X INPUT +0.1V TO +10V for w = 1/CR1, which is just (10) which has no dc component. To restore the output to ± 10 V when E = 10 V, a feedback attenuator with an approximate ratio of 4 is used between W and Z1; this technique can be used wherever it is desired to achieve a higher overall gain in the transfer function. Y1 OPTIONAL SUMMING INPUT 610V FS In fact, the values of R3 and R4 include additional compensation for the effects of the 50 kΩ input resistance of all three interfaces; R2 is included for a similar reason. These resistor values should not be altered without careful calculation of the consequences; with the values shown, the center frequency f0 is 100 kHz for C = 1 nF. The amplitude of the output is only a weak function of frequency: the output amplitude will be 0.5% too low at f = 0.9f0 and f = 1.1f0. The cross-connection is simply to produce the cosine output with the sign shown in Equation (10); however, the sign in this case will rarely be important. REV. C DD 13 NC –15V Squaring of an input signal, E, is achieved simply by connecting the X and Y inputs in parallel; the phasing can be chosen to produce an output of E2/U or –E2/U as desired. The input may have either polarity, but the basic output will either always be positive or negative; as for multiplication, the Z2 input may be used to add a further signal to the output. W = E2(cos2wt)/( 10 V) VP 14 2 X2 Figure 7. Frequency Doubler Squaring and Frequency-Doubling E π E π 1 W = 4 sin wt + sin wt − 4 2 4 10 V 2 1 X1 L The smallest FS current is simply ± 10 V/50 kΩ, or ± 200 µA, with a tolerance of about 20%. To guarantee a 1% conversion tolerance without adjustment, RS must be less than 2.5 kΩ. The maximum full scale output current should be limited to about ± 10 mA (thus, RS = 1 kΩ). This concept can be applied to all connection modes, with the appropriate choice of terminals. (Esinwt)2 = E2 (1 – cos2wt)/2 +15V 0.1mF AD734 L +15V 1 X1 VP 14 2 X2 DD 13 NC 0.1mF L 3 U0 W 12 4 U1 Z1 11 5 U2 Z2 10 6 Y1 ER 9 NC 0.1mF VN 8 7 Y2 W = 10 (Z2 – Z1) (X1 – X2) +Y1 Z INPUT 610V FS –15V L Figure 8. Standard (AD534) Divider Connection The numerator input, which is differential and can have either polarity, is applied to pins Z1 and Z2. As with all dividers based on feedback, the bandwidth is directly proportional to the denominator, being 10 MHz for X = 10 V and reducing to 100 kHz for X = 100 mV. This reduction in bandwidth, and the increase in output noise (which is inversely proportional to the denominator voltage) preclude operation much below a denominator of 100 mV. Division using direct control of the denominator (Figure 10) does not have these shortcomings. –7– AD734 AD734 S OPTIONAL SUMMING INPUT 610V FS L This connection scheme may also be viewed as a variable-gain element, whose output, in response to a signal at the X input, is controllable by both the Y input (for attenuation, using Y less than U) and the U input (for amplification, using U less than Y). The ac performance is shown in Figure 11; for these results, Y was maintained at a constant 10 V. At U = 10 V, the gain is unity and the circuit bandwidth is a full 10 MHz. At U = 1 V, the gain is 20 dB and the bandwidth is essentially unaltered. At U = 100 mV, the gain is 40 dB and the bandwidth is 2 MHz. Finally, at U = 10 mV, the gain is 60 dB and the bandwidth is 250 kHz, corresponding to a 250 MHz gain-bandwidth product. +15V 0.1mF 1 X1 VP 14 2 X2 DD 13 NC 3 U0 4 U1 Z1 11 5 U2 Z2 10 6 Y1 ER 9 7 Y2 VN 8 L W= D (10V) (Z2 – Z1) + S W 12 Z INPUT +10mV TO +10V NC 0.1mF L –15V Figure 9. Connection for Square Rooting Connections for Square-Rooting 70 GAIN – dB 50 ( X1 − X 2 )(Y1 − Y 2 ) + Z 2, (U1 − U 2 ) 1 X1 X – INPUT U1 U – INPUT U2 Y – INPUT 2MV 3 U0 W 12 4 U1 Z1 11 5 U2 Z2 10 6 Y1 ER 9 7 Y2 VN 8 100k 1M FREQUENCY – Hz 10M Figure 11. Three-Variable Multiplier/Divider Performance The 2 MΩ resistor is included to improve the accuracy of the gain for small denominator voltages. At high gains, the X input offset voltage can cause a significant output offset voltage. To eliminate this problem, a low-pass feedback path can be used from W to X2; see Figure 13 for details. Where a numerator of 10 V is needed, to implement a twoquadrant divider with fixed scaling, the connections shown in Figure 12 may be used. The reference voltage output appearing between Pin 9 (ER) and Pin 8 (VN) is amplified and buffered by the second op amp, to impose 10 V across the Y1/Y2 input. Note that Y2 is connected to the negative supply in this application. This is permissible because the common-mode voltage is still high enough to meet the internal requirements. The transfer function is (11) X − X2 W = 10 V 1 + Z2 . U1 − U 2 (12) The ac performance of this circuit remains as shown in Figure 11. +15V AD734 1 X1 VP 14 2 X2 DD 13 3 U0 W 12 4 U1 Z1 11 X – INPUT U1 0.1mF (X1 – X2) (Y1 – Y2) + Z2 W= U1 – U2 U – INPUT LOAD L GROUND NC U = 10V 10k VP 14 DD 13 U = 1V 0 +15V 2 X2 30 10 where the X, Y, and Z signals may all be positive or negative, but the difference U = U1 – U 2 must be positive and in the range +10 mV to +10 V. If a negative denominator voltage must be used, simply ground the noninverting input of the op amp. As previously noted, the X input must have a magnitude of less than 1.25U. AD734 U = 100mV 40 20 Note that the loading on the output side of the diode will be provided by the 25 kΩ of input resistance at X1 and Y2, and by the user’s load. In high speed applications it may be beneficial to include further loading at the output (to 1 kΩ minimum) to speed up response time. As in previous applications, a further signal, shown here as S, may be summed to the output; if this option is not used, this node should be connected to the load ground. DIVISION BY DIRECT DENOMINATOR CONTROL The AD734 may be used as an analog divider by directly varying the denominator voltage. In addition to providing much higher accuracy and bandwidth, this mode also provides greater flexibility, because all inputs remain available. Figure 10 shows the connections for the general case of a three-input multiplier divider, providing the function W = U = 10mV 60 The AD734 may be used to generate an output proportional to the square-root of an input using the connections shown in Figure 9. Feedback is now via both the X and Y inputs, and is always negative because of the reversed-polarity between these two inputs. The Z input must have the polarity shown, but because it is applied to a differential port, either polarity of input can be accepted with reversal of Z1 and Z2, if necessary. The diode D, which can be any small-signal type (1N4148 being suitable) is included to prevent a latching condition which could occur if the input momentarily was of the incorrect polarity of the input, the output will be always negative. 0.1mF L 2MV 5 U2 U2 Z2 OPTIONAL SUMMING INPUT 610V FS 200kV –15V 100kV SCALE ADJUST 0.1mF W= ER 9 7 Y2 VN 8 U1–U2 +Z 2 LOAD L GROUND Z2 10 6 Y1 (X1– X2) 10V 0.1mF L Z2 OPTIONAL SUMMING INPUT 610V FS –15V OP AMP = AD712 DUAL Figure 10. Three-Variable Multiplier/Divider Using Direct Denominator Control Figure 12. Two-Quadrant Divider with Fixed 10 V Scaling –8– REV. C AD734 The variable denominator of the AD734 and its high gainbandwidth product make it an excellent choice for precise automatic gain control (AGC) applications. Figure 13 shows a suggested method. The input signal, EIN, which may have a peak amplitude of from 10 mV to 10 V at any frequency from 100 Hz to 10 MHz, is applied to the X input, and a fixed positive voltage EC to the Y input. Op amp A2 and capacitor C2 form an integrator having a current summing node at its inverting input. (The AD712 dual op amp is a suitable choice for this application.) In the absence of an input, the current in D2 and R2 causes the integrator output to ramp negative, clamped by diode D3, which is included to reduce the time required for the loop to establish a stable, calibrated, output level once the circuit has received an input signal. With no input to the denominator (U0 and U2), the gain of the AD734 is very high (about 70 dB), and thus even a small input causes a substantial output. C1 1mF A2 +15V 1 X1 VP 14 2 X2 DD 13 3 U0 W 12 NC 4 U1 Z1 11 5 U2 Z2 10 6 Y1 ER 9 7 Y2 VN 8 EC +1V TO +10V +1 D2 1N914 100kHZ 0 –1 1MHZ 100HZ –2 10m 100m 1 INPUT AMPLITUDE – Volts 10 Figure 14. AGC Amplifier Output Error vs. Input Voltage AD734 C2 1mF +2 R3 1MV A1 EIN D3 1N914 The output amplitude tracks EC over the range +1 V to slightly more than +10 V. ERROR – dB A PRECISION AGC LOOP WIDEBAND RMS-DC CONVERTER USING U INTERFACE 0.1mF D1 1N914 EOUT L 0.1mF The AD734 is well suited to such applications as implicit RMSDC conversion, where the AD734 implements the function C1 1mF V RMS = L [ ] avg V IN 2 (13) V RMS using its direct divide mode. Figure 15 shows the circuit. –15V R2 1MV R1 1MV +15V OP AMP = AD712 DUAL Diode D1 and C1 form a peak detector, which rectifies the output and causes the integrator to ramp positive. When the current in R1 balances the current in R2, the integrator output holds the denominator output at a constant value. This occurs when there is sufficient gain to raise the amplitude of EIN to that required to establish an output amplitude of EC over the range of +1 V to +10 V. The X input of the AD734, which has finite offset voltage, could be troublesome at the output at high gains. The output offset is reduced to that of the X input (one or two millivolts) by the offset loop comprising R3, C3, and buffer A1. The low pass corner frequency of 0.16 Hz is transformed to a high-pass corner that is multiplied by the gain (for example, 160 Hz at a gain of 1000). In applications not requiring operation down to low frequencies, amplifier A1 can he eliminated, but the AD734’s input resistance of 50 kΩ between X1 and X2 will reduce the time constant and increase the input offset. Using a non-polar 20 µF tantalum capacitor for C1 will result in the same unity-gain high-pass corner; in this case, the offset gain increases to 20, still very acceptable. Figure 14 shows the error in the output for sinusoidal inputs at 100 Hz, 100 kHz, and 1 MHz, with EC set to +10 V. The output error for any frequency between 300 Hz and 300 kHz is similar to that for 100 kHz. At low signal frequencies and low input amplitudes, the dynamics of the control loop determine the gain error and distortion; at high frequencies, the 200 MHz gain-bandwidth product of the AD734 limit the available gain. REV. C 0.1mF AD734 VIN Figure 13. Precision AGC Loop 1/2 AD708 L 1 X1 VP 14 2 X2 DD 13 3 U0 U2a L L 4 U1 L R1 3.32kV U2b W 12 U1 Z1 11 5 U2 Z2 10 6 Y1 ER 9 7 Y2 VN 8 C1 47mF C2 1mF L L 1/2 AD708 VO = VO VIN 2 0.1mF L –15V Figure 15. A 2-Chip, Wideband RMS-DC Converter In this application, the AD734 and an AD708 dual op amp serve as a 2-chip RMS-DC converter with a 10 MHz bandwidth. Figure 16 shows the circuit’s performance for square-, sine-, and triangle-wave inputs. The circuit accepts signals as high as 10 V p-p with a crest factor of 1 or 1 V p-p with a crest factor of 10. The circuit’s response is flat to 10 MHz with an input of 10 V, flat to almost 5 MHz for an input of 1 V, and to almost 1 MHz for inputs of 100 mV. For accurate measurements of input levels below 100 mV, the AD734’s output offset (Z interface) voltage, which contributes a dc error, must be trimmed out. In Figure 15’s circuit, the AD734 squares the input signal, and its output (VIN2) is averaged by a low-pass filter that consists of R1 and C1 and has a corner frequency of 1 Hz. Because of the implicit feedback loop, this value is both the output value, VRMS, and the denominator in Equation (13). U2a and U2b, an AD708 dual dc precision op amp, serve as unity-gain buffers, supplying both the output voltage and driving the U interface. –9– AD734 100 If the two X1 inputs are at frequencies f1 and f2 and the frequency at the Y1 input is f0, then the two-tone third-order intermodulation products should appear at frequencies 2f1 – f 2 ± f0 and 2f2 – f1 ± f0. Figures 18 and 19 show the output spectra of the AD734 with f1 = 9.95 MHz, f 2 = 10.05 MHz, and f0 = 9.00 MHz for a signal level of f1 & f2 of 6 dBm and f0 of +24 dBm in Figure 18 and f1 & f2 of 0 dBm and f0 of +24 dBm in Figure 19. This performance is without external trimming of the AD734’s X and Y input-offset voltages. OUTPUT VOLTAGE – Volts 10 1 100m The possible Two Tone Intermodulation Products are at 2 × 9.95 MHz – 10.05 MHz ± 9.00 MHz and 2 × 10.05 – 9.95 MHz ± 9.00 MHz; of these only the third-order products at 0.850 MHz and 1.150 MHz are within the 10 MHz bandwidth of the AD734; the desired output signals are at 0.950 MHz and 1.050 MHz. Note that the difference (Figure 18) between the desired outputs and third-order products is approximately 78 dB, which corresponds to a computed third-order intercept point of +46 dBm. 10m SQUARE WAVE SINE WAVE TRI-WAVE 1m 100m 10k 100k 1M INPUT FREQUENCY – Hz 10M Figure 16. RMS-DC Converter Performance LOW DISTORTION MIXER The AD734’s low noise and distortion make it especially suitable for use as a mixer, modulator, or demodulator. Although the AD734’s –3 dB bandwidth is typically 10 MHz and is established by the output amplifier, the bandwidth of its X and Y interfaces and the multiplier core are typically in excess of 40 MHz. Thus, provided that the desired output signal is less than 10 MHz, as would typically be the case in demodulation, the AD734 can be used with both its X and Y input signals as high as 40 MHz. One test of mixer performance is to linearly combine two closely spaced, equal-amplitude sinusoidal signals and then mix them with a third signal to determine the mixer’s 2-tone Third-Order Intermodulation Products. AD734 HP3326A COMBINE A+B AD707 DATEL DVC-8500 HP3326A HIGH VOLTAGE OPTION 1 X1 VP 14 2 X2 DD 13 3 U0 W 12 4 U1 Z1 11 5 U2 Z2 10 6 Y1 ER 9 7 Y2 VN 8 +15V 0.1mF 2kV HP3585A WITH 10X PROBE dBm REF TO 50V Figure 18. AD734 Third-Order Intermodulation Performance for f1 = 9.95 MHz, f 2 = 10.05 MHz, and f0 = 9.00 MHz and for Signal Levels of f1 & f2 of 6 dBm and f0 of +24 dBm. All Displayed Signal Levels Are Attenuated 20 dB by the 10X Probe Used to Measure the Mixer’s Output 0.1mF –15V Figure 17. AD734 Mixer Test Circuit Figure 17 shows a test circuit for measuring the AD734’s performance in this regard. In this test, two signals, at 10.05 MHz and 9.95 MHz are summed and applied to the AD734’s X interface. A second 9 MHz signal is applied to the AD734’s Y interface. The voltage at the U interface is set to 2 V to use the full dynamic range of the AD734. That is, by connecting the W and Z1 pins together, grounding the Y2 and X2 pins, and setting U = 2 V, the overall transfer function is W = X1Y1 2V (14) and W can be as high as 20 V p-p when X1 = 2 V p-p and Y1 = 10 V p-p. The 2 V p-p signal level corresponds to +10 dBm into a 50 Ω input termination resistor connected from X1 or Y1 to ground. Figure 19. AD734 Third-Order Intermodulation Performance for f1 = 9.95 MHz, f 2 = 10.05 MHz, and f0 = 9.00 MHz and for Signal Levels of f1 & f2 of 0 dBm and f0 of +24 dBm. All Displayed Signal Levels Are Attenuated 20 dB by the 10X Probe Used to Measure the Mixer’s Output –10– REV. C 0.06 0.04 0.02 0 –0.02 –0.04 –0.06 –0.08 –2V VS = 615V RLOAD = 2kV CLOAD = 20pF 0.1 0.05 0 –0.05 0.2 0.1 0 –0.1 –0.2 –0.3 –0.1 –0.4 2V 0 SIGNAL AMPLITUDE VS = 615V X = 1.4V RMS Y = 10V RLOAD = 500V CLOAD = 20pF 0.3 GAIN FLATNESS VS = 615V RLOAD = 2kV CLOAD = 20pF DIFFERENTIAL PHASE – Degrees DIFFERENTIAL GAIN – dB Typical Characteristics–AD734 –2V Figure 20. Differential Gain at 3.58 MHz and RL = 2 kΩ 0 SIGNAL AMPLITUDE Figure 21. Differential Phase at 3.58 MHz and R L = 2 kΩ 100 100k 2V 1M FREQUENCY – Hz 10M Figure 22. Gain Flatness, 300 kHz to 10 MHz, RL = 500 Ω 100 0 80 –40 PSRR – dB 80 dB 60 X INPUT, Y = 10V 40 0 1k COMMON-MODE SIGNAL = 7V RMS 10k 60 VN VP 40 0 1k 10M Figure 23. CMRR vs. Frequency 10k 100k 1M FREQUENCY – Hz 1k 10M Figure 24. PSRR vs. Frequency 0 –20 TEST INPUT = 7V RMS OTHER INPUT = 10V DC RLOAD = $2kV –20 X INPUT 10M FREQUENCY = 1MHz VP = 15V VN = –15V RLOAD = 2kV –40 dBc dBc –40 –60 100k 1M FREQUENCY – Hz 0 –20 –40 10k Figure 25. Feedthrough vs. Frequency 0 TEST INPUT = 1V RMS U = 2V OTHER INPUT = 2V DC X INPUT, Y NULLED –80 –100 20 100k 1M FREQUENCY – Hz Y INPUT, X NULLED –60 dBc 20 FEEDTHROUGH – dBc INPUT SIGNAL = 7V RMS Y INPUT, X = 10V X INPUT –60 Y INPUT X INPUT. Y = 10V DC –60 Y INPUT Y INPUT. X = 10V DC –80 1k –80 –80 10k 100k 1M FREQUENCY – Hz 10M 1k 10k 100k 1M FREQUENCY – Hz 10M –100 –10dBm 70.7mV RMS 10dBm 707mV RMS 30dBm 7V RMS SIGNAL LEVEL Figure 26. THD vs. Frequency, U=2V REV. C Figure 27. THD vs. Frequency, U = 10 V –11– Figure 28. THD vs. Signal Level, f = 1 MHz AD734–Typical Characteristics 3 AMPLITUDE – dB 2 1 INCREASING CLOAD 0 –1 –2 –3 0 –30 –60 –90 –120 –150 VS = 615V X = 1.4V rms Y = 10V RLOAD = 500V CLOAD = 20pF, 47pF, 100pF –180 INCREASING CLOAD –4 –5 100k 1M FREQUENCY – Hz 100k 10M 1M FREQUENCY – Hz 10M Figure 31. Pulse Response vs. CLOAD, CLOAD = 0 pF, 47 pF, 100 pF, 200 pF Figure 30. Phase vs. Frequency vs. CLOAD Figure 29. Gain vs. Frequency vs. CLOAD C1442a–0–10/99 VS = 615V X = 1.4V rms Y = 10V RLOAD = 500V CLOAD = 20pF, 47pF, 100pF 4 PHASE SHIFT – Degrees 5 0 20 OUTPUT AMPLITUDE – dB 10 5 0 –5 –10 –15 –10 10 11 12 13 14 15 16 17 18 SUPPLY VOLTAGE – 6VS 20 30 10 5 0 INPUT OFFSET VOLTAGE DRIFT WILL TYPICALLY BE WITHIN SHADED AREA 6 DEVIATION OF INPUT OFFSET VOLTAGE – mV DEVIATION OF INPUT OFFSET VOLTAGE – mV 40 20 0 –20 –5 –40 –10 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE – 8C Figure 34. VOS Drift, X Input INPUT OFFSET VOLTAGE DRIFT WILL TYPICALLY BE WITHIN SHADED AREA 4 2 0 –2 –4 –60 –15 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE – 8C 90 100 8 60 INPUT OFFSET VOLTAGE DRIFT WILL TYPICALLY BE WITHIN SHADED AREA 15 DEVIATION OF INPUT OFFSET VOLTAGE – mV 40 50 60 70 80 Y1 FREQUENCY – MHz Figure 33. Output Amplitude vs. Input Frequency, When Used as Demodulator Figure 32. Output Swing vs. Supply Voltage 20 U = 10V X1 FREQ = Y1 FREQ –1MHz (E.G., Y1 – X1 = 1MHz FOR ALL CURVES) –30 10 9 U = 5V –20 –20 8 U = 2V U = 1V Figure 35. VOS Drift, Z Input –6 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE – 8C Figure 36. VOS Drift, Y Input OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 14-Lead Plastic DIP (N) Package 14 14-Lead Ceramic DIP (Q) Package 8 0.280 (7.11) 0.240 (6.10) PIN 1 1 7 0.325 (8.25) 0.300 (7.62) 0.795 (20.19) 0.725 (18.42) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.130 (3.30) MIN 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) SEATING PLANE –12– REV. C PRINTED IN U.S.A. OUTPUT SWING – Volts 15