ETC DM2223T-12I

DM2223/2233 Multibank Burst EDO EDRAM
512Kb x 8 Enhanced Dynamic RAM
Enhanced
Memory Systems Inc.
Product Specification
Features
8Kbit SRAM Cache Memory for 12ns Random Reads Within Four
Active Pages (Multibank Cache)
■ Fast 4Mbit DRAM Array for 30ns Access to Any New Page
■ Write Posting Register for 12ns Random or Burst Writes Within
a Page
■ 5ns Output Enable Access Time Allows Fast Interleaving
■ Linear or Interleaved Burst Mode Configurable Without Mode
Register Load Cycles
■ Fast Page to Page Move or Read-Modify-Write Cycles
■
On-chip Cache Hit/Miss Comparators Automatically Maintain Cache
Coherency Without External Cache Control
■ Output Latch Enable Allows Extended Data Output (EDO) for
Faster System Operation
■ Hidden Precharge and Refresh Cycles
■ Write-per-bit Option (DM2233) for Parity and Video Applications
■ Extended 64ms Refresh Period for Low Standby Power
■ Low Profile 300-Mil 44-Pin TSOP-II Package
■ Industrial Temperature Range Option
■
Description
The Enhanced Memory Systems 4Mb EDRAM combines raw speed
with innovative architecture to offer the optimum cost-performance
solution for high performance local or main memory in computer and
embedded control systems. In most high speed applications, zero-waitstate operation can be achieved without secondary SRAM cache for
system clock speeds of up to 100MHz without interleaving or 132MHz
with two-way interleaving. The EDRAM outperforms conventional SRAM
cache plus DRAM or synchronous DRAM memory systems by
minimizing wait states on initial reads (hit or miss) and by eliminating
writeback delays. Architectural similarity with JEDEC DRAMs allows a
single memory controller design to support either slow JEDEC DRAMs
or high speed EDRAMs. A system designed in this manner can provide
a simple upgrade path to higher system performance.
The 512K x 8 EDRAM has a control and address interface
compatible with the Enhanced 4M x 1 and 1M x 4 EDRAM products
so that EDRAMs of different organizations can be supported with the
same controller design. The 512K x 8 EDRAM implements the
following additional features which can be supported on new designs:
An optional synchronous burst mode for 100MHz burst transfers
or 132MHz two-way interleaved burst transfers.
■ A controllable output latch provides an extended data (EDO)
mode.
■ Cache size is increased from 2Kbits to 8Kbits. The 8Kbit cache is
organized as four 256 x 8 direct mapped row registers. All row
registers can be accessed without clocking /RE.
■ Concurrent random page write and cache reads from four cache
pages allows fast page-to-page move or read-modify-write cycles.
■
Architecture
The EDRAM architecture includes an integrated SRAM cache
which operates much like a page mode or static column DRAM.
The EDRAM’s SRAM cache is integrated into the DRAM array as
tightly coupled row registers. The 512K x 8 EDRAM has a total of four
independent DRAM memory banks each with its own 256 x 8 SRAM
row register. Memory reads always occur from the cache row register
of one of these banks as specified by column address bits A8 and A9
Pin Configuration
Functional Diagram
/CAL
BE
BM0-2
Column
Address
Latch
and Burst
Control
VCC
A0-A9
Column Decoder
4 - 256 X 8 Cache Pages
(Row Registers)
4 - 9 Bit
Comparators
A0-A10
/F
W/R
/RE
Row Adress
and
Refresh
Control
Row Decoder
Row
Address
Latch
Memory
Array
(2048 X 256 X 8)
A0-A9
Refresh
Counter
The information contained herein is subject to change without notice.
Enhanced reserves the right to change or discontinue this product without notice.
VSS
DQ0
3
4
42
41
/S
A10
W/R
VCC
5
40
A9
6
39
A8
DQ2
7
38
A7
VSS
DQ3
8
37
A6
9
36
A5
DQ0-DQ7
QLE
VCC
10
35
A4
11
34
VSS
12
33
/RE
/S
/G
DQ4
13
32
VSS
14
31
/CAL
VCC
DQ5
15
30
A3
DQ6
16
29
A2
VCC
17
28
A1
DQ7
18
27
A0
VSS
19
26
/WE
BM0
20
25
BM1
VCC
21
24
BE
BM2
22
23
VSS
/G
I/O
Control
and
Data
Latches
4 - Last Row
Read Address
Latches
44
43
DQ1
QLE
Sense Amps
& Column Write Select
1
2
VSS
/F
/WE
VCC
VSS
© 1996 Enhanced Memory Systems Inc., 1850 Ramtron Drive, Colorado Springs, CO
80921
Telephone (719) 481-7000, Fax (719) 488-9095
38-2106-001
(bank select). When the internal comparator detects that the row
address matches the last row read from any of the four DRAM
banks (page hit), only the SRAM is accessed and data is available
on the output pins in 12ns from column address input. Subsequent
reads within the current page or any of the other three active pages
(burst reads or random reads) can continue at 12ns cycle time.
When the row address does not match the last row read from any
of the four DRAM banks (page miss), the new DRAM row is
accessed and loaded into the appropriate SRAM row register and
data is available on the output pins all within 30ns from row
enable. Subsequent reads within the current page or any of the
other three active pages (burst reads or random reads) can
continue at 12ns cycle time. During either read hit or read miss
operations, the EDRAM’s flexible output data latch can be used to
extend data output time so that the entire 100Mbyte/second
bandwidth can be used.
Since reads occur from the SRAM cache, the DRAM precharge
can occur during burst reads. This eliminates the precharge time
delay suffered by other DRAMs and SDRAMs when accessing a new
page. The EDRAM has an independent on-chip refresh counter and
dedicated refresh pin to allow the DRAM array to be refreshed
concurrently with cache read operations (hidden refresh).
During EDRAM read accesses, data can be accessed in either
static column or page mode depending upon the operation of the
/CAL input. If /CAL is held high, new data is accessed with each new
column address (static column mode). If /CAL is brought low
during a read access, the column address is latched and new data
will not be accessed until both the column address is changed and
/CAL is brought high (page mode). A dedicated output enable (/G)
with 5ns access time allows high speed two-way interleave without
an external multiplexer.
Memory writes are posted to the input data latch and directed
to the DRAM array. During a write hit, the on-chip address comparator
activates a parallel write path to the SRAM cache to maintain
coherency. Random or page mode writes can be posted 5ns after
column address and data are available. The EDRAM allows 12ns
page mode cycle time for both write hits and write misses. Memory
writes do not affect the contents of the cache row register except
during a cache hit. Since the DRAM array can be written to at SRAM
speeds, there is no need for complex writeback schemes.
By concurrently accessing any of the EDRAM’s four active read
pages and any write page, data moves or read-modify-write cycles
between rows may be accomplished at page mode speeds without
requiring additional /RE cycles.
An internal burst address counter with burst enable (BE) and
burst mode control (BM0-2) can be used to facilitate all popular
burst read and write sequences. By setting burst type and wrap
length with dedicated control pins, burst mode can be changed
without the mode register loading cycles found in other Burst EDO
or SDRAM parts. As an example, graphic or video applications may
switch back and forth between four word Intel burst write sequences
and full page linear reads without register loading delays. Many
other flexible burst options exist with this form of burst operation
control. If bursting is not desired, it is only necessary to tie BE low.
Four Bank Cache Architecture
Bank 3
Bank 2
Bank 1
Last
Row
Read
Address
Latch
+ 9-Bit
Compare
RA0-10
CA0-7
1M Array
1M Array
1M Array
1M Array
D0-7
Data-In
Latch
CA0-7
256 x 8
Cache
256 x 8
Cache
Bank 0
CA8, CA9
A0-10
Column Address Latch
Row Address Latch
Bank 0
256 x 8
Cache
Bank 1
(0,0)
Bank 2
(0,1)
(1,0)
1 of 4 Selector
CA8, CA9
Data-Out
Latch
CAL
QLE
G
S
Q0-7
3-2
256 x 8
Cache
Bank 3
(1,1)
last row read address latch for the bank specified by row address
A8-9 (LRR: a 9-bit row address latch for each internal DRAM bank
which is reloaded on each /RE active read miss cycle). If the row
address matches the LRR, the requested data is already in the
SRAM cache and no DRAM memory reference is initiated. The data
specified by the row and column address is available at the output
pins at the greater of times tAC or tGQV. Since no DRAM activity is
Functional Description
initiated, /RE can be brought high after time tRE1, and a shorter
The EDRAM is designed to provide optimum memory
precharge time, tRP1, is required. Additional locations within any of
performance with high speed microprocessors. As a result, it is
the four active cache pages may be accessed concurrently with
possible to perform simultaneous operations to the DRAM and
precharge by providing new column addresses and column bank
SRAM cache sections of the EDRAM. This feature allows the EDRAM select bits CA to the multiplex address inputs. New data is
8-9
to hide precharge and refresh operation during reads and
available at the output at time tAC after each column address change
maximize hit rate by maintaining valid cache contents during write in static column mode. During any read cycle, the EDRAM may be
operations even if data is written to another memory page. These
operated in either static column mode with /CAL=high or page
new capabilities, in conjunction with the faster basic DRAM and
mode with /CAL clocked to latch the column address. In page
cache speeds of the EDRAM, minimize processor wait states.
mode, data valid time is determined by either tAC or tCQV.
By integrating the SRAM cache as row registers in the DRAM
array and keeping the on-chip control simple, the EDRAM is able
to provide superior performance without any significant increase in
die size over standard slow 4Mb DRAMs. By eliminating the need
for SRAMs and cache controllers, system cost, board space, and
power can all be reduced.
EDRAM Basic Operating Modes
The EDRAM operating modes are specified in the table below.
Hit and Miss Terminology
In this datasheet, “hit” and “miss” always refer to a hit or miss
to any of the four pages of data contained in the SRAM cache row
registers. There are four cache row registers, one for each of the
four banks of DRAM. These registers are specified by the bank
select column address bits A8 and A9. The contents of these cache
row registers is always equal to the last row that was read from
each of the four internal DRAM banks (as modified by any write hit
data).
Row And Column Addressing
Like common DRAMs, the EDRAM requires the address to be
multiplexed into row and column addresses. Unlike other
memories, the DM2223 and DM2233 allow four read pages (DRAM
pages duplicated in SRAM cache) and one write page to be active at
the same time. To allow any of the four active cache pages to be
accessed quickly, the row address bits A8-9 (DRAM bank selects)
are also duplicated in the column address bits A8-9. This allows any
cache bank to be selected by simply changing the column address.
The write bank address is specified by row address A8-9, and writes
are inhibited when a different column bank select is enabled.
DRAM Read Miss
A DRAM read request is initiated by clocking /RE with W/R low
and /F high. The EDRAM will compare the new row address to the
LRR address latch for the bank specified by row address A8-9 (LRR:
a 9-bit row address latch for each internal DRAM bank which is
reloaded on each /RE active read miss cycle). If the row address
does not match the LRR, the requested data is not in SRAM cache
and a new row is fetched from the DRAM. The EDRAM will load the
new row data into the SRAM cache and update the LRR latch. The
data at the specified column address is available at the output pins
at the greater of times tRAC, tAC, and tGQV. /RE may be brought high
after time tRE since the new row data is safely latched into SRAM
cache. This allows the EDRAM to precharge the DRAM array while
data is accessed from SRAM cache. Additional locations within any
of the four cache pages may be accessed by providing new column
addresses and column bank select bits CA8-9 to the multiplex
address inputs. New data is available at the output at time tAC after
each column address change in static column mode. During any
read cycle, the EDRAM may be operated in either static column
mode with /CAL=high or page mode with /CAL clocked to latch the
column address. In page mode, data valid time is determined by
either tAC or tCQV.
DRAM Write Hit
DRAM Read Hit
A DRAM write request is initiated by clocking /RE while W/R,
A DRAM read request is initiated by clocking /RE with W/R low
and /F high. The EDRAM will compare the new row address to the /WE, and /F are high. The EDRAM will compare the new row
EDRAM Basic Operating Modes
Function
/S
/RE
W/R
/F
A0-10
Read Hit
L
↓
L
H
Row = LRR
No DRAM Reference, Data in Cache
Read Miss
L
↓
L
H
Row ≠ LRR
DRAM Row to Cache
Write Hit
L
↓
H
H
Row = LRR
Write to DRAM and Cache, Reads Enabled
Write Miss
L
↓
H
H
Row ≠ LRR
Write to DRAM, Cache Not Updated, Reads Enabled
Internal Refresh
X
↓
X
L
X
Low Power Standby
H
H
X
X
X
Unallowed Mode
H
L
X
H
X
H = High; L = Low; X = Don’t Care; ↓ = High-to-Low Transition; LRR = Last Row Read
3-3
Comment
1mA Standby Current
address to the LRR address latch for the bank specified by row
address A8-9 (LRR: a 9-bit row address latch for each internal DRAM
bank which is reloaded on each /RE active read miss cycle). If the
row address matches the LRR, the EDRAM will write data to both the
DRAM page in the specified bank and its corresponding SRAM cache
simultaneously to maintain coherency. The write address and data
are posted to the DRAM as soon as the column address is latched by
bringing /CAL low and the write data is latched by bringing /WE low.
The write address and data can be latched very quickly after the fall
of /RE (tRAH + tASC for the column address and tDS for the data).
During a write burst or any page write sequence, the second write
data can be posted at time tRSW after /RE. Subsequent writes within
the page can occur with write cycle time tPC. With /G enabled and /WE
disabled, cache read operations may be performed while /RE is
activated. This allows random read from any of the four cache pages
and random write, read-modify-write, or write-verify to the current
write page with 12ns cycle times. To perform internal memory-tomemory transfers, /WE can be brought low while /G is low to latch
the read data into the write posting register. The read/write transfer
is complete when the new write column address is latched by bringing
/CAL low concurrently with /WE. At the end of any write sequence
(after /CAL and /WE are brought high and tRE is satisfied), /RE can
be brought high to precharge the memory. Reads can be performed
from any of the cache pages concurrently with precharge by providing
the desired column address and column bank select bits CA8-9 to
the multiplex address inputs. During write sequences, a write
operation is not performed unless both /CAL and /WE are low. As a
result, the /CAL input can be used as a byte write select in multi-chip
systems. If /CAL is not clocked on a write sequence, the memory will
perform an /RE only refresh to the selected row and data will
remain unmodified. Writes are inhibited for any write having a
column address bank select different from the bank selected by the
row address.
precharge by providing the desired column address and column
bank select bits CA8-9 to the multiplex address inputs. During write
sequences, a write operation is not performed unless both /CAL and
/WE are low. As a result, /CAL can be used as a byte write select in
multi-chip systems. If /CAL is not clocked on a write sequence, the
memory will perform an /RE only refresh to the selected row and
data will remain unmodified. Writes are inhibited for any write
having a column address bank select different from the bank
selected by the row address.
/RE Inactive Operation
Data may be read from any of the four SRAM cache pages
without clocking /RE. This capability allows the EDRAM to perform
cache read operations during precharge and refresh cycles to
minimize wait states. It is only necessary to select /S and /G and
provide the appropriate column address to read data as shown in the
table below. In this mode of operation, the cache reads may occur
from any of the four pages as specified by column bank select bits
CA8-9. To perform a cache read in static column mode, /CAL is held
high, and the cache contents at the specified column address will be
valid at time tAC after address is stable. To perform a cache read in
page mode, /CAL is clocked to latch the column address.
This option allows the external logic to perform fast hit/miss
comparison so that the time required for row/column multiplexing
is avoided.
Function
/S
/G
/CAL
A0-9
Cache Read (Static Column)
L
L
H
Col Adr
Cache Read (Page Mode)
L
L
↕
Col Adr
EDO and Output Latch Enable Operation
The 512K x 8 EDRAM has an output latch enable (QLE) that
DRAM Write Miss
can
be
used to extend data output valid time. The output latch
A DRAM write request is initiated by clocking /RE while W/R, /WE,
and /F are high. The EDRAM will compare the new row address to the enable operates as shown in the following table.
When QLE is low, the latch is transparent and the EDRAM
LRR address latch for the bank specified by row address A8-9 (LRR:
operates identically to the standard 4M x 1 and 1M x 4 EDRAMs.
a 9-bit row address latch for each internal DRAM bank which is
When /CAL is high during a static column mode read, the QLE input
reloaded on each /RE active read miss cycle). If the row address
does not match the LRR, the EDRAM will write data only to the DRAM can be used to latch the output to extend the data output valid time.
QLE can be held high during page mode reads. In this case, the data
page in the appropriate bank and the contents of the current cache is
not modified. The write address and data are posted to the DRAM as
outputs are latched while /CAL is high and open when /CAL is not high.
soon as the column address is latched by bringing /CAL low and the
write data is latched by bringing /WE low. The write address and data
QLE
/CAL
Comments
can be latched very quickly after the fall of /RE (tRAH + tASC for the
L
X
Output Transparent
column address and tDS for the data). During a write burst or any
page write sequence, the second write data can be posted at time
↕
H
Output Latched When QLE=H (Static Column)
tRSW after /RE. Subsequent writes within the page can occur with
write cycle time tPC. With /G enabled and /WE disabled, cache read
H
↕
Ouput Latched When /CAL=H (Page Mode)
operations may be performed while /RE is activated. This allows
random read accesses from any of the four cache pages and random
When output data is latched and /S goes high, data does not go
writes to the current write page with 12ns cycle times. To perform
internal memory-to-memory transfers, /WE can be brought low while Hi-Z until /G is disabled or either QLE or /CAL goes low to unlatch
/G is low to latch the read data into the write posting register. The
data.
read/ write transfer is complete when the new write column address
Burst Mode Operation
is latched by bringing /CAL low concurrently with /WE. At the end of
Burst mode provides a convenient method for high speed
any write sequence (after /CAL and /WE are brought high and tRE is
satisfied), /RE can be brought high to precharge the memory. Reads sequential reading or writing of data. To enter burst mode, the
starting address, a burst enable signal (BE) and burst mode
can be performed from any of the cache pages concurrently with
3-4
information (BM0-2) as shown in the following table must be
provided. Random accesses using external addresses or new burst
sequences may be performed after a burst sequence is terminated.
To start a burst cycle, BE must be brought high prior to the
falling edge of /CAL. At the falling edge of /CAL, the EDRAM latches
the starting address and the states of the burst mode pins (BM0-2)
which define the type and wrap length of the burst. Once a burst
sequence has been started, the internal address counter increments
with each low to high transition of /CAL. Burst mode is terminated
immediately when either BE goes low or /S goes high (/S must not
go high while /RE is low). Burst mode must be terminated before a
subsequent burst sequence can be initiated. Furthermore, the state
of the address counter is indeterminate following a burst
termination and must be reloaded for a subsequent burst operation.
Burst reads may be performed from any of the four cache pages and
may occur with /RE either active or inactive. As with all writes,
however, burst writes may only be performed to the currently active
write page (defined by the row address) while /RE is active.
Burst mode may be used with or without output latch enable
operation. If burst mode is not used, BE and BM0-2 may be tied to
ground to disable the burst function.
EDRAM Burst Modes
BM2,1,0
Burst Type
Wrap Length
Address Sequence
0-0-0
Linear
2
0-0-1
Linear
4
0-1-0
Linear
8
0-1-1
Linear
Full Page
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
(B)(S),(B)(S+1),…
(B)(255),(B)(0),…
1-0-0
Interleaved
(Scrambled)
2
0-1
1-0
1-0-1
Interleaved
(Scrambled)
4
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
Internal Refresh
If /F is active (low) on the assertion of /RE, an internal refresh
cycle is executed. This cycle refreshes the row address supplied by
an internal refresh counter. This counter is incremented at the end
of the cycle in preparation for the next /F refresh cycle. At least
1,024 /F cycles must be executed every 64ms. /F refresh cycles can
be hidden because cache memory can be read under column
address control throughout the entire /F cycle. /F cycles are the
only active cycles during which /S can be disabled.
/CAL Before /RE Refresh (“/CAS Before /RAS”)
/CAL before /RE refresh, a special case of internal refresh, is
discussed in the “Reduced Pin Count Operation” section below.
/RE Only Refresh Operation
Although /F refresh using the internal refresh counter is the
recommended method of EDRAM refresh, an /RE only refresh may
be performed using an externally supplied row address. /RE refresh
is performed by executing a write cycle (W/R and /F are high)
where /CAL is not clocked. This is necessary so that the current
cache contents and LRR are not modified by the refresh operation.
All combinations of addresses A0-9 must be sequenced every 64ms
refresh period. A10 does not need to be cycled. Read refresh cycles
are not allowed because a DRAM refresh cycle does not occur when
a read refresh address matches the LRR address latch.
Low Power Mode
The EDRAM enters its low power mode when /S is high. In this
mode, the internal DRAM circuitry is powered down to reduce
standby current to 1mA.
a) B=Bank Address, S=Starting Column Address;
Initialization Cycles
A minimum of eight /RE active initialization cycles (read, write,
or refresh) are required before normal operation is guaranteed.
Following these start-up cycles, two read cycles to different row
addresses must be performed for each of the four internal banks of
DRAM to initialize the internal cache logic. Row address bits A8 and
A9 define the four internal DRAM banks.
Unallowed Mode
Read, write, or /RE only refresh operations must not be performed
to unselected memory banks by clocking /RE when /S is high.
b) For BM2,1,0=111, wrap length is 1,024 8-bit words with 256 8-bit words
for each of the four cache blocks. During read or write sequences, the
address count will switch from bank to bank after column address 256.
Write operations, however, will only occur when the internally generated
bank address A8 and A9 matches the row address A8 and A9 that were
loaded when /RE went low.
Reduced Pin Count Operation
Although it is desirable to use all EDRAM control pins to optimize
system performance, the interface to the EDRAM may be simplified to
reduce the number of control lines by either tying pins to ground or
tying one or more control inputs together. The /S input can be tied to
1-1-0
Interleaved
(Scrambled)
8
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
1-1-1
Linear
All Pages
(B)(S),(B)(S+1),…
(B)(255),(B+1)(0),…
NOTES:
Write-Per-Bit Operation
The DM2233 version of the 512Kb x 8 EDRAM offers a write-perbit capability which allows single bits of the memory to be selectively
written without altering other bits in the same word. This capability
may be useful for implementing parity or masking data in video
graphics applications. The bits to be written are determined by a bit
mask data word which is placed on the I/O data pins DQ0-7 prior to
clocking /RE. The logic one bits in the mask data select the bits to be
written. As soon as the mask is latched by an /RE low transition, the
mask data is removed and write data can be placed on the databus.
The mask is only specified on the /RE transition. During page mode
burst write operations, the same mask is used for all write operations.
3-5
/WE — Write Enable
This input controls the latching of write data on the input data
pins. A write operation is initiated when both /CAL and /WE are low.
/G — Output Enable
This input controls the gating of read data to the output data
pins during read operations.
/S — Chip Select
This input is used to power up the I/O and clock circuitry.
When /S is high, the EDRAM remains in its low power mode. /S
must remain active throughout any read or write operation. With the
exception of /F refresh cycles, /RE should never be clocked when /S
is inactive.
DQ0-7 — Data Input/Output
These bidirectional data pins are used to read and write data
to the EDRAM. On the DM2233 write-per-bit memory, these pins
are also used to specify the bit mask used during write operations.
A0-10 — Multiplex Address
These inputs are used to specify the row and column
Pin Descriptions
addresses of the EDRAM data. The 11-bit row address is latched on
/RE — Row Enable
the falling edge of /RE. The 10-bit column address can be specified
This input is used to initiate DRAM read and write operations at any other time to select read data from the SRAM cache or to
and latch a row address as well as the states of W/R and /F. It is not specify the write column address during write cycles. The addition
necessary to clock /RE to read data from any of the SRAM row
of column address bits CA8-9 to specify the desired SRAM bank to
registers. On read operations, /RE can be brought high as soon as be accessed allows quick read access to all four cache pages
data is loaded into cache to allow early precharge.
without the need of performing an /RE cycle.
/CAL — Column Address Latch
QLE — Output Latch Enable
This input is used to latch the column address and in combination
This input enables the output latch. When QLE is low, the
with /WE to trigger write operations. When /CAL is high, the column output latch is transparent. Data is latched when both /CAL and
address latch is transparent. When /CAL transitions low, it latches
QLE are high. This allows output data to be extended during either
the address present while /CAL was high. /CAL can be toggled when static column or page mode read cycles.
/RE is low or high. In burst mode, toggling /CAL will increment the
BE — Burst Enable
internal address counter. However, /CAL must be high during the
This input is used to enable and disable the burst mode
high-to-low transition of /RE except for /F refresh cycles. If QLE is
function.
high during a read, /CAL will hold data output until it transitions
low.
BM0-2 — Burst Mode
These input pins define the burst type and address wrap
W/R — Write/Read
around
length during burst read and write transfers.
This input along with /F specifies the type of DRAM operation
initiated on the low going edge of /RE. When /F is high, W/R
VCC Power Supply
specifies either a write (logic high) or read operation (logic low).
These inputs are connected to the +5 volt power supply.
/F — Refresh
VSS Ground
This input will initiate a DRAM refresh operation using the
These inputs are connected to the power supply ground
internal refresh counter as an address source when /F is low on the
connection.
low going edge of /RE.
ground if low power standby mode is not required. The QLE input can
be tied low if output latching is not required, or tied high if “extended
data out” (hyper page mode) is required. BE can be tied low if burst
operation is not desired. The /CAL and /F pins can be tied together if
hidden refresh operation is not required. In this case, a CBR refresh
(/CAL before /RE) can be performed by holding the combined input
low prior to /RE. A CBR refresh does not require that a row address be
supplied when /RE is asserted. The timing is identical to /F refresh
cycle timing. The /WE input can be tied to /CAL if independent posting
of column addresses and data are not required during write
operations. In this case, both column address and write data will be
latched by the combined input during writes. The W/R and /G inputs
can be tied together if reads are not required during a write cycle. If
these techniques are used, the EDRAM will require only three control
lines for operation (/RE, /CAS [combined /CAL, /F, and /WE], and W/R
[combined W/R and /G]). The simplified control interface still allows
the fast page read/write cycle times, fast random read/write times, and
hidden precharge functions available with the EDRAM.
Pin Names
Pin Names
Function
Pin Names
Function
A0-10
Address Inputs
/WE
Write Enable
DQ0-7
Data In/Data Out
/G
Output Enable
/RE
Row Enable
/F
Refresh Control
/CAL
Column Address Latch
/S
Chip Select
W/R
Write/Read Control
BE
Burst Enable
VCC
Power (+5V)
QLE
Output Latch Enable
VSS
Ground
BM0-2
Burst Mode Control
3-6
Absolute Maximum Ratings
AC Test Load and Waveforms
(Beyond Which Permanent Damage Could Result)
VIN Timing Reference Point at VIL and VIH
Description
VOUT Timing Referenced to 1.5 Volts
5.0V
R1 = 828Ω
Input Voltage (VIN)
- 1 ~ VCC+1
Output Voltage (VOUT)
- 1 ~ VCC+1
- 1 ~ 7v
Power Supply Voltage (VCC)
Output
R2 = 295Ω
Ratings
CL = 50pf
Load Circuit
Ambient Operating Temperature (TA)
-40 ~ +85°C
Storage Temperature (TS)
-55 ~ 150°C
Static Discharge Voltage
(Per MIL-STD-883 Method 3015)
Class 1
Short Circuit O/P Current (IOUT)
50mA*
*One output at a time; short duration.
VIH
VIH
Capacitance
GND
VIL
VIL
≤5ns
≤5ns
Description
Max
Input Capacitance
6pf
A0-10, BE
Input Capacitance
7pf
/RE, /CAL, W/R, W/E, /F, /S, QLE
Input Capacitance
2pf
/G, BM0-2
I/O Capacitance
6pf
DQ0-7
Input Waveforms
Electrical Characteristics
Symbol
TA = 0 to 70°C (Commercial), -40 to 85°C (Industrial)
Parameters
Min
Max
VCC
Supply Voltage
4.75V
5.25V
VIH
Input High Voltage
2.4V
VCC+1
VIL
Input Low Voltage
-1.0V
0.8V
VOH
Output High Level
2.4V
VOL
Output Low Level
Vi(L)
Input Leakage Current
V0(L)
Output Leakage Current
Symbol
Operating Current
Pins
Test Conditions
All Voltages Referenced to VSS
IOUT = - 5mA
0.4V
IOUT = 4.2mA
-10µA
10µA
0V ≤ VIN ≤ 6.5V, All Other Pins Not Under Test = 0V
-10µA
10µA
0V ≤ VIN, 0V ≤ VOUT ≤ 5.5V
33MHz Typ(1)
-12 Max
-15 Max
Test Condition
Notes
ICC1
Random Read
110mA
225mA
180mA
/RE, /CAL, /G and Addresses Cycling: tC = tC Minimum
2, 3
ICC2
Fast Page Mode Read
65mA
145mA
115mA
/CAL, /G and Addresses Cycling: tPC = tPC Minimum
2, 4
ICC3
Static Column Read
55mA
110mA
90mA
/G and Addresses Cycling: tAC = tAC Minimum
2, 4
ICC4
Random Write
135mA
190mA
150mA
/RE, /CAL, /WE and Addresses Cycling: tC = tC Minimum
2, 3
ICC5
Fast Page Mode Write
50mA
135mA
105mA
/CAL, /WE and Addresses Cycling: tPC = tPC Minimum
2, 4
ICC6
Standby
1mA
1mA
1mA
All Control Inputs Stable ≥ VCC - 0.2V, Outputs Driven
ICCT
Average Typical
Operating Current
30mA
—
—
See "Estimating EDRAM Operating Power" Application Note
1
(1) “33MHz Typ” refers to worst case ICC expected in a system operating with a 33MHz memory bus. See power applications note for further details. This parameter is not 100% tested
or guaranteed.
(2) ICC is dependent on cycle rates and is measured with CMOS levels and the outputs open.
(3) ICC is measured with a maximum of one address change while /RE = VIL
(4) ICC is measured with a maximum of one address change while /CAL = VIH
3-7
Switching Characteristics
VCC = 5V ± 5%, ( TA = 0 to 70°C (Commercial), -40 to 85°C (Industrial), CL = 50pf
-12
Symbol
Description
Min
-15
Max
Min
Max
Units
tAC(1)
Column Address Access Time
tACH
Column Address Valid to /CAL Inactive (Write Cycle)
12
15
ns
tACI
Address Valid to /CAL Inactive (QLE High)
12
15
ns
tAHQ
Column Address Hold From QLE High (/CAL=H)
0
0
ns
tAQH
Address Valid to QLE High
12
15
ns
tAQX
Column Address Change to Output Data Invalid
5
5
ns
tASC
Column Address Setup Time
5
5
ns
tASR
Row Address Setup Time
5
5
ns
tBCH
BE Hold From /CAL Low
0
0
ns
tBHS
BE High Setup to /CAL Low
5
5
ns
tBLS
BE Low Setup to /CAL Low (Non-Burst Mode)
7
7
ns
tBP
BE Low Time
5
5
ns
tBQV
Data Out Valid From BE Low (/CAL High, QLE Low)
tBQX
Data Change From BE Low (/CAL High, QLE Low)
5
5
ns
tBSR
BE Low to /RE Setup Time
7
7
ns
tC
Row Enable Cycle Time
55
65
ns
tC1
Row Enable Cycle Time, Cache Hit (Row=LRR), Read Cycle Only
20
25
ns
tCAE
Column Address Latch Active Time
5
6
ns
tCAH
Column Address Hold Time
0
0
ns
tCAH1
Column Address Hold Time - Burst Mode Entry
2
2
ns
tCH
Column Address Latch High Time (Latch Transparent)
5
5
ns
tCHR
/CAL Inactive Lead Time to /RE Inactive (Write Cycles Only)
-2
-2
ns
tCHW
Column Address Latch High to Write Enable Low (Multiple Writes)
0
0
ns
tCLV
Column Address Latch Low to Data Valid (QLE High)
tCQH
Data Hold From /CAL ↓ Transaction (QLE High)
tCQV
Column Address Latch High to Data Valid
tCQX
Column Address Latch Inactive to Data Invalid
5
5
ns
tCRP
Column Address Latch Setup Time to Row Enable
5
5
ns
tCWL
/WE Low to /CAL Inactive
5
5
ns
tDH
Data Input Hold Time
0
0
ns
tDMH
Mask Hold Time From Row Enable (Write-Per-Bit)
1
1.5
ns
tDMS
Mask Setup Time to Row Enable (Write-Per-Bit)
5
5
ns
tDS
Data Input Setup Time
5
5
ns
20
18
7
0
7
0
Output Enable Access Time
tGQX
(2,3)
Output Enable to Output Drive Time
0
5
tGQZ(4,5)
Output Turn-Off Delay From Output Disabled (/G↑)
0
5
tMCH
BM0-2 Mode Hold Time From /CAL Low
0
ns
ns
ns
5
ns
0
5
ns
0
5
ns
5
3-8
ns
ns
15
15
(1)
tGQV
15
12
0
ns
Switching Characteristics (continued)
VCC = 5V ± 5%, ( TA = 0 to 70°C (Commercial), -40 to 85°C (Industrial), CL = 50pf
-12
Symbol
Description
Min
-15
Max
Min
Max
Units
tMCL
BM0-2 Mode to /CAL ↓ Transition
5
5
ns
tMH
/F and W/R Mode Select Hold Time
0
0
ns
tMSU
/F and W/R Mode Select Setup Time
5
5
ns
tNRH
/CAL, /G, and /WE Hold Time For /RE-Only Refresh
0
0
ns
tNRS
/CAL, /G, and /WE Setup Time For /RE-Only Refresh
5
5
ns
tPC
Column Address Latch Cycle Time
12
15
ns
tQCI
QLE High to /CAL Inactive
0
0
ns
tQH
QLE High Time
5
5
ns
tQL
QLE Low Time
5
5
ns
tQQH
Data Hold From QLE Inactive
2
2
ns
tQQV
Data Valid From QLE Low
(1)
7.5
7.5
ns
tRAC
Row Enable Access Time, On a Cache Miss
30
35
ns
tRAC1(1)
Row Enable Access Time, On a Cache Hit (Limit Becomes tAC)
15
17
ns
tRAH
Row Address Hold Time
1
1.5
ns
tRBH
BE Hold Time From /RE
0
0
ns
tRE
Row Enable Active Time
30
tRE1
Row Enable Active Time, Cache Hit (Row=LRR) Read Cycle
tREF
Refresh Period
tRP
Row Precharge Time
tRP1
100000
8
35
100000
ns
10
64
ns
64
ms
20
25
ns
Row Precharge Time, Cache Hit (Row=LRR) Read Cycle
8
10
ns
tRRH
/WE Don’t Care From Row Enable High (Write Only)
0
0
ns
tRSH
Last Write Address Latch to End of Write
12
15
ns
tRSW
Row Enable to Column Address Latch Low For Second Write
35
40
ns
tRWL
Last Write Enable to End of Write
12
15
ns
tSC
Column Address Cycle Time
12
15
ns
tSDC
/S Enable to First /CAL Low
12
15
ns
tSH
/S High to Exit Burst
7
7
ns
tSHR
Select Hold From Row Enable
0
0
ns
tSQV(1)
Chip Select Access Time
tSQX(2,3)
Output Turn-On From Select Low
0
12
tSQZ
(4,5)
Output Turn-Off From Chip Select
0
8
tSSR
Select Setup Time to Row Enable
5
tT
Transition Time (Rise and Fall)
1
tWC
Write Enable Cycle Time
tWCH
Column Address Latch Low to Write Enable Inactive Time
12
3-9
15
ns
0
15
ns
0
10
ns
5
10
1
ns
10
ns
12
15
ns
5
5
ns
Switching Characteristics (continued)
VCC = 5V ± 5%, ( TA = 0 to 70°C (Commercial), -40 to 85°C (Industrial), CL = 50pf
-12
Symbol
Description
Min
-15
Max
Min
Max
Units
tWHR(6)
Write Enable Hold After /RE
0
0
ns
tWI
Write Enable Inactive Time
5
5
ns
tWP
Write Enable Active Time
5
5
ns
tWQV(1)
Data Valid From Write Enable High
tWQX(2,5)
Data Output Turn-On From Write Enable High
0
12
tWQZ(3,4)
Data Turn-Off From Write Enable Low
0
12
tWRP
Write Enable Setup Time to Row Enable
5
12
(1) VOUT Timing Reference Point at 1.5V
(2) Parameter Defines Time When Output is Enabled (Sourcing or Sinking Current) and is Not Referenced to VOH or VOL
(3) Minimum Specification is Referenced from VIH and Maximum Specification is Referenced from VIL on Input Control Signal
(4) Parameter Defines Time When Output Achieves Open-Circuit Condition and is Not Referenced to VOH or VOL
(5) Minimum Specification is Referenced from VIL and Maximum Specification is Referenced from VIH on Input Control Signal
(6) For Write-Per-Bit Devices, tWHR is Limited By Data Input Setup Time, tDS
3-10
15
ns
0
15
ns
0
15
ns
5
ns
/RE Inactive Cache Read Hit (Static Column Mode)
/RE
/F
W/R
A0-9
A0-10
Column 1
Column 2
Column 3
t SC
t SC
t SC
Column 4
/CAL
/WE
t AC
t AC
t AQX
t AQX
DQ0-7
Open
Data 1
t AC
t AC
t AQX
Data 2
Data 3
Data 4
t GQZ
t GQX
t GQV
/G
t SQX
t SQV
t SQZ
/S
Don’t Care or Indeterminate
NOTES: 1. Column address A8-9 specify cache bank accessed on each read.
3-11
/RE Inactive Cache Read Hit (Page Mode)
/RE
/F
W/R
t CAH
A0-9
A0-10
Column 1
Column 2
t ASC
t CAH
t CAE
/CAL
Row
t ASC
t CH
t PC
t CQV
/WE
t AC
t CQX
DQ0-7
Open
Data 1
Data 2
t AC
t GQX
t GQZ
t GQV
/G
t SQX
t SQV
t SQZ
/S
Don’t Care or Indeterminate
NOTES: 1. Column address A8-9 specify cache bank accessed on each read.
3-12
/RE Inactive Cache Read Hit (EDO Mode)
/RE
/F
W/R
t CAH
A0-9
A0-10
Column 1
Column 2
t ASC
t CAH
t CAE
/CAL
A0-10
Row
t ASC
t CH
t PC
t CQV
/WE
t CLV
DQ0-7
Open
t AC
t CLV
t CQH
Data 1
Data 2
t AC
t GQX
t GQZ
t GQV
/G
t SQX
t SQV
t SQZ
/S
QLE
Don’t Care or Indeterminate
NOTES: 1. Column addresses A8-9 specify cache bank accessed on each read.
3-13
/RE Active Cache Read Hit (Static Column Mode)
t C1
t RE1
/RE
t RP1
t MSU
t MH
/F
t MSU
t MH
W/R
t ASR
t RAH
A0-10
A0-9
Row
Column 1
Column 2
Column 3
t SC
t SC
t SC
Column 4
t CRP
/CAL
/WE
t AC
t RAC1
DQ0-7
t AC
t AQX
t AQX
Open
Data 1
t AC
t AC
t AQX
Data 2
Data 3
Data 4
t GQX
t GQZ
t GQV
/G
t SHR
t SSR
t SQZ
/S
t BSR
t RBH
BE
See Burst Timing Diagrams
Don’t Care or Indeterminate
NOTES: 1. Column address A8-9 specify cache bank accessed on each read.
3-14
/RE Active Cache Read Hit (Page Mode)
t C1
t RE1
/RE
t RP1
t MSU
t MH
/F
t MSU
t MH
W/R
t ASR
t RAH
A0-10
Row
t CAH
A0-9
Column 1
Column 2
t ASC
t CRP
t CAH
t CAE
/CAL
Row
t ASC
t CH
t PC
t CQV
/WE
t AC
t CQX
t RAC1
DQ0-7
Open
Data 1
Data 2
t AC
t GQX
t GQZ
t GQV
/G
t SHR
t SSR
t SQZ
/S
tBSR
t RBH
BE
See Burst Timing Diagrams
Don’t Care or Indeterminate
NOTES: 1. Column address A8-9 specify cache bank accessed on each read.
3-15
/RE Active Cache Read Hit (EDO Mode)
t C1
t RE1
/RE
t RP1
t MSU
t MH
/F
t MSU
t MH
W/R
t ASR
t RAH
A0-10
Row
t CAH
Column 1
Column 2
t ASC
t ASC
t CRP
Row
t CAH
t CH
t CAE
/CAL
t PC
t CQV
/WE
t CLV
t RAC1
DQ0-7
Open
t AC
t CLV
t CQH
Data 1
Data 2
t AC
t GQX
t GQZ
t GQV
/G
t SHR
t SSR
t SQZ
/S
QLE
Don’t Care or Indeterminate
NOTES: 1. Latched data becomes invalid when /S is inactive.
2. Column addresses A specify cache bank accessed on each read.
8-9
3-16
/RE Active Cache Read Miss (Static Column Mode)
tC
t RE
/RE
t RP
t MSU
t MH
/F
t MSU
t MH
W/R
t ASR
t RAH
A0-10
A0-10
t SC
Row
A0-9
Column 1
A0-9
Column 2
A0-10
Row
t CRP
/CAL
t AQX
/WE
t AC
t AC
t RAC
DQ0-7
t AQX
Open
Data 1
Data 2
t GQX
t GQV
t GQZ
/G
t SHR
t SSR
t SQZ
/S
t BSR
t RBH
BE
See Burst Timing Diagrams
Don’t Care or Indeterminate
NOTES: 1. Column address A8-9 specify cache bank accessed on each read.
3-17
/RE Active Cache Read Miss (Page Mode)
tC
t RE
/RE
t RP
t MSU
t MH
/F
t MSU
t MH
W/R
t ASR
t RAH
A0-10
A0-10
Row
A0-9
t CAH
A0-9
Column 1
A0-10
Column 2
t ASC
Row
t ASC
t CRP
t CAH
t CAE
/CAL
t CH
t PC
t CQV
/WE
t AC
t CQX
t RAC
Open
DQ0-7
Data 1
Data 2
t AC
t GQZ
/G
t GQX
t SSR
t SHR
t GQV
t SQZ
/S
t BSR
t RBH
BE
See Burst Timing Diagrams
Don’t Care or Indeterminate
NOTES: 1. Column address A8-9 specify cache bank accessed on each read.
3-18
/RE Active Cache Read Miss (EDO Mode)
tC
t RE
/RE
t RP
t MSU
t MH
/F
t MSU
t MH
W/R
t ASR
t RAH
A 0-10
Row
A0-10
A 0-9
t CAH
A 0-9
Column 1
Column 2
t ASC
Row
t ASC
t CRP
t CAH
t CH
t CAE
/CAL
t
PC
t CQV
/WE
t CLV
t RAC
DQ
Open
0-7
t CLV
t AC
t CQH
Data 1
Data 2
t AC
t GQZ
/G
t GQX
t SSR
t SHR
t GQV
t SQZ
/S
QLE
t BSR
t RBH
BE
See Burst Timing Diagrams
NOTES: 1. Latched data becomes invalid when /S is inactive.
2. This is the only valid /RE active read miss timing if EDO option is selected.
3. Column addresses A specify cache bank accessed during read.
8-9
3-19
Don’t Care or Indeterminate
Output Latch Enable Operation (Static Column Mode Read)
/CAL
t AC
A0-9
t AC
Column 1
Column 2
t AQX
t AHQ
DQ 0-7
t QOH
Data 1
Data 2
t AQH
t QQV
t QL
QLE
t QH
Output Latch Enable Operation (Page Mode Read)
t PC
t QCI
t CAE
/CAL
t ACI
t CLV
t AC
A 0-9
t CH
t AC
Column 1
Column 2
t AQX
t CQH
DQ 0-7
Data 1
Data 2
t CQV
QLE
Output Latch Enable Operation (Asynchronous Access)
t PC
t CAE
t CH
/CAL
t QCI
t ACI
A 0-9
t ACI
t ACI
Column 1
Column 2
t CQV
Column 3
t CQV
t AC
t AC
t AC
DQ 0-7
Data 1
t QQH
t QQV
Data 2
t QQV
t QQV
QLE
t QQH
Data 3
t QL
t QH
3-20
Burst-To-Burst Reads Or Writes
BM0-2
Mode and Length
tMCH
CA0-9
Start Address
tAC
tMCL
/CAL
tBCH
tBHS
tCQV
tBP
BE
tCQX
DQ0-7
Qn
QA
QA+1
tCQV
tBQV
/S
tSDC
tSH
tSQV
Previous Burst
New Burst
Burst-To-Random Reads Or Writes
BM0-2
CA0-9
Address (A)
Address (B)
tAC
/CAL
tBCH
tBLS
tCQV
tBCH
BE
tBQX
DQ0-7
Qn
QA
QB
tCQV
tBQV
tAC
Previous Burst
Random Access
NOTES: 1. All relevant timing relationships between CA0-9, /CAL, /WE, and DQ0-7 as shown in other timing diagrams applies to burst mode.
2. Bringing either BE low when /CAL is high or bringing /S high will exit burst mode.
3. /S may only go high when /RE is inactive or during an internal (/F) refresh.
3-21
/RE Inactive Burst Read Hit (EDO Mode)
t
BM
MCH
Mode and Length
t
0-2
AC
t
CAH1
Start Addr.
CA
0-9
t
ASC
t MCL
CAL
t
Random Addr.
t
AC
t
ACI
t
t PC
ACI
t
t
CAE
BLS
CH
t BHS
tBCH
BE
tBP
t CLV
tBQV
tCLV
tCQV
/DQ
tCQH
Qn
Qa+1
Qa
0-7
Qa+1
tSQV
tSH
tCLV
tCLV
tCQH
tSDC
/S
tQCI
QLE
Note: 1. Column addresses A8-9 specify cache bank accessed on cache read.
3-22
tCQV
tCQV
tCQV
tCQV
tCQH
tCQH
Qa+2
tCLV
tBQV
Qa+3
Random Addr.
/RE Active Burst Read Miss (EDO Mode)
t RE
tC
t RAC
t RP
/RE
/F
t MH
t MSU
W/R
A
t AC
t RAH
t ASR
t CAH1
Row
0-10
Start Address
Random Addr.
Mode and Length
BM
0-2
t
ASC
t CRP
t MCH
tACI
tCAE
t MCL
/CAL
t PC
tACI
t CH
tBLS
t WRP
/WE
tCQH
t CQV
tCLV
t GQX
tCLV
tCQH
Qa
/DQ
t CQV
tCQH
Qa+1
t CQV
tCLV
tCQH
tCQV
tCLV
Qa+2
tCLV
Qa+3
Random Data
0-7
t GQV
/G
t SSR
/S
t QCI
/QLE
/BE
t BP
t BQV
t RBH
t BHS
tBCH
Note: 1. Column addresses A8-9 specify cache bank accessed on cache read.
3-23
tBQV
/RE Active Burst Write Followed by Random Read in EDO Mode
tC
t RE
t RSH
t CHR
tRWL
t RSW
/RE
t RP
t MH
t MSU
/F
W/R
A
t ACH
tCAH1
t RAH
t ASR
Row
0-10
tAC
Start Address
Random Addr.
Mode and Length
tMCH
t
ASC
t
t
BM
0-2
t CRP
MCL
tCWL
t PC
t CH
CAE
tACI
tQCI
/CAL
t WCH
t WP
t WRP
t WHR
/WE
tBLS
t CHW
t WC
t DH
tCLV
t DS
Qa
/DQ
tCQV
tWQV
Qa+1
Qa+2
Qa+3
Random Data
0-7
tGQV
/G
t SSR
/S
t RBH
t BSR
/BE
t BP
tBQV
t BHS
/QLE
Note: 1. Column addresses A8-9 must be the same as row addresses A8-9 for writes.
3-24
Burst Write (Hit or Miss) Followed By /RE Inactive Cache Reads
t RE
/RE
t MSU
t RP
t MH
/F
t MSU
t MH
W/R
t ASR
t RAH
A0-10
Row
t CAH
t
A0-9 RSW
A0-9
Column 1
A0-10
t ASC
t CRP
t CAH
/CAL
t ACH
t CAE
t WCH
t WRP
DQ0-7
Open
t CAE
t CH
t PC
t CHW
t CWL
tCHR
t WCH
t RRH
t WP
/WE
t DS
Column n
t RSH
t CWL
t WP
t WHR
A0-9
Column 2
t ACH
t WC
t DH
t WI
t RWL
t DH
t DS
Data 1
Data 2
t WQV
t AC
Cache (Column n)
t GQX
/G
t GQV
t SSR
/S
t BSR
t RBH
BE
See Burst Timing Diagrams
Don’t Care or Indeterminate
3-25
Read/Write During Write Hit Cycle (Can Include Read-Modify-Write)
tC
t RE
/RE
t RP
t MSU
t MH
/F
t MSU
t MH
W/R
t ASR
t CAH
t RAH
A0-10
Row
A0-9
Column 1
t CRP
t AC
A0-9
Column 2
t ACH
t ASC
A0-9
Column 3
t RSH
t CAE
/CAL
t CHR
t WCH
t CQV
t CWL
t WRP
/WE
t WHR
t AC
DQ0-7
t AQX
t RWL
t DS
Read Data
t GQX
t RRH
t WP
t WQV
Write Data
t DH
t GQZ
t GQV
Read Data
t GQZ
t WQX
t GQV
/G
t SSR
/S
t BSR
t RBH
BE
See Burst Timing Diagrams
Don’t Care or Indeterminate
NOTES: 1. If column address one equals column address two, then a read-modify-write cycle is performed.
2. Reads and writes can occur to different banks.
3-26
Memory-To-Memory Transfer (Non-Pipelined)
tRE
/RE
tMSU
tMH
/F
tMSU
tMH
W/R
tASR
tACH
tRAH
A0-7
A8,9
tACH
Read Address
Write
Address
Read Address
Write
Address
Write
Address
ROW
COL X
COL A
COL Y
COL B
COL C
Selected
Write
Bank
Read Bank
Selected
Write Bank
Read Bank
Selected
Write Bank
Selected
Write Bank
RA=R8,9
BA=B1
BA=R8,9
BA=B2
BA=R8,9
tASC
tCRP
/CAL
tACH
tWRP
tAC
tCAH
BA=R8,9
tASC
tCAH
tASC
tCH
tAC
tCAE
tCWL
tWP
tWHR
tCAH
tCH
tCAE
tWI
tWCH
tWP
tRSH
tCHR
tRWL
tWP
tWI
tWCH
tCHR
tCAE
tWCH
/WE
tDS
tCQV
tAQX
DQ0-7
Q(B1,A)
tAQX
tRRH
tDH
Q(B2,Y)
tGQX
tGQV
tDS
Data In
tGQX
tWQZ
tWQZ
tGQV
tGQZ
/G
tSSR
tGQZ
tSHR
/S
tBSR
BE
Don’t Care or Indeterminate
NOTES: 1. Reads may be from any of the cache banks, but writes only occur to the active row latched by /RE.
2. Transfers can be within page, between pages, or between chips.
3-27
Write-Per-Bit Cycle (/G=High)
t RE
t RP
/RE
t RSH
t ACH
t CAE
/CAL
t RAH
t ASC
t ASR
A0-10
t CHR
t CAH
Row
Column
t MSU
t MH
t CWL
W/R
t DMS
DQ0-7
t RWL
t WCH
t DMH
Mask
Data
t DS
t WRP
t DH
/WE
t RRH
t WP
t WHR
t MSU
/F
t SSR
t MH
t SHR
/S
t BSR
t RBH
BE
See Burst Timing Diagrams
Don’t Care or Indeterminate
NOTES: 1. Data mask bit high (1) enables bit write; data mask bit low (0) inhibits bit write.
2. Write-per-bit cycle only valid for DM2233.
3-28
/F Refresh Cycle
t RE
/RE
t MSU
t RP
t MH
/F
Don’t Care or Indeterminate
NOTES: 1. During /F refresh cycles, the status of W/R, /WE, A0-10, /CAL, /S, and /G is a don’t care.
2. /RE inactive cache reads may be performed in parallel with /F refresh cycles.
/RE Only Refresh
t RE
/RE
tC
t RP
t ASR
t RAH
A 0-10
Row
t NRS
t NRH
/CAL, /WE, /G
t MSU
t MH
W/R, /F
t SSR
t SHR
/S
t BSR
t RBH
BE
See Burst Timing Diagrams
Don’t Care or Indeterminate
NOTES: 1. All binary combinations of A0-9 must be refreshed every 64ms interval. A10 does not have to be cycled, but must remain valid
during row address setup and hold times.
2. /RE refresh is write cycle with no /CAL active cycle.
3-29
Mechanical Data
44 Pin 300 Mil Plastic TSOP Package
Inches (mm)
0.741 (18.81) MAX.
0.0315 (0.80) TYP.
0.040 (1.02) TYP.
0.040 (1.02) TYP.
0.040 (1.02) TYP.
7° TYP.
0.044 (1.13) MAX.
0.004 (0.10)
0.000 (0.00)
0.308 (7.82)
0.292 (7.42)
0.016 (0.40)
0.008 (0.20)
0.371 (9.42)
0.355 (9.02)
0.039 (1.00) TYP.
0.039 (1.00)
0.023 (0.60)
0.024 (0.60)
0.016 (0.40)
0.010 (0.24)
0.004 (0.09)
Part Numbering System
DM2223T - 12I
Temperature Range
No Designator = 0 to 70°C (Commercial)
I = -40 to 85°C (Industrial)
Access Time from Cache in Nanoseconds
12ns
15ns
Packaging System
T = 300 Mil, TSOP-II
I/O Width
i.e., Power to Which 2 is Raised for I/O Width (x8)
Special Features Field
2 = No Write Per Bit, Burst Mode
3 = Write Per Bit, Burst Mode
Capacity in Bits
i.e., Power to Which 2 is Raised for Total Capacity
Dynamic Memory
The information contained herein is subject to change without notice. Enhanced Memory Sytems Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in
an Enhanced product, nor does it convey or imply any license under patent or other rights.
3-30