ETC DM512K36ST6-15I

Enhanced
Memory Systems Inc.
Features
DM512K32ST6/DM512K36ST6 Multibank EDO
512Kb x 32/512Kb x 36 EDRAM SIMM
Product Specification
Architecture
The DM512K36ST6
achieves 512K x 36 density by
mounting five 512K x 8
EDRAMs, packaged in 44-pin
plastic TSOP-II packages, on a
multi-layer substrate. Four
2203 devices and one
DM2213 device provide data
and parity storage. The
DM512K32 contains four
2203 devices for data only.
The EDRAM memory
module architecture is very
similar to a standard 2MB
DRAM module with the
addition of an integrated
Description
cache and on-chip control which allows it to operate much like a
The Enhanced Memory Systems 2MB EDRAM SIMM module
page mode or static column DRAM.
provides a single memory module solution for the main memory or
The EDRAM’s SRAM cache is integrated into the DRAM array as
local memory of fast embedded control, DSP, and other high
tightly
coupled row registers. The 512K x 32/36 EDRAM SIMM has a
performance systems. Due to its fast 12ns cache row register, the
total of four independent DRAM memory banks each with its own 256
EDRAM memory module supports zero-wait-state burst read
operations at up to 83MHz bus rates in a non-interleave configuration x 32/36 SRAM row register. Memory reads always occur from the
cache row register of one of these banks as specified by row address
and >100MHz bus rates with a two-way interleave configuration.
bits A8 and A9 (bank select). When the internal comparator detects
On-chip write posting and fast page mode operation supports
that the row address matches the last row read from any of the four
12ns write and burst write operations. On a cache miss, the fast
DRAM array reloads the entire 1KByte cache over a 1KByte-wide bus DRAM banks (page hit), the SRAM is accessed and data is available
in 18ns for an effective bandwidth of 56.8 Gbytes/sec. This means
on the output pins in 12ns from column address input. Subsequent
very low latency and fewer wait states on a cache miss than a nonreads within the page (burst reads or random reads) can continue at
integrated cache/DRAM solution. The JEDEC compatible 72-bit SIMM 12ns cycle time. When the row address does not match the last row
configuration allows a single memory controller to be designed to
read from any of the four DRAM banks (page miss), the new DRAM
support either JEDEC slow DRAMs or high speed EDRAMs to provide row is accessed and loaded into the appropriate SRAM row register
a simple upgrade path to higher system performance.
and data is available on the output pins
all within 30ns from row enable.
Subsequent reads within the page (burst
Functional Diagram
reads or random reads) can continue at
12ns cycle time. During either read hit or
/CAL
Column
0-3, P
A 0 - A7
Address
read miss operations, the EDO option
Latch
Column Decoder
extends data output time to allow use of
4 - 256 X 36 Cache Pages
the full 83Mbyte/second bandwidth.
(Row Registers)
4 - 9 Bit
Comparators
Since reads occur from the SRAM
Sense Amps
cache,
the DRAM precharge can occur
/G
& Column Write Select
A0 - A10
I/O
during
burst reads. This eliminates the
4 - Last Row
Control
Read Address
DQ0-35
and
precharge
time delay suffered by other
Latches
Data
Latches
DRAMs and SDRAMs when accessing a
/S
new page. The EDRAM has an
Memory
Row
/WE
Array
Address
independent on-chip refresh counter and
2Mbyte + Parity
Latch
dedicated refresh control pin to allow the
DRAM array to be refreshed concurrently
with cache read operations (hidden
V
C 1-5
A 0 - A9
V
refresh).
/F
Row Adress
■ 4KByte SRAM Cache Memory for 12ns Random Reads Within Four
Row Decoder
Actives Pages (Multibank Cache)
■ Fast DRAM Array for 30ns Access to Any New Page
■ Write Posting Register for 12ns Random Writes and Burst Writes
Within a Page (Hit or Miss)
■ 1KByte Wide DRAM to SRAM Bus for 56.8 Gigabytes/Sec Cache Fill
■ On-chip Cache Hit/Miss Comparators Maintain Cache Coherency
on Writes
■ EDO Mode for 83 MHz Non-Interleave Burst Rate
■ Hidden Precharge and Refresh Cycles
■ Extended 64ms Refresh Period for Low Standby Power
■ Standard CMOS/TTL Compatible I/O Levels and +5 Volt Supply
■ Compatibility with JEDEC 512K x 32/36 DRAM SIMM Configuration
Allows Performance Upgrade in System
■ Industrial Temperature Range Option
CC
SS
W/R
/RE
and
Refresh
Control
Refresh
Counter
0, 2
The information contained herein is subject to change without notice. Enhanced reserves the
right to change or discontinue this product without notice.
© 1996 Enhanced Memory Sytems Inc, 1850 Ramtron Drive, Colorado Springs, CO
80921
Telephone (800) 545-DRAM; Fax (719) 488-9095; http://www.csn.net/ramtron/enhanced 38-2117-000
During EDRAM read accesses, data is accessed in EDO mode.
The column address is latched on the falling edge of /CAL while the
output data latch is transparent. On the rising edge of /CAL the
output data is latched while the column address latch is
transparent. The EDO mode allows the output data valid time to be
extended so that the next column address can be latched sooner. A
dedicated output enable (/G) with 5ns access time allows high
speed two-way interleave without an external multiplexer.
Memory writes are posted to the input data latch and directed
to the DRAM array. During a write hit, the on-chip address
comparator activates a parallel write path to the SRAM cache to
maintain coherency. Random or page mode writes can be posted
5ns after column address and data are available. The EDRAM
allows 12ns page mode cycle time for both write hits and write
misses. Memory writes do not affect the contents of the cache row
register except during a cache hit. Since the DRAM array can be
written to at SRAM speeds, there is no need for complex writeback
schemes.
By integrating the SRAM cache as row registers in the DRAM
array and keeping the on-chip control simple, the EDRAM is able
to provide superior performance over standard slow 4Mb DRAMs.
By eliminating the need for SRAMs and cache controllers, system
cost, board space, and power can all be reduced.
Functional Description
The EDRAM is designed to provide optimum memory
performance with high speed microprocessors. As a result, it is
possible to perform simultaneous operations to the DRAM and
SRAM cache sections of the EDRAM. This feature allows the EDRAM
to hide precharge and refresh operation during reads and
maximize hit rate by maintaining page cache contents during write
operations even if data is written to another memory page. These
capabilities, in conjunction with the faster basic DRAM and cache
speeds of the EDRAM, minimize processor wait states.
EDRAM Basic Operating Modes
The EDRAM operating modes are specified in the table.
Hit and Miss Terminology
In this datasheet, “hit” and “miss” always refer to a hit or miss
to any of the four pages of data contained in the SRAM cache row
registers. There are four cache row registers, one for each of the
four banks of DRAM. These registers are specified by the bank
select row address bits A8 and A9. The contents of these cache row
registers is always equal to the last row that was read from each of
the four internal DRAM banks (as modified by any write hit data).
DRAM Read Hit
A DRAM read request is initiated by clocking /RE with W/R low
and /F high. The EDRAM will compare the new row address to the
last row read address latch for the bank specified by row address
bits A8-9 (LRR: a 9-bit row address latch for each internal DRAM
bank which is reloaded on each /RE active read miss cycle). If the
row address matches the LRR, the requested data is already in the
SRAM cache and no DRAM memory reference is initiated. The data
specified by the row and column address is available at the output
Four Bank Cache Architecture
Bank 3
Bank 2
Bank 1
A0-10
Column Address Latch
Row Address Latch
Bank 0
Last
Row
Read
Address
Latch
+ 9-Bit
Compare
RA0-10
CA0-7
512K Byte
Array
512K Byte
Array
512K Byte
Array
512K Byte
Array
D0-35
Data-In
Latch
CA0-7
256 x 36
Cache
256 x 36
Cache
Bank 0
256 x 36
Cache
Bank 1
(0,0)
Bank 2
(0,1)
(1,0)
1 of 4 Selector
RA8, RA9
Data-Out
Latch
CAL
0-3, P
G
S
Q 0-35
2-58
256 x 36
Cache
Bank 3
(1,1)
of any write sequence (after /CAL and /WE are brought high and tRE
is satisfied), /RE can be brought high to precharge the memory.
Cache reads can be performed concurrently with precharge (see
“/RE Inactive Operation”). When /RE is inactive, the cache reads
will occur from the page accessed during the last /RE active read
cycle. During write sequences, a write operation is not performed
unless both /CAL and /WE are low. As a result, the /CAL input can
DRAM Read Miss
be used as a byte write select in multi-chip systems.
A DRAM read request is initiated by clocking /RE with W/R low
and /F high. The EDRAM will compare the new row address to the DRAM Write Miss
A DRAM write request is initiated by clocking /RE while W/R,
LRR address latch for the bank specified by row address bits A8-9
/WE, and /F are high. The EDRAM will compare the new row
(LRR: a 9-bit row address latch for each internal DRAM bank
address to the LRR address latch for the bank specified for row
which is reloaded on each /RE active read miss cycle). If the row
address does not match the LRR, the requested data is not in SRAM address bits A8-9 (LRR: a 9-bit row address latch for each internal
cache and a new row is fetched from the DRAM. The EDRAM will
DRAM bank which is reloaded on each /RE active read miss cycle).
load the new row data into the SRAM cache and update the LRR
If the row address does not match any of the LRRs, the EDRAM will
latch. The data at the specified column address is available at the
write data to the DRAM page in the appropriate bank and the
output pins at the greater of times tRAC1, tAC, tGQV, and tASC + tCLV.
contents of the current cache is not modified. The write address
/RE may be brought high after time tRE since the new row data is
and data are posted to the DRAM as soon as the column address is
safely latched into SRAM cache. This allows the EDRAM to
latched by bringing /CAL low and the write data is latched by
precharge the DRAM array while data is accessed from SRAM
bringing /WE low (both /CAL and /WE must be high when initiating
cache. Additional locations within the currently active page may be the write cycle with the falling edge of /RE). The write address and
accessed by providing new column addresses to the multiplex
data can be latched very quickly after the fall of /RE (tRAH + tASC for
address inputs.
the column address and tDS for the data). During a write burst
sequence, the second write data can be posted at time tRSW after
DRAM Write Hit
/RE. Subsequent writes within a page can occur with write cycle
A DRAM write request is initiated by clocking /RE while W/R,
time tPC. During a write miss sequence cache reads are inhibited
/WE, and /F are high. The EDRAM will compare the new row
and the output buffers are disabled (independently of /G) until
address to the LRR address latch for the bank specified by row
address bits A8-9 (LRR: a 9-bit row address latch for each internal time tWRR after /RE goes high. At the end of a write sequence (after
DRAM bank which is reloaded on each /RE active read miss cycle). /CAL and /WE are brought high and tRE is satisfied), /RE can be
If the row address matches the LRR, the EDRAM will write data to
brought high to precharge the memory. Cache reads can be
both the DRAM page in the appropriate bank and its corresponding performed concurrently with the precharge (see “/RE Inactive
SRAM cache simultaneously to maintain coherency. The write
Operation”). When /RE is inactive, the cache reads will occur from
address and data are posted to the DRAM as soon as the column
the page accessed during the last /RE active read cycle. During
address is latched by bringing /CAL low and the write data is
write sequences, a write operation is not performed unless both
latched by bringing /WE low (both /CAL and /WE must be high
/CAL and /WE are low. As a result, /CAL can be used as a byte write
when initiating the write cycle with the falling edge of /RE). The
select in multi-chip systems.
write address and data can be latched very quickly after the fall of
/RE Inactive Operation
/RE (tRAH + tASC for the column address and tDS for the data).
Data may be read from the SRAM cache without clocking /RE.
During a write burst sequence, the second write data can be posted
This capability allows the EDRAM to perform cache read
at time tRSW after /RE. Subsequent writes within a page can occur
operations during precharge and refresh cycles to minimize wait
with write cycle time tPC. With /G enabled and /WE disabled, read
states. It is only necessary to select /S and /G and provide the
operations may be performed while /RE is activated in write hit
mode. This allows read-modify-write, write-verify, or random read- appropriate column address to read data. In this mode of
write sequences within the page with 12ns cycle times. At the end
operation, the cache reads will occur from the page accessed
pins at the greater of times tRAC1, tAC, tGQV, and tASC + tCLV. Since no
DRAM activity is initiated, /RE can be brought high after time tRE1,
and a shorter precharge time, tRP1, is required. Additional locations
within the currently active page may be accessed concurrently with
precharge by providing new column addresses to the multiplex
address inputs.
EDRAM Basic Operating Modes
Function
/S
/RE
W/R
/F
A0-10
Read Hit
L
↓
L
H
Row = LRR
No DRAM Reference, Data in Cache
Read Miss
L
↓
L
H
Row ≠ LRR
DRAM Row to Cache
Write Hit
L
↓
H
H
Row = LRR
Write to DRAM and Cache, Reads Enabled
Write Miss
L
↓
H
H
Row ≠ LRR
Write to DRAM, Cache Not Updated, Reads Disabled
Internal Refresh
X
↓
X
L
X
Cache Reads Enabled
Low Power Standby
H
H
X
X
X
Standby Current
Unallowed Mode
H
L
X
H
X
H = High; L = Low; X = Don’t Care; ↓ = High-to-Low Transition; LRR = Last Row Read
2-59
Comment
during the last /RE active read cycle. /CAL is clocked to latch the
column address and data.
This option is desirable when the external control logic is
capable of fast hit/miss comparison. In this case, the controller
can avoid the time required to perform row/column multiplexing
on hit cycles.
EDO Mode Operation
The EDRAM SIMM has an on-board data latch to latch output
data from the SRAM cache while a new cache address is being
specified. EDO mode pipelines the fetching of new data from the
cache with the transfer of the previous data to the bus. EDO allows
non-interleave data transfers at up to a 83 MHz data rate. In this
mode, static column and page mode read operations are not
supported. All read operations require /CAL to be clocked to latch
the input address and enable the output data to propagate through
the output latch to the output pins.
Write-Per-Bit Operation
The DM512K36ST6 SIMM provides a write-per-bit capability
to selectively modify individual parity bits (DQ8, 17, 26, 35) for byte
write operations. The parity device (DM2213) is selected via
/CALP. Byte write selection to non-parity bits is accomplished via
CAL0-3. The bits to be written are determined by a bit mask data
word which is placed on the parity I/O data pins prior to clocking
/RE. The logic one bits in the mask data select the bits to be
written. As soon as the mask is latched by /RE, the mask data is
removed and write data can be placed on the databus. The mask
is only specified on the /RE transition. During page mode write
operations, the same mask is used for all write operations.
Initialization Cycles
A minimum of eight /RE active initialization cycles (read,
write, or refresh) are required before normal operation is
guaranteed. Following these start-up cycles, two read cycles to
different row addresses must be performed for each of the four
internal banks of DRAM to initialize the internal cache logic. Row
address bits A8 and A9 define the four internal DRAM banks.
Unallowed Mode
Read, write, or /RE only refresh operations must not be
initiated to unselected memory banks by clocking /RE when /S is
high.
Reduced Pin Count Operation
It is possible to simplify the interface to the 2MByte SIMM to
reduce the number of control lines. /RE0 and /RE2 could be tied
together externally to provide a single row enable. W/R and /G can
be tied together if reads are not performed during write hit cycles.
This external wiring simplifies the interface without any
performance impact.
Pin Descriptions
/RE0,2 — Row Enable
These inputs are used to initiate DRAM read and write
operations and latch a row address and the states of W/R and /F. It
is not necessary to clock /RE to read data from the EDRAM SRAM
row registers. On read operations, /RE can be brought high as
soon as data is loaded into cache to allow early precharge.
Internal Refresh
If /F is active (low) on the assertion of /RE, an internal refresh
cycle is executed. This cycle refreshes the row address supplied by
an internal refresh counter. This counter is incremented at the end
of the cycle in preparation for the next /F refresh cycle. At least
1,024 /F cycles must be executed every 64ms. /F refresh cycles can
be hidden because cache memory can be read under column
address control throughout the entire /F cycle. /F cycles are the
only active cycles where /S can be disabled.
/RE Only Refresh Operation
Although /F refresh using the internal refresh counter is the
recommended method of EDRAM refresh, it is possible to perform
an /RE only refresh using an externally supplied row address. /RE
refresh is performed by executing a write cycle (W/R and /F are
high) where /CAL is not clocked. This is necessary so that the
current cache contents and LRR are not modified by the refresh
operation. All combinations of addresses A0-9 must be sequenced
every 64ms refresh period. A10 does not need to be cycled. Read
refresh cycles are not allowed because a DRAM refresh cycle does
not occur when a read refresh address matches the LRR address
latch.
Low Power Mode
The EDRAM enters its low power mode when /S is high. In
this mode, the internal DRAM circuitry is powered down to reduce
standby current.
/CAL 0-3, P — Column Address Latch
These inputs are used to latch the column address and in
combination with /WE to trigger write operations. When /CAL is
high, the column address latch is transparent. When /CAL is low,
the column address is closed and the output of the latch contains
the address present while /CAL was high. /CAL can be toggled
when /RE is low or high. However, /CAL must be high during the
high-to-low transition of /RE except for /F refresh cycles. The
output data is latched when /CAL is high.
W/R — Write/Read
This input along with /F specifies the type of DRAM operation
initiated on the low going edge of /RE. When /F is high, W/R
specifies either a write (logic high) or read operation (logic low).
/F — Refresh
This input will initiate a DRAM refresh operation using the
internal refresh counter as an address source when /F is low on
the low going edge of /RE.
/WE — Write Enable
This input controls the latching of write data on the input data
pins. A write operation is initiated when both /CAL and /WE are
low.
/G — Output Enable
This input controls the gating of read data to the output data
pins during read operations.
/S — Chip Select
This input is used to power up the I/O and clock circuitry.
When /S is high, the EDRAM remains in its low power mode. /S
2-60
U1
Byte 3
Byte 4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
W/R
/WE
/F
/S
/G
43
26
2
42
12
10
24
W/R
/WE
/F
/S
/G
QLE
/HIT
DM2203T
512K x 8
10
11
30
59
66
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
DM2213T
512K x 8
32
/RE
/CAL0
/CAL1
/CAL2
/CAL3
/CALP
/RE0
/RE2
C1
C2
C3
C4
C5
PD
*DM2213 and R1-4 are not present on the DM512K32ST6.
2-61
R4*
R3*
VCC
VCC
VCC
VCC
VCC
VCC
1
5
11
17
22
31
VSS
VSS
VSS
VSS
VSS
VSS
VSS
3
8
14
19
23
34
44
/RE
33
/RE
33
32
33
/RE
/CAL
32
33
32
R6 - R10
/RE
/CAL
EDRAM
/CAL
EDRAM
EDRAM
/CAL
EDRAM
33
DM2203T
512K x 8
EDRAM
/CAL
DM2203T
512K x 8
32
Byte 1
4
6
7
9
13
15
16
18
+5V
/CAL0
/CAL1
/CAL2
/CAL3
/CALP
/RE0
/RE2
R2*
R1*
4
6
7
9
13
15
16
18
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
4
6
7
9
13
15
16
18
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
27
28
29
30
35
36
37
38
39
40
41
Byte 2
4
6
7
9
13
15
16
18
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
4
6
7
9
13
15
16
18
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U4
DM2203T
512K x 8
+5V
U3
Parity*
U5
40
43
41
42
46
44
34
70
DQ8
DQ17
DQ26
DQ35
100KΩ
100KΩ
1
29
39
71
72
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
+5V
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
48
47
68
69
67
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
2
4
6
8
20
22
24
26
36
49
51
53
55
57
61
63
65
37
3
5
7
9
21
23
25
27
35
50
52
54
56
58
60
62
64
38
12
13
14
15
16
17
18
28
31
32
19
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Edge
Connecter
J1
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
Interconnect Diagram
Pinout
Interconnect
Pin No. Function (Component Pin)
Organization
C (3, 8, 14, 19,
1
GND
23, 34, 44) Ground
U1 (4)
Byte 1 I/O 1
2
DQ0
Interconnect
Pin No. Function (Component Pin)
37
DQ17*
U3 (6)
38
DQ35*
Organization
Parity I/O for Byte 2
3
DQ18
U4 (4)
Byte 3 I/O 1
39
GND
U3 (9)
Parity I/O for Byte 4
C (3, 8, 14, 19, Ground
23, 34, 44)
4
DQ1
U1 (6)
Byte 1 I/O 2
40
/CAL 0
U1 (32)
Byte 1 Column Address Latch
5
DQ19
U4 (6)
Byte 3 I/O 2
41
/CAL 2
U4 (32)
Byte 3 Column Address Latch
6
DQ2
U1 (7)
Byte 1 I/O 3
42
/CAL 3
U5 (32)
Byte 4 Column Address Latch
7
DQ20
U4 (7)
Byte 3 I/O 3
43
/CAL 1
U2 (32)
Byte 2 Column Address Latch
8
DQ3
U1 (9)
Byte 1 I/O 4
44
/RE0
U1, 2 (33)
Row Enable (Bytes 1,2)
9
DQ21
45
NC
46
/CAL P*
U3 (32)
Parity Column Address Latch
47
/WE
C (26)
Write Enable
48
W/R
C (43)
W/R Mode Control
10
+5 Volts
11
+5 Volts
12
A0
U4 (9)
Byte 3 I/O 4
C (1, 5,11, 17,
VCC
22, 31)
C (1, 5, 11, 17, V
CC
22, 31)
C (27)
Address
13
A1
C (28)
Address
49
DQ9
U2 (4)
Byte 2 I/O 1
14
A2
C (29)
Address
50
DQ27
U5 (4)
Byte 4 I/O 1
15
A3
C (30)
Address
51
DQ10
U2 (6)
Byte 2 I/O 2
16
A4
C (35)
Address
52
DQ28
U5 (6)
Byte 4 I/O 2
17
A5
C (36)
Address
53
DQ11
U2 (7)
Byte 2 I/O 3
18
A6
C (37)
Address
54
DQ29
U5 (7)
Byte 4 I/O 3
19
A 10
C (41)
Address
55
DQ12
U2 (9)
Byte 2 I/O 4
20
DQ4
U1 (13)
Byte 1 I/O 5
56
DQ30
U5 (9)
Byte 4 I/O 4
21
DQ22
U4 (13)
Byte 3 I/O 5
57
DQ13
U2 (13)
Byte 2 I/O 5
22
DQ5
U1 (15)
Byte 1 I/O 6
58
DQ31
23
DQ23
U4 (15)
Byte 3 I/O 6
59
+5 Volts
U5 (13)
Byte 4 I/O 5
C (1, 5, 11, 17,
VCC
22, 31)
24
DQ6
U1 (16)
Byte 1 I/O 7
60
DQ32
U5 (15)
Byte 4 I/O 6
25
DQ24
U4 (164
Byte 3 I/O 7
61
DQ14
U2 (15)
Byte 2 I/O 6
26
DQ7
U1 (18)
Byte 1 I/O 8
62
DQ33
U5 (16)
Byte 4 I/O 7
27
DQ25
U4 (18)
Byte 3 I/O 8
63
DQ15
U2 (16)
Byte 2 I/O 7
28
A7
64
DQ34
U5 (18)
Byte 4 I/O 8
29
GND
65
DQ16
30
+5 Volts
C (38)
Address
C (3, 8, 14, 19,
23, 34, 44) Ground
C (1, 5, 11, 17,
VCC
22, 31)
66
+5 Volts
U2 (18)
Byte 2 I/O 8
C (1, 5, 11, 17,
VCC
22, 31)
31
A8
C (39)
Address
67
/G
C (12)
Output Enable
32
A9
C (40)
Address
68
/F
C (2)
Refresh Mode Control
33
NC
Reserved for 2Mb x 36
69
/S
C (42)
Chip Select
34
/RE2
U3, 4, 5 (33)
Row Enable (Bytes 3,4, Parity)
70
PD
35
DQ26*
U3 (7)
Parity I/O for Byte 3
71
GND
36
DQ8 *
U3 (4)
Parity I/O for Byte 1
72
GND
Signal GND
Presence Detect
C (3, 8, 14, 19,
23, 34, 44) Ground
C (3, 8, 14, 19
33, 34, 44) Ground
*No Connect for DM512K32ST6
C = Common to All Memory Chips, U1 = Chip 1, etc.
2-62
Reserved for 2Mb x 36
VCC Power Supply
These inputs are connected to the +5 volt power supply.
VSS Ground
These inputs are connected to the power supply ground
connection.
must remain active throughout any read or write operation. With
the exception of /F refresh cycles, /RE should never be clocked
when /S is inactive.
DQ0-35 — Data Input/Output
These bidirectional data pins are used to read and write data
to the EDRAM. On the DM512K36 SIMM, the parity pins are also
used to specify the bit mask used during parity write operations.
A0-10 — Multiplex Address
These inputs are used to specify the row and column
addresses of the EDRAM data. The 11-bit row address is latched on
the falling edge of /RE. The 8-bit column address can be specified
at any other time to select read data from the SRAM cache or to
specify the write column address during write cycles.
Absolute Maximum Ratings
Capacitance
(Beyond Which Permanent Damage Could Result)
Description
Ratings
Description
Max*
Input Voltage (VIN )
- 1 ~ 7v
Input Capacitance
22/24pf
A0-10
Output Voltage (VOUT )
- 1 ~ 7v
Input Capacitance
16pf
/RE0
Power Supply Voltage (VCC )
- 1 ~ 7v
Input Capacitance
14/18pf
/RE2
Ambient Operating Temperature (TA )
-40 ~ 85°C
Input Capacitance
17pf
/G
Storage Temperature (TS )
-55 ~ 150°C
I/O Capacitance
9pf
DQ0-35
Pins
Static Discharge Voltage
(Per MIL-STD-883 Method 3015)
Class 1
Input Capacitance
10pf
/CAL0-3, P
Short Circuit O/P Current (I OUT )
50mA*
Input Capacitance
24pf
W/R, /WE, /F, /S
* One output at a time per device; short duration
* DM512K32ST6/DM512K36ST6, respectively
AC Test Load and Waveforms
Load Circuit
VIN Timing Reference Point at VIL and VIH
VOUT Timing Referenced to 1.5 Volts VIH
Input Waveforms
5.0V
VIH
R1 = 828Ω
VIH
Output
R 2 = 295 Ω
C L = 50pf
GND
VIL
VIL
≤ 5ns
2-63
≤ 5ns
Electrical Characteristics
(TA = 0 to 70°C, Commercial; -40 to 85°C, Industrial)
Symbol
Parameters
Min
Max
VCC
Supply Voltage
4.75V
5.25V
VIH
Input High Voltage
2.4V
6.5V
V IL
Input Low Voltage
-1.0V
0.8V
VOH
Output High Level
2.4V
VOL
Output Low Level
I i(L)
Input Leakage Current
-50µA
-50µA
OV ≤ V IN ≤ 6.5V, All Other Pins Not Under Test = 0V
I O(L)
Output Leakage Current
-50µA
-50µA
OV ≤ V IN , OV ≤ VOUT ≤ 5.5V
Test Conditions
All Voltages Referenced to VSS
IOUT = - 5mA
0.4V
IOUT = 4.2mA
Operating Current — DM512K32ST6
Symbol
Operating Current
33MHz Typ (1) -12 Max
-15 Max
Test Condition
Notes
ICC1
Random Read
440mA
900mA
720mA
/RE, /CAL, /G and Addresses Cycling: tC = tC Minimum
2, 3
ICC2
Fast Page Mode Read
260mA
580mA
460mA
/CAL, /G and Addresses Cycling: tPC = tPC Minimum
2, 4
ICC3
Static Column Read
220mA
440mA
360mA
/G and Addresses Cycling: t SC = t SC Minimum
2, 4
ICC4
Random Write
540mA
760mA
600mA
/RE, /CAL, /WE and Addresses Cycling: t C = t C Minimum
2, 3
ICC5
Fast Page Mode Write
200mA
540mA
420mA
/CAL, /WE and Addresses Cycling: tPC = tPC Minimum
2, 4
ICC6
Standby
4mA
4mA
4mA
All Control Inputs Stable ≥ VCC - 0.2V, Outputs Driven
ICCT
Average Typical
Operating Current
120mA
—
—
See "Estimating EDRAM Operating Power" Application Note
1
33MHz Typ (1) -12 Max
-15 Max
Test Condition
Notes
Operating Current — DM512K36ST6
Symbol
Operating Current
ICC1
Random Read
550mA
1125mA
900mA
/RE, /CAL, /G and Addresses Cycling: tC = tC Minimum
2, 3
ICC2
Fast Page Mode Read
325mA
725mA
575mA
/CAL, /G and Addresses Cycling: tPC = tPC Minimum
2, 4
ICC3
Static Column Read
275mA
550mA
450mA
/G and Addresses Cycling: t SC = t SC Minimum
2, 4
ICC4
Random Write
675mA
950mA
750mA
/RE, /CAL, /WE and Addresses Cycling: t C = t C Minimum
2, 3
ICC5
Fast Page Mode Write
250mA
675mA
525mA
/CAL, /WE and Addresses Cycling: tPC = tPC Minimum
2, 4
ICC6
Standby
5mA
5mA
5mA
All Control Inputs Stable ≥ VCC - 0.2V, Outputs Driven
ICCT
Average Typical
Operating Current
150mA
—
—
See "Estimating EDRAM Operating Power" Application Note
1
(1) “33MHz Typ” refers to worst case ICC expected in a system operating with a 33MHz memory bus. See power applications note for further details. This parameter is not 100% tested
or guaranteed.
(2) ICC is dependent on cycle rates and is measured with CMOS levels and the outputs open.
(3) ICC is measured with a maximum of one address change while /RE = VIL.
(4) ICC is measured with a maximum of one address change while /CAL = VIH.
2-64
Switching Characteristics
(VCC = 5V ± 5%, TA = 0 to 70°C, Commercial; -40 to 85°C, Industrial)
-12
Symbol
Description
Min
-15
Max
Min
Max
Units
tAC(1)
Column Address Access Time
tACH
Column Address Valid to /CAL Inactive (Write Cycle)
12
15
ns
tACI
Address Valid to /CAL Inactive
12
15
ns
tAQX
Column Address Change to Output Data Invalid
5
5
ns
tASC
Column Address Setup Time
5
5
ns
tASR
Row Address Setup Time
5
5
ns
tC
Row Enable Cycle Time
55
65
ns
tC1
Row Enable Cycle Time, Cache Hit (Row=LRR), Read Cycle Only
20
25
ns
tCAE
Column Address Latch Active Time
5
6
ns
tCAH
Column Address Hold Time
0
0
ns
tCH
Column Address Latch High Time (Latch Transparent)
5
5
ns
tCHR
/CAL Inactive Lead Time to /RE Inactive (Write Cycles Only)
-2
-2
ns
tCHW
Column Address Latch High to Write Enable Low (Multiple Writes)
0
0
ns
tCLV
Column Address Latch Low to Data Valid
tCQH
Column Address Latch Low to Data Invalid
tCQV
Column Address Latch High to Data Valid
tCRP
Column Address Latch Setup Time to Row Enable
5
5
ns
tCWL
/WE Low to /CAL Inactive
5
5
ns
tDH
Data Input Hold Time
0
0
ns
tDMH
Mask Hold Time From Row Enable (Write-Per-Bit)
1
1.5
ns
tDMS
Mask Setup Time to Row Enable (Write-Per-Bit)
5
5
ns
tDS
Data Input Setup Time
5
5
ns
tGQV(1)
12
15
7
5
7
5
15
Output Enable Access Time
ns
ns
ns
15
ns
5
ns
0
5
ns
0
5
ns
5
(2,3)
Output Enable to Output Drive Time
0
5
tGQZ
(4,5)
Output Turn-Off Delay From Output Disabled (/G↑)
0
5
tMH
/F and W/R Mode Select Hold Time
0
0
ns
tMSU
/F and W/R Mode Select Setup Time
5
5
ns
tNRH
/CAL, /G, and /WE Hold Time For /RE-Only Refresh
0
0
ns
tNRS
/CAL, /G, and /WE Setup Time For /RE-Only Refresh
5
5
ns
tPC
Column Address Latch Cycle Time
12
15
ns
tGQX
(1)
tRAC
Row Enable Access Time, On a Cache Miss
30
35
ns
tRAC1
Row Enable Access Time, On a Cache Hit (Limit Becomes tAC)
15
17
ns
tRAC2(1,6)
Row Enable Access Time for a Cache Write Hit
30
35
ns
tRAH
Row Address Hold Time
1
tRE
Row Enable Active Time
30
(1)
2-65
1.5
100000
35
ns
100000
ns
Switching Characteristics (continued)
(VCC = 5V ± 5%, (TA = 0 to 70°C, Commercial; -40 to 85°C, Industrial; CL = 50pF)
-12
Symbol
Description
Min
tRE1
Row Enable Active Time, Cache Hit (Row=LRR) Read Cycle
tREF
Refresh Period
tRGX
Output Enable Don't Care From Row Enable (Write, Cache Miss), O/P Hi Z
9
tRQX1(2,6)
Row Enable High to Output Turn-On After Write Miss
0
(7)
tRP
Row Precharge Time
tRP1
-15
Max
8
Min
Max
10
64
ns
64
0
ms
ns
10
12
Units
15
ns
20
25
ns
Row Precharge Time, Cache Hit (Row=LRR) Read Cycle
8
10
ns
tRRH
Read Hold Time From Row Enable (Write Only)
0
0
ns
tRSH
Last Write Address Latch to End of Write
12
15
ns
t RSW
Row Enable to Column Address Latch Low For Second Write
35
40
ns
tRWL
Last Write Enable to End of Write
12
15
ns
tSC
Column Address Cycle Time
12
15
ns
tSHR
Select Hold From Row Enable
0
0
ns
tSQV(1)
Chip Select Access Time
12
(2,3)
Output Turn-On From Select Low
0
12
tSQZ(4,5)
Output Turn-Off From Chip Select
0
8
tSSR
Select Setup Time to Row Enable
5
tT
Transition Time (Rise and Fall)
1
tWC
Write Enable Cycle Time
tWCH
tSQX
15
ns
0
15
ns
0
10
ns
5
10
1
ns
10
ns
12
15
ns
Column Address Latch Low to Write Enable Inactive Time
5
5
ns
tWHR(7)
Write Enable Hold After /RE
0
0
ns
tWI
Write Enable Inactive Time
5
5
ns
tWP
Write Enable Active Time
5
5
ns
tWQV(1)
Data Valid From Write Enable High
tWQX(2,5)
Data Output Turn-On From Write Enable High
0
12
tWQZ(3,4)
Data Turn-Off From Write Enable Low
0
12
tWRP
Write Enable Setup Time to Row Enable
5
tWRR
Write to Read Recovery (Following Write Miss)
12
2-66
ns
0
15
ns
0
15
ns
5
12
(1) VOUT Timing Reference Point at 1.5V
(2) Parameter Defines Time When Output is Enabled (Sourcing or Sinking Current) and is Not Referenced to VOH or VOL
(3) Minimum Specification is Referenced from VIH and Maximum Specification is Referenced from VIL on Input Control Signal
(4) Parameter Defines Time When Output Achieves Open-Circuit Condition and is Not Referenced to VOH or VOL
(5) Minimum Specification is Referenced from VIL and Maximum Specification is Referenced from VIH on Input Control Signal
(6) Access Parameter Applies When /CAL Has Not Been Asserted Prior to tRAC2
(7) For Write-Per-Bit Devices, tWHR is Limited By Data Input Setup Time, tDS
15
ns
15
ns
/RE Inactive Cache Read Hit (EDO Mode)
/RE
0, 2
/F
W/R
t ACI
t CAH
A0-7
A0-10
Column 1
Column 2
t ASC
t CAH
t CAE
/CAL
A0-10
0-3, P
Row
t ASC
t CH
t PC
t CQV
/WE
t CLV
DQ0-35
Open
t AC
t CLV
t CQH
Data 1
Data 2
t AC
t GQX
t GQZ
t GQV
/G
t SQX
t SQV
t SQZ
/S
Don’t Care or Indeterminate
NOTES: 1. Data accessed during /RE inactive read is from the row address specified during the last /RE active read cycle.
2. Latched data becomes invalid when /S is inactive.
2-67
/RE Active Cache Read Hit (EDO Mode)
t C1
t RE1
/RE
0,2
t RP1
t MSU
t MH
/F
t MSU
t MH
W/R
tACI
t ASR
t RAH
A0-10
Row
t CAH
Column 1
Column 2
t ASC
t ASC
t CRP
Row
t CAH
t CH
t CAE
/CAL
t PC
0-3, P
t CQV
/WE
t CLV
t RAC1
DQ
Open
0-35
t AC
t CLV
t CQH
Data 1
Data 2
t AC
t GQX
t GQZ
t GQV
/G
t SHR
t SSR
t SQZ
/S
Don’t Care or Indeterminate
NOTES: 1. Latched data becomes invalid when /S is inactive.
2-68
/RE Active Cache Read Miss (EDO Mode)
tC
t RE
/RE
0, 2
t RP
t MSU
t MH
/F
t MSU
t MH
W/R
t ACI
t ASR
A 0-10
t RAH
Row
A0-10
A 0-7
t CAH
A 0-7
Column 1
Column 2
t ASC
Row
t ASC
t CRP
t CAH
t CH
t CAE
/CAL
0-3, P
t
PC
t CQV
/WE
t CLV
t RAC
Open
DQ
0-35
t CLV
t AC
t CQH
Data 1
Data 2
t AC
t GQZ
/G
t SSR
t GQX
t SHR
t GQV
t SQZ
/S
Don’t Care or Indeterminate
NOTES: 1. Latched data becomes invalid when /S is inactive.
2-69
Burst Write (Hit or Miss) Followed By /RE Inactive Cache Reads
t RE
/RE
0,2
t MSU
t RP
t CHR
t MH
/F
t MSU
t MH
W/R
t ASR
t RAH
A0-7
A0-10
Row
t CAH
t RSW
Column 1
A0-10
t ASC
t CRP
t CAH
/CAL
t CAE
t WCH
t CWL
DQ0-35
Open
t CAE
t CH
t PC
t CHW
t CAH
t CWL
t CAE
t WCH
t RRH
t WP
/WE
t DS
Column n
t RSH
t WP
t WHR
A0-7
Column 2
t ACH
t ACH
0-3, P
t WRP
t ASC
A0-7
t WC
t DH
t WI
t RWL
t DH
t DS
Data 1
Data 2
t CLV
t WRR
t AC
Cache (Column n)
t RQX1
t GQX
/G
t GQV
t SSR
/S
Don’t Care or Indeterminate
NOTES: 1. /G becomes a don’t care after tRGX during a write miss.
2-70
Read/Write During Write Hit Cycle (Can Include Read-Modify-Write)
tC
t RE
/RE0,2
t RP
t MSU
t MH
/F
t MSU
t MH
W/R
t CHR
t ASR
t RAH
A0-10
Row
Column 1
t ASC
t ASC
t CRP
t AC
t ASC
A0-7
Column 2
t ACH
t WCH
t CLV
t PC
t WRP
/WE
t CWL
DQ0-35
Read Data
t GQX
t CQV
t RRH
t RWL
t WQV
t CLV
t DS
t AC
t CAE
t WP
t WHR
t RAC2
t RSH
t CAE
t CAH
/CAL0-3,P
Column 3
Write Data
t DH
t GQZ
t GQV
Read Data
t
GQZ
t WQX
t GQV
/G
t SSR
/S
Don’t Care or Indeterminate
NOTES: 1. If column address one equals column address two, then a read-modify-write cycle is performed.
2-71
Write-Per-Bit Cycle (/G=High)
t RE
t RP
/RE
0, 2
t RSH
t CHR
t ACH
t CAE
/CAL0-3,P
t RAH
t ASR
A0-10
t ASC
t CAH
A 0-7
Row
Column
t MSU
t MH
t CWL
t DMH
t RWL
t WCH
W/R
t DMS
DQ0-35
Mask
Data
t DS
t WRP
t DH
/WE
t RRH
t WP
t WHR
t MSU
/F
t SSR
t MH
t SHR
/S
Don’t Care or Indeterminate
NOTES: 1. Data mask bit high (1) enables bit write; data mask bit low (0) inhibits bit write.
2. Write-per-bit cycle valid only for DM512K36 ST6.
3. Write-per-bit waveform applies to parity bits only (DQ 8, 17, 26, 35).
2-72
/F Refresh Cycle
t RE
/RE0, 2
t MSU
t RP
t MH
/F
Don’t Care or Indeterminate
NOTES: 1. During /F refresh cycles, the status of W/R, /WE, A0-10, /CAL, /S, and /G is a don’t care.
2. /RE inactive cache reads may be performed in parallel with /F refresh cycles.
/RE-Only Refresh
t RE
/RE
tC
t RP
0,2
t ASR
t RAH
A 0-10
Row
t NRS
t NRH
,/WE, /G
/CAL
0-3,P
t MSU
t MH
W/R, /F
t SSR
t SHR
/S
Don’t Care or Indeterminate
NOTES: 1. All binary combinations of A0-9 must be refreshed every 64ms interval. A10 does not have to be cycled, but must remain valid
during row address setup and hold times.
2. /RE refresh is write cycle with no /CAL active cycle.
2-73
Mechanical Data
72 Pin SIMM Module
4.245 (107.82)
4.255 (108.08)
Inches (mm)
3.984 (101.19)
0.133 (3.38)
0.400
(10.16)
0.945 (24.00)
0.955 (24.26)
C2
U1
U4
C4
U3
R8
R6
U5
R10
C5
U2
R9
0.010
(.254)
R7
1
0.225
(5.72)
72
0.040 (1.02)
0.042 (1.07)
0.060 (1.52)
RAD.
0.064 (1.63)
0.050 (1.27)
0.245 (6.22)
0.255 (6.48)
0.123 (3.12)
0.127 (3.22)
R4 R3 C3 R1 R2
C1
0.075 (1.90)
0.085 (2.16)
0.062 (1.57) RAD.
0.104 (2.65)
0.250 (6.35)
1.750 (44.45)
0.250 (6.35)
0.100
(2.54)
0.047 (1.19)
0.054 (1.37)
3.750 (95.25)
2.125 (53.98)
U1-2, U4-5 — Enhanced DM2203T-XX, 512K x 8 EDRAMs, 300 Mil TSOP
U5 — Enhanced DM2213T-XX, 512K x 8 EDRAM with write-per-bit (not present on DM512K32ST6)
C1-C5 — 0.22µF Chip Capacitors
R1-R4, R6-R10 — 100KΩ Chip Resistors
Socket — AMP 822030-3 or Equivalent
Part Numbering System
DM512K36ST6 - 12I
Special Configurations
No Designator = 00 to 700C Commerical Temperature
I = 400 to 850C Industrial Temperature
Access Time from Cache in Nanoseconds
12ns
15ns
Configuration
6 = +5 Volt, Multibank EDO
Packaging System
T = 300 Mil, Plastic TSOP-II
Memory Module Configuration
S = SIMM
I/O Width
32 = 32 Bits
36 = 36 Bits
Memory Depth (Kilobits)
Dynamic Memory
The information contained herein is subject to change without notice. Enhanced Memory Systems Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in
an Enhanced product, nor does it convey or imply any license under patent or other rights.
2-74