ETC DRV591GQE

DRV591
SLOS389 – NOVEMBER 2001
±3-A HIGH-EFFICIENCY PWM POWER DRIVER
FEATURES
D ±3-A Maximum Output Current
D Low Supply Voltage Operation: 2.8 V to 5.5 V
D High Efficiency Generates Less Heat
D Over-Current and Thermal Protection
D Fault Indicators for Over-Current, Thermal and
D
D
D
D
DESCRIPTION
The DRV591 is a high-efficiency, high-current power
amplifier ideal for driving a wide variety of thermoelectric cooler elements in systems powered from 2.8 V
to 5.5 V. PWM operation and low output stage
on-resistance significantly decrease power dissipation
in the amplifier.
Under-Voltage Conditions
Two Selectable Switching Frequencies
Internal or External Clock Sync
PWM Scheme Optimized for EMI
9×9 mm PowerPAD Quad Flatpack or
5×5 mm MicroStar Junior Packages
The DRV591 is internally protected against thermal and
current overloads. Logic-level fault indicators signal
when the junction temperature has reached
approximately 130°C to allow for system-level
shutdown before the amplifier’s internal thermal
shutdown circuitry activates. The fault indicators also
signal when an over-current event has occurred. If the
over-current circuitry is tripped, the DRV591
automatically resets (see application information
section for more details).
APPLICATIONS
D Thermoelectric Cooler (TEC) Driver
D Laser Diode Biasing
The PWM switching frequency may be set to 500 kHz
or 100 kHz depending on system requirements. To
eliminate external components, the gain is fixed at
approximately 2.34 V/V.
VDD
OUT+
PGND
SHUTDOWN
OUT–
10 µH
FAULT1
FAULT0
OUT+
PVDD
PVDD
PVDD
FREQ
INT/EXT
PGND
IN–
10 µF
1 µF
To TEC or Laser
Diode Anode
OUT–
Shutdown Control
PGND
IN+
OUT–
1 kΩ
PGND
AREF
OUT–
1 kΩ
COSC
PVDD
1 µF
PGND
PVDD
220 pF
PGND
ROSC
PVDD
DC Control
Voltage
10 µH
OUT+
AGND (Connect to PowerPAD)
FAULT0
120 kΩ
AVDD
FAULT1
1 µF
OUT+
1 µF
10 µF
10 µF
To TEC or Laser
Diode Cathode
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and MicroStar Junior are trademarks of Texas Instruments.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
DRV591
SLOS389 – NOVEMBER 2001
block diagram
VDD
AGND
VDD
PVDD
R
IN–
+
_
2.34 × R
_
+
Gate
Drive
OUT–
_
+
_
+
+
_
PGND
PVDD
IN+
R
2.34 × R
+
_
OUT+
Gate
Drive
PGND
SHUTDOWN
INT/EXT
FREQ
TTL
Input
Buffer
Biases
and
References
Start-up
Protection
Logic
Ramp
Generator
COSC
Thermal
ROSC
VDDok
FAULT0
AREF
FAULT1
FREQ
INT/EXT
PVDD
PVDD
PVDD
OUT+
OUT+
OUT+
VFP PACKAGE
(TOP VIEW)
32 31 30 29 28 27 26 25
AVDD
AGND
ROSC
COSC
AREF
IN+
IN–
SHUTDOWN
1
24
2
23
3
22
4
PowerPAD
21
5
20
6
19
7
18
8
17
FAULT1
FAULT0
PVDD
PVDD
PVDD
OUT–
OUT–
OUT–
9 10 11 12 13 14 15 16
2
OC
Detect
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OUT+
PGND
PGND
PGND
PGND
PGND
PGND
OUT–
DRV591
SLOS389 – NOVEMBER 2001
Terminal Functions
TERMINAL
NAME
I/O
NO.
DESCRIPTION
AGND
2
AREF
5
O
Connect 1 µF capacitor to ground for AREF voltage filtering
AVDD
1
I
Analog power supply
COSC
4
I
Connect capacitor to ground to set oscillation frequency (220 pF for 500 kHz, 1 nF for 100 kHz) when
the internal oscillator is selected; connect clock signal when an external oscillator is used
FAULT0
10
O
Fault flag 0, low when active open drain output (see application information)
FAULT1
9
O
Fault flag 1, high when active open drain output (see application information)
FREQ
32
I
Selects 500 kHz switching frequency when a TTL logic low is applied to this terminal; selects 100kHz
switching frequency when a TTL logic high is applied
IN–
7
I
Negative differential input
IN+
6
I
Positive differential input
INT/EXT
31
I
Selects the internal oscillator when a TTL logic high is applied to this terminal; selects the use of an
external oscillator when a TTL logic low is applied to this terminal
14, 15, 16, 17
O
Negative bridge-tied load (BTL) output (4 pins)
OUT+
24, 25, 26, 27
O
Positive bridge-tied load (BTL) output (4 pins)
PGND
18, 19, 20, 21,
22, 23
PVDD
11, 12, 13, 28,
29, 30
I
High-current power supply (6 pins)
ROSC
3
I
Connect 120 kΩ resistor to AGND to set oscillation frequency (either 500 kHz or 100 kHz). Not needed if an external clock is used.
SHUTDOWN
8
I
Places the amplifier in shutdown mode when a TTL logic low is applied to this terminal; places the
amplifier in normal operation when a TTL logic high is applied
OUT–
Analog ground
High-current ground (6 pins)
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, AVDD, PVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 5.5 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output current, IO (FAULT0, FAULT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 165°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE
DISSIPATION RATING TABLE
θJA†
θJC
(°C/W)
(°C/W)
VFP
29.4
1.2
GQE‡
37.8
4.56
TA = 25°C
POWER RATING
4.1 W
3.3 W
† This data was taken using 2 oz trace and copper pad that is soldred directly to a JEDEC
standard 4-layer 3 in × 3 in PCB.
‡ This package is in the Product Preview stage of development.
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3
DRV591
SLOS389 – NOVEMBER 2001
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
PowerPAD QUAD FLATPACK
(VFP)
–40°C to 85°C
DRV591VFP§
PLASTIC BALL GRID ARRAY
MicroStar Junior
(GQE)
DRV591GQE
§ Tape and reel transport media is in the Product Preview stage of development
recommended operating conditions
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
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ÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Supply voltage, AVDD, PVDD
High-level input voltage, VIH
FREQ, INT/EXT, SHUTDOWN, COSC
Low-level input voltage, VIL
FREQ, INT/EXT, SHUTDOWN, COSC
MIN
MAX
2.8
5.5
2
Operating free-air temperature, TA
– 40
UNIT
V
V
0.8
V
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
|VOO|
Output offset voltage (measured
differentially)
|IIH|
High-level input current
|IIL|
Vn
TEST CONDITIONS
VI = VDD/2,
IO = 0 A
Low-level input current
VDD = 5.5V,
VDD = 5.5V,
VI = VDD
VI = 0 V
Integrated output noise voltage
f = <1 Hz to 10 kHz
VICM
Common mode voltage range
Common-mode
VDD = 5 V
VDD = 3.3 V
Av
Closed-loop voltage gain
MIN
rDS(on)
Voltage output (measured differentially)
Drain source on-state
on state resistance
Drain-source
Iq
Quiescent current
Iq(SD)
Quiescent current in shutdown mode
Output resistance in shutdown
4
100
mV
1
µA
1
µA
µV
1.2
2.1
2.34
2.6
60
IO = ±1 A, rds(on) = 65 mΩ, VDD = 5 V
IO = ±3 A, rds(on) = 65 mΩ, VDD = 5 V
High side
VDD = 5 V, IO = 4 A,
TA = 25°C
Low side
V
V/V
kHz
4.87
V
4.61
25
60
95
25
65
95
High side
25
80
140
Low side
25
90
140
3
Sinking 200 µA
mΩ
mΩ
A
0.1
For 500 kHz operation
225
250
275
For 100 kHz operation
45
50
55
VDD = 5 V, No load or filter
VDD = 3.3 V, No load or filter
2
6.2
12
2
4.6
8
VDD = 5 V, SHUTDOWN = 0.8 V
SHUTDOWN = 0.8 V
0
0.1
50
2
V
kHz
mA
µA
kΩ
Power-on threshold
1.7
2.8
V
Power-off threshold
1.6
2.6
V
Thermal trip point
ZI
14
3.8
Maximum continuous current output
External clock frequency range
UNIT
1.2
2.1
VDD = 3.3 V, IO = 4 A,
TA = 25°C
Status flag output pins (FAULT0, FAULT1)
Fault active (open drain output)
MAX
40
Full power bandwidth
VO
TYP
FAULT0 active
Input impedance (IN+, IN–)
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130
°C
100
kΩ
DRV591
SLOS389 – NOVEMBER 2001
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Efficiency
vs Load resistance
2, 3
vs Supply voltage
4
vs Free-air temperature
5
vs Free-air temperature
6
rDS(on)
Drain-source
Drain
source on
on-state
state resistance
Iq
PSRR
Supply current
vs Supply voltage
Power supply rejection ratio
vs Frequency
7
8, 9
Closed loop response
10, 11
vs Output voltage
IO
Maximum output current
VIO
Input offset voltage
vs Ambient temperature
Common-mode input voltage
12
13
14, 15
test set-up for graphs
The LC output filter used in Figures 2, 3, 8, and 9 is shown below.
L1
OUT+
C1
RL
L2
OUT–
C2
L1, L2 = 10 µH (part number: CDRH104R, manufacturer: Sumida)
C1, C2 = 10 µF (part number: ECJ-4YB1C106K, manufacturer: Panasonic)
Figure 1. LC Output Filter
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5
DRV591
SLOS389 – NOVEMBER 2001
TYPICAL CHARACTERISTICS
EFFICIENCY
vs
LOAD RESISTANCE
EFFICIENCY
vs
LOAD RESISTANCE
100
100
90
90
PO = 2 W
80
70
70
PO = 0.5 W
60
50
40
50
40
30
20
20
VDD = 5 V
fS = 500 kHz
0
2
3
4
5
6
7
8
RL – Load Resistance – Ω
9
VDD = 3.3 V
fS = 500 kHz
10
0
1
PO = 0.25 W
60
30
10
10
1
2
3
4
5
6
7
8
RL – Load Resistance – Ω
Figure 2
IO = 1 A
TA = 25°C
250
Total
150
Low Side
High Side
50
0
2.7
3.1
3.5
3.9
4.3
4.7
VDD – Supply Voltage – V
5.1
5.5
300
250
VDD = 5 V
IO = 1 A
VFP Package
200
Total
150
Low Side
100
High Side
50
0
–40
–15
10
35
60
TA – Free-Air Temperature – °C
Figure 5
Figure 4
6
10
DRAIN-SOURCE ON-STATE RESISTANCE
vs
FREE-AIR TEMPERATURE
rDS(on) – Drain-Source On-State Resistance – mΩ
rDS(on) – Drain-Source On-State Resistance – mΩ
300
100
9
Figure 3
DRAIN-SOURCE ON-STATE RESISTANCE
vs
SUPPLY VOLTAGE
200
PO = 1 W
PO = 0.5 W
Efficiency – %
Efficiency – %
80
PO = 1 W
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85
DRV591
SLOS389 – NOVEMBER 2001
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
300
10
VDD = 3.3 V
IO = 1 A
VFP Package
250
No Load
9
8
Iq – Supply Current – mA
rDS(on) – Drain-Source On-State Resistance – mΩ
DRAIN-SOURCE ON-STATE RESISTANCE
vs
FREE-AIR TEMPERATURE
Total
200
150
Low Side
100
High Side
7
6
5
4
3
2
50
1
0
–40
–15
10
35
60
0
2.7
85
TA – Free-Air Temperature – °C
3.1
3.5
Figure 6
5.1
5.5
–20
VDD = 5 V
fS = 500 kHz
RL = 1 Ω
Vripple = 100 mVpp
PSRR – Power Supply Rejection Ratio – dB
PSRR – Power Supply Rejection Ratio – dB
4.7
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
–20
–40
–50
–60
–70
–80
10
4.3
Figure 7
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
–30
3.9
VDD – Supply Voltage – V
100
1k
10k
f – Frequency – Hz
100k
Figure 8
–30
VDD = 3.3 V
fS = 500 kHz
RL = 1 Ω
Vripple = 100 mVpp
–40
–50
–60
–70
–80
10
100
1k
10k
f – Frequency – Hz
100k
Figure 9
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DRV591
SLOS389 – NOVEMBER 2001
TYPICAL CHARACTERISTICS
CLOSED LOOP RESPONSE
4
10
Phase
0
–10
3
–30
2
–40
Phase –°
Gain – V/V
–20
Gain
–50
1
–60
VDD = 5 V
No Load
–70
0
10
100
1k
10k
f – Frequency – Hz
–80
100k
Figure 10
CLOSED LOOP RESPONSE
10
4
0
Phase
–10
3
–30
2
–40
–50
1
–60
VDD = 3.3 V
No Load
0
10
100
–70
1k
10k
f – Frequency – Hz
Figure 11
8
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–80
100k
Phase – °
Gain – V/V
–20
Gain
DRV591
SLOS389 – NOVEMBER 2001
TYPICAL CHARACTERISTICS
MAXIMUM OUTPUT CURRENT
vs
OUTPUT VOLTAGE
MAXIMUM OUTPUT CURRENT
vs
AMBIENT TEMPERATURE
3.5
3.5
I O– Maximum Output Current – A
I O – Maximum Output Current – A
3
TJ = 100°C
2.5
TJ = 85°C
2
TJ = 125°C
1.5
1
VDD = 5 V
TA = 25°C
VFP Package
0.5
0
0
1
2
3
VO – Output Voltage – V
4
3
2.5
2
1.5
1
0.5
TJ ≤ 125°C
VFP Package
0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80
TA – Ambient Temperature – °C
5
Figure 12
Figure 13
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
10
19
8
VIO – Input Offset Voltage – mV
VIO – Input Offset Voltage – mV
9
20
VDD = 5 V
No Load
7
6
5
4
3
2
1
0
1.2
VDD = 3.3 V
No Load
18
17
16
15
14
13
12
11
1.6
2.0
2.4
2.8
3.2
3.6 3.8
VIC – Common-Mode Input Voltage – V
Figure 14
10
1.2
1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
VIC – Common-Mode Input Voltage – V
2.1
Figure 15
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9
DRV591
SLOS389 – NOVEMBER 2001
APPLICATION INFORMATION
VDD
OUT+
OUT+
OUT+
PVDD
PVDD
PGND
IN+
PGND
IN–
PGND
SHUTDOWN
OUT–
10 µH
FAULT1
FAULT0
10 µF
To TEC or Laser
Diode Anode
OUT–
PGND
AREF
OUT–
Shutdown Control
COSC
OUT–
1 kΩ
PGND
PVDD
1 kΩ
PGND
ROSC
PVDD
1 µF
10 µH
OUT+
PVDD
220 pF
DC Control
Voltage
1 µF
AGND (Connect to PowerPAD)
FAULT1
120 kΩ
PVDD
FREQ
AVDD
FAULT0
1 µF
INT/EXT
10 µF
1 µF
10 µF
To TEC or Laser
Diode Cathode
Figure 16. Typical Application Circuit
output filter considerations
TEC element manufacturers provide electrical specifications for maximum dc current and maximum output
voltage for each particular element. The maximum ripple current, however, is typically only recommended to
be less than 10% with no reference to the frequency components of the current. The maximum temperature
differential across the element, which decreases as ripple current increases, may be calculated with the
following equation:
DT +
1
ǒ1 ) N2Ǔ
DT max
(1)
Where:
∆T = actual temperature differential
∆Tmax = maximum temperature differential (specified by manufacturer)
N = ratio of ripple current to dc current
According to this relationship, a 10% ripple current reduces the maximum temperature differential by 1%. An
LC network may be used to filter the current flowing to the TEC to reduce the amount of ripple and, more
importantly, protect the rest of the system from any electromagnetic interference (EMI).
10
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DRV591
SLOS389 – NOVEMBER 2001
APPLICATION INFORMATION
filter component selection
The LC filter, which may be designed from two different perspectives, both described below, will help estimate
the overall performance of the system. The filter should be designed for the worst-case conditions during
operation, which is typically when the differential output is at 50% duty cycle. The following section serves as
a starting point for the design, and any calculations should be confirmed with a prototype circuit in the lab.
Any filter should always be placed as close as possible to the DRV591 to reduce EMI.
L
OUT+
C
TEC
OUT+
or
OUT–
R
L
C
L
TEC
R
OUT–
C
Figure 17. LC Output Filter
Figure 18. LC Half-Circuit Equivalent
(for DRV591 Only)
LC filter in the frequency domain
The transfer function for a 2nd order low-pass filter (Figures 17 and 18) is shown in equation (2):
H
(jw) +
LP
(2)
1
ǒ Ǔ
– ww
0
2
jw
) 1 w )1
Q 0
w0 + 1
ǸLC
Q + quality factor
w + DRV591 switching frequency
For the DRV591, the differential output switching frequency is typically selected to be 500 kHz. The resonant
frequency for the filter is typically chosen to be at least one order of magnitude lower than the switching
frequency. Equation (2) may then be simplified to give the following magnitude equation (3). These equations
assume the use of the filter in Figure 17.
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DRV591
SLOS389 – NOVEMBER 2001
APPLICATION INFORMATION
LC filter in the frequency domain (continued)
ŤHLPŤdB
+ * 40 log
fo +
ǒǓ
fs
fo
(3)
1
2p ǸLC
f s + 500 kHz (DRV591 switching frequency)
If L=10 µH and C=10 µF, the cutoff frequency is 15.9 kHz, which corresponds to –60 dB of attenuation at the
500 kHz switching frequency. For VDD = 5 V, the amount of ripple voltage at the TEC element is approximately
5 mV.
The average TEC element has a resistance of 1.5 Ω, so the ripple current through the TEC is approximately
3.4 mA. At the 3-A maximum output current of the DRV591, this 5.4 mA corresponds to 0.11% ripple current,
causing less than 0.0001% reduction of the maximum temperature differential of the TEC element (see
equation 1).
LC filter in the time domain
The ripple current of an inductor may be calculated using equation (4):
DI +
L
ǒVO * VTECǓDTs
(4)
L
D + duty cycle (0.5 worst case)
T s + 1ńf s + 1ń500 kHz
For VO = 5 V, VTEC = 2.5 V, and L = 10 µH, the inductor ripple current is 250 mA. To calculate how much of that
ripple current will flow through the TEC element, however, the properties of the filter capacitor must be
considered.
For relatively small capacitors (less than 22 µF) with very low equivalent series resistance (ESR, less than
10 mΩ), such as ceramic capacitors, the following equation (5) may be used to estimate the ripple voltage on
the capacitor due to the change in charge:
ǒǓ
f
2
DV + p (1–D) o
C
2
fs
D + duty cycle
2
V
(5)
TEC
f s + 500 kHz
fo +
12
1
2p ǸLC
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DRV591
SLOS389 – NOVEMBER 2001
APPLICATION INFORMATION
LC filter in the time domain (continued)
For L = 10 µH and C = 10 µF, the cutoff frequency, fo, is 15.9 kHz. For worst case duty cycle of 0.5 and
VTEC=2.5 V, the ripple voltage on the capacitors is 6.2 mV. The ripple current may be calculated by dividing the
ripple voltage by the TEC resistance of 1.5 Ω, resulting in a ripple current through the TEC element of 4.1 mA.
Note that this is similar to the value calculated using the frequency domain approach.
For larger capacitors (greater than 22 µF) with relatively high ESR (greater than 100 mΩ), such as electrolytic
capacitors, the ESR dominates over the charging-discharging of the capacitor. The following simple
equation (6) may be used to estimate the ripple voltage:
DV
C
+ DI
L
R
(6)
ESR
DI + inductor ripple current
L
R
+ filter capacitor ESR
ESR
For a 100 µF electrolytic capacitor, an ESR of 0.1 Ω is common. If the 10 µH inductor is used, delivering 250 mA
of ripple current to the capacitor (as calculated above), then the ripple voltage is 25 mV. This is over ten times
that of the 10 µF ceramic capacitor, as ceramic capacitors typically have negligible ESR.
For worst case conditions, the on-resistance of the output transistors has been ignored to give the maximum
theoretical ripple current. In reality, the voltage drop across the output transistors decreases the maximum VO
as the output current increases. It can be shown using equation (4) that this decreases the inductor ripple
current, and therefore the TEC ripple current.
switching frequency configuration: oscillator components ROSC and COSC and FREQ operation
The onboard ramp generator requires an external resistor and capacitor to set the oscillation frequency. The
frequency may be either 500 kHz or 100 kHz by selecting the proper capacitor value and by holding the FREQ
pin either low (500 kHz) or high (100 kHz). Table 1 shows the values required and FREQ pin configuration for
each switching frequency.
Table 1. Frequency Configuration Options
SWITCHING FREQUENCY
ROSC
COSC
FREQ
500 kHz
120 kΩ
220 pF
LOW (GND)
100 kHz
120 kΩ
1 nF
HIGH (VDD)
For proper operation, the resistor ROSC should have 1% tolerance while capacitor COSC should be a ceramic
type with 10% tolerance. Both components should be grounded to AGND, which should be connected to PGND
at a single point, typically where power and ground are physically connected to the printed-circuit board.
external clocking operation
To synchronize the switching to an external clock signal, pull the INT/EXT terminal low, and drive the clock signal
into the COSC terminal. This clock signal must be from 10% to 90% duty cycle and meet the voltage
requirements specified in the electrical specifications table. Since the DRV591 includes an internal frequency
doubler, the external clock signal must be approximately 250 kHz. Deviations from the 250 kHz clock frequency
are allowed and are specified in the electrical characteristic table. The resistor connected from ROSC to ground
may be omitted from the circuit in this mode of operation—the source is disconnected internally.
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13
DRV591
SLOS389 – NOVEMBER 2001
APPLICATION INFORMATION
input configuration: differential and single-ended
If a differential input is used, it should be biased around the midrail of the DRV591 and must not exceed the
common-mode input range of the input stage (see the operating characteristics at the beginning of the data
sheet).
The most common configuration employs a single-ended input. The unused input should be tied to VDD/2, which
may be simply accomplished with a resistive voltage divider. For the best performance, the resistor values
chosen should be at least 100 times lower than the input resistance of the DRV591. This prevents the bias
voltage at the unused input from shifting when the signal input is applied. A small ceramic capacitor should also
be placed from the input to ground to filter noise and keep the voltage stable. An op amp configured as a buffer
may also be used to set the voltage at the unused input.
fixed internal gain
The differential output voltage may be calculated using equation (7):
ǒ
Ǔ
(7)
–V
+V
–V
+ Av V
IN) IN–
O
OUT) OUT–
AV is the voltage gain, which is fixed internally at 2.34 V/V. The maximum and minimum ratings are provided
in the electrical specification table at the beginning of the data sheet.
V
power supply decoupling
To reduce the effects of high-frequency transients or spikes, a small ceramic capacitor, typically 0.1 µF to 1 µF,
should be placed as close to each set of PVDD pins of the DRV591 as possible. For bulk decoupling, a 10 µF
to 100 µF tantalum or aluminum electrolytic capacitor should be placed relatively close to the DRV591.
AREF capacitor
The AREF terminal is the output of an internal mid-rail voltage regulator used for the onboard oscillator and ramp
generator. The regulator may not be used to provide power to any additional circuitry. A 1 µF ceramic capacitor
must be connected from AREF to AGND for stability (see oscillator components above for AGND connection
information).
SHUTDOWN operation
The DRV591 includes a shutdown mode that disables the outputs and places the device in a low supply current
state. The SHUTDOWN pin may be controlled with a TTL logic signal. When SHUTDOWN is held high, the
device operates normally. When SHUTDOWN is held low, the device is placed in shutdown. The SHUTDOWN
pin must not be left floating. If the shutdown feature is unused, the pin may be connected to VDD.
14
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DRV591
SLOS389 – NOVEMBER 2001
APPLICATION INFORMATION
fault reporting
The DRV591 includes circuitry to sense three faults:
D Overcurrent
D Undervoltage
D Overtemperature
These three fault conditions are decoded via the FAULT1 and FAULT0 terminals. Internally, these are
open-drain outputs, so an external pull-up resistor of 5 kΩ or greater is required.
Table 2. Fault Indicators
FAULT1
FAULT0
0
0
Overcurrent
0
1
Undervoltage
1
0
Overtemperature
1
1
Normal operation
The over-current fault is reported when the output current exceeds four amps. As soon as the condition is
sensed, the over-current fault is set and the outputs go into a high-impedance state for approximately 3 µs to
5 µs (500 kHz operation). After 3 µs to 5 µs, the outputs are re-enabled. If the over-current condition has ended,
the fault is cleared and the device resumes normal operation. If the over-current condition still exists, the above
sequence will repeat.
The under-voltage fault is reported when the operating voltage is reduced below 2.8 V. This fault is not latched,
so as soon as the power-supply recovers, the fault will be cleared and normal operation will resume. During the
under-voltage condition, the outputs go to 3-state to prevent over-dissipation due to increased rDS(on).
The over-temperature fault is reported when the junction temperature exceeds 130°C. The device continues
operating normally until the junction temperature reaches 190°C, at which point the IC is disabled to prevent
permanent damage from occurring. The system’s controller must reduce the power demanded from the
DRV591 once the over-temperature flag is set, or else the device switches off when it reaches 190°C. This fault
is not latched; once the junction temperature drops below 130°C, the fault is cleared, and normal operation
resumes.
power dissipation and maximum ambient temperature
Though the DRV591 is much more efficient than traditional linear solutions, the power drop across the
on-resistance of the output transistors does generate some heat in the package, which may be calculated as
shown in equation (8):
(8)
P
DISS
ǒ OUTǓ
+ I
2
r
DS(on), total
For example, at the maximum output current of 3 A through a total on-resistance of 130 mΩ (at TJ = 25°C), the
power dissipated in the package is 1.17 W.
Calculate the maximum ambient temperature using equation (9):
ǒ
T +T * θ
A
J
JA
P
Ǔ
(9)
DISS
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15
DRV591
SLOS389 – NOVEMBER 2001
APPLICATION INFORMATION
printed circuit board (PCB) layout considerations
Since the DRV591 is a high-current switching device, a few guidelines for the layout of the printed-circuit board
(PCB) must be considered:
1. Grounding. Analog ground (AGND) and power ground (PGND) must be kept separated, ideally back to
where the power supply physically connects to the PCB, minimally back to the bulk decoupling capacitor
(10 µF ceramic minimum). Furthermore, the PowerPAD ground connection should be made to AGND, not
PGND. Ground planes are not recommended for AGND or PGND, traces should be used to route the
currents. Wide traces (100 mils) should be used for PGND while narrow traces (15 mils) should be used
for AGND.
2. Power supply decoupling. A small 0.1 µF to 1 µF ceramic capacitor should be placed as close to each
set of PVDD pins as possible, connecting from PVDD to PGND. A 0.1 µF to 1 µF ceramic capacitor should
also be placed close to the AVDD pin, connecting from AVDD to AGND. A bulk decoupling capacitor of at
least 10 µF, preferably ceramic, should be placed close to the DRV591, from PVDD to PGND. If power
supply lines are long, additional decoupling may be required.
3. Power and output traces. The power and output traces should be sized to handle the desired maximum
output current. The output traces should be kept as short as possible to reduce EMI, i.e., the output filter
should be placed as close to the DRV591 outputs as possible.
4. PowerPAD. The DRV591 in the Quad Flatpack package uses TI’s PowerPAD technology to enhance the
thermal performance. The PowerPAD is physically connected to the substrate of the DRV591 silicon, which
is connected to AGND. The PowerPAD ground connection should therefore be kept separate from PGND
as described above. The pad underneath the AGND pin may be connected underneath the device to the
PowerPAD ground connection for ease of routing. For additional information on PowerPAD PCB layout,
refer to the PowerPAD Thermally Enhanced Package application note, TI literature number SLMA002.
5. Thermal performance. For proper thermal performance, the PowerPAD must be soldered down to a
thermal land, as described in the PowerPAD Thermally Enhanced Package application note, TI literature
number SLMA002. In addition, at high current levels (greater than 2 A) or high ambient temperatures
(greater than 25°C), an internal plane may be used for heat sinking. The vias under the PowerPAD should
make a solid connection, and the plane should not be tied to ground except through the PowerPAD
connection, as described above.
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DRV591
SLOS389 – NOVEMBER 2001
MECHANICAL DATA
GQE (S-PBGA-N80)
PLASTIC BALL GRID ARRAY
5,10
SQ
4,90
4,00 TYP
0,50
J
0,50
H
G
F
E
D
C
B
A
1
0,68
0,62
2
3
4
5
6
7
8
9
1,00 MAX
Seating Plane
0,35
0,25
NOTES: A.
B.
C.
D.
∅ 0,05 M
0,21
0,11
0,08
4200461/C 10/00
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
MicroStar Junior BGA configuration
Falls within JEDEC MO-225
MicroStar Junior is a trademark of Texas Instruments.
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17
DRV591
SLOS389 – NOVEMBER 2001
MECHANICAL DATA
VFP (S-PQFP-G32)
PowerPAD PLASTIC QUAD FLATPACK
0,45
0,30
0,80
24
0,22 M
17
25
16
Thermal Pad
(See Note D)
32
9
0,13 NOM
1
8
5,60 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
1,45
1,35
Seating Plane
0°–7°
0,75
0,45
0,10
1,60 MAX
4200791/A 04/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MS-026
PowerPAD is a trademark of Texas Instruments.
18
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