Solutions on a chip for enjoying the digital life style Frame-It-1 TM Video Deinterlacer Intellectual Property Core Product Brief Zoran Corporation 3112 Scott Boulevard Santa Clara, CA 95054-3317 ® T e l 408.919.4 1 1 1 Fax 408.919.4122 www.zoran.com Description Zoran’s Frame-It-1 Video Deinterlacer is a silicon-efficient, high-performance Intellectual Property Core for video IC designs requiring progressive video output. Frame-It-1 is based on Zoran’s extensive experience delivering high quality, high volume video ICs to major consumer products manufacturers worldwide. Frame-It-1 employs a robust motion detection and an intelligent interpolation algorithm in a easily implemented, fully synchronous design. 3:2 pulldown, 2:2 pulldown, and bad edit detection enable superior deinterlacing of source material orginally from film. function into an IC. Expensive, discrete components can be eliminated from system designs. Frame-It-1 is designed into Zoran's Vaddis™ family of DVD decoders, which are in mass production and are used in brand name consumer products worldwide. VIP-II Demonstration System The VIP-II is an FPGA demonstration system for Zoran's IP Core products. The VIP-II accepts composite video, S-video and component video inputs and with its user friendly GUI, enables customers to thoroughly evaluate the performance of Zoran's IP Core products. Proven in silicon, the Frame-It-1 Video Deinterlacer greatly reduces the risk and time involved when integrating the video deinterlacing Features • • • • • • "I to P" converter • Converts interlaced video to progressive output video • Robust motion detection based algorithm • Weaves still areas of the image • Advanced interpolation for moving areas of the image • 3:2 and 2:2 pulldown detection for film modes Bad edit detection Silicon efficient design Requires only a single clock input from 20 to 30 MHz Fully synchronous design Process technology independent "softcore" Integrated Circuit Applications • LCD controllers • LCD-TV • PDP-TV • Projector TV Systems • Progressive output CRT-TV • Any IC requiring progressive video output Deliverables • Compilable Verilog source code • Bit-accurate, cycle-accurate C++ model • Synopsis synthesis scripts • Test input files • Documentation • VIP-II FPGA demonstration system available Frame-It-1 Video Deinterlacer Block Diagram Line Buffers Motion Detector Optional Line Buffers Field Buffers Adaptive BobWeave Input Control Interlaced Video Input Field Buffer Control Output Control Deinterlaced Video Output Gradient Detector Frame-It-1 Video Deinterlacer 10/02-LDI Frame-It-1-PB-1.0 Solutions on a chip for enjoying the digital life style Frame-It-1 TM Video Deinterlacer Intellectual Property Core ® Product Brief Frame-It-1 Video Deinterlacer Logical Pinout reg_ack reg_rd_rdy reg_rd_data[7:0] hactive_out vactive_out ext_clk ext_reset_1 y_top_out[7:0] c_top_out[7:0] y_bot_out[7:0] c_bot_out[7:0] reg_addr[7:0] reg_rd_wtn reg_rdy reg_wt_data[7:0] yc_lbuf_rrst yc_lbuf_wrst y_prev_lbuf_A_ren y_prev_lbuf_A_wen clk clk_x2 (optional)* reset_1 enable (optional)† hactive_in vactive_in field proscan240 repeat_first_field no_time_advance‡ Frame-It-1 y_prev_lbuf_B_ren y_prev_lbuf_B_wen Video y_prev_lbuf_wdata[7:0] y_curr_lbufA_ren Deinterlacer y_curr_lbuf_A_wen y_curr_lbuf_B_ren Pinout y_curr_lbuf_B_wen y_curr_lbuf_wdata[7:0] y_next_lbuf_A_ren y_next_lbuf_A_wen y_next_lbuf_B_ren y_next_lbuf_B_wen y_next_lbuf_wdata[7:0] y_prev_in[7:0] c_prev_in[7:0] y_curr_in[7:0] c_curr_in[7:0] y_next_in[7:0] c_next_in[7:0] c_curr_lbuf_A_ren c_curr_lbuf_A_wen c_curr_lbuf_B_ren c_curr_lbuf_B_wen c_curr_lbuf_wdata[7:0] y_prev_lbuf_A_rdata[7:0] y_prev_lbuf_B-rdata[7:0] y_curr_lbuf_A_rdata[7:0] y_curr_lbuf_B_rdata[7:0] y_next_lbuf_A_rdata[7:0] y_next_lbuf_rdata[7:0] c_miss_lbuf_ren c_miss_lbuf_wen c_miss_lbuf_wdata[7:0] c_curr_lbuf_A_rdata[7:0] c_curr_lbuf_B_rdata[7:0] c_miss_lbuf_rdata[7:0] k_prev_lbuf_rrst k_prev_lbuf_ren k_prev_lbuf_wrst k_prev_lbuf_wen k_prev_lbuf_wdata[7:0] k_prev_lbuf_rdata[7:0] m_top_lbuf_rdata[7:0] m_top_lbuf_rrst m_top_lbuf_ren m_top_lbuf_wrst m_top_lbuf_wen m_top_lbuf_wdata[7:0] k_prev_fbuf_rdata[7:0] *Required for Double-Rate Outputs †Required for Enabled Flops ‡Reserved for Future Use k_prev_fbuf_rrst k_prev_fbuf_ren k_prev_fbuf_wrst k_prev_fbuf_wen k_prev_fbuf_wdata[7:0] dbg_dmux[7:0] Zoran, Vaddis, and Frame-It are trademarks or registered trademarks of Zoran Corporation. All other trademarks are property of their respective owners. For more information, contact Zoran's Santa Clara office or the office nearest you: Canada China Hong Kong Israel Japan Korea Taiwan Zoran Toronto Lab Zoran China Office Zoran Asia Pacific Ltd. Zoran Microelectronics Ltd. Zoran Japan Office Zoran Korea Office Zoran Taiwan Office 2175 Queen St. East, Suite 2507 Unit 504-505 Advanced Technology Ctr. 2-2-8 Roppongi, Minato-ku 505, Dongbuk Building 9F-1, No 26, Lane 513 Suite 302 Electronics Science & New East Ocean Center P.O. Box 2495 Tokyo 106-0032, Japan 45-20, Yoido-Dong, Reikuang Rd., Neihu 114 Toronto, Ontario Tech Building No. 9 Science Museum Road Haifa, 31024 Israel Te l : +81-03-5574-7081 Youngdungpo-ku Taipei, Taiwan R.O.C. M4E 1E5 Canada 2070 Central Shennan Rd. Kowloon, Hong Kong Te l : +972-4-8545-777 Fax: +81-03-5574-7156 Seoul, Korea 150-891 Te l : +886-2-2659-9797 Te l : (416) 690-3356 Shenzhen, Guangdong, Tel: +852-2-620-5838 Fax: +972-4-8551-551 Tel: +82-2-761-7471 Fax: +886-2-2659-9595 Fax: (416) 690-3363 518031 P.R. China Fax: +852-2-620-5238 Fax: +82-2-761-7472 Te l : +86-755-378-0319 10/02-LDI Fax: +86-755-378-0852 Frame-It-1-PB-1.0