HD404629R Series AS Microcomputer Incorporating a DTMF Generator Circuit ADE-202-048D Rev.5.0 Sept. 1999 Description The HD404629R Series is part of the HMCS400-Series microcomputers designed to increase program productivity and also incorporate large-capacity memory. Each microcomputer has a high precision dualtone multifrequency (DTMF) generator, LCD controller/driver, A/D converter, input capture circuit, 32kHz oscillator for clock, and four low-power dissipation modes. The HD404629R Series includes four chips: the HD404628R with 8-kword ROM; the HD4046212R with 12-kword ROM; the HD404629R with 16-kword ROM; the HD4074629 with 16-kword PROM. A program can be written to the PROM by a PROM writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. Features • 1,876-digit × 4-bit RAM • 44 I/O pins, including 10 high-current pins (15 mA, max.) and 20 pins multiplexed with LCD segment pins • Four timer/counters • 8-bit input capture circuit • Three timer outputs (including two PWM out-puts) • Two event counter inputs (including one double-edge function) • Clock-synchronous 8-bit serial interface • A/D converter (4 channels × 8 bits) • LCD controller/driver (52 segments × 4 commons) • On-chip DTMF generator • Built-in oscillators Main clock: 4-MHz ceramic (an external clock is also possible) Subclock: 32.768-kHz crystal • Eleven interrupt sources Five by external sources, including three double-edge functions Six by internal sources • Subroutine stack up to 16 levels, including interrupts HD404629R Series • Four low-power dissipation modes Subactive mode Standby mode Watch mode Stop mode • One external input for transition from stop mode to active mode • Instruction cycle time (min.): 1 µs (fOSC = 4 MHz) • Operation voltage VCC = 2.7 V to 6.0 V (HD404629R) VCC = 2.7 V to 5.5 V (HD4074629) • Two operating modes MCU mode MCU/PROM mode (HD4074629 only) 2 HD404629R Series Ordering Information Type Product Name Model Name ROM (Words) Package Mask ROM HD404628R HD404628RH 8,192 100-pin plastic QFP (FP-100B) HD4046212R HD404629R TM ZTAT HD4074629 HD404628RFS 100-pin plastic QFP (FP-100A) HD404628RTF 100-pin plastic TQFP (TFP-100B) HD4046212RH 12,288 100-pin plastic QFP (FP-100B) HD4046212RFS 100-pin plastic QFP (FP-100A) HD4046212RTF 100-pin plastic TQFP (TFP-100B) HD404629RH 16,384 100-pin plastic QFP (FP-100B) HD404629RFS 100-pin plastic QFP (FP-100A) HD404629RTF 100-pin plastic TQFP (TFP-100B) HD4074629H 16,384 100-pin plastic QFP (FP-100B) HD4074629FS 100-pin plastic QFP (FP-100A) HD4074629TF 100-pin plastic TQFP (TFP-100B) TM ZTAT : Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd. Cautions about operaton! Like the ZTATTM HD4074629 and the HD404629 Series, the HD404629R Series has been verified to fully meet the standard electrical characteristics described in the data sheet or other related documents. However, due to differences in the manufacturing process, the type of built-in ROMs used, and internal wiring patterns, the HD404629R Series has different power factors, operating margins, and noise margins. Therefore, you should test both of your systems incorporating the ZTATTM and mask ROM versions. When your system is modified to use an HD404629R Series in place of a conventional chip, you should also perform a similar evaluation test to verify performance of your new system. 3 HD404629R Series List of Functions Product name HD404628R HD4046212R HD404629R HD4074629 ROM (Words) 8,192 12,288 16,384 16,384 PROM RAM (Digits) 1,876 I/O 44 (max) Large-current I/O pins 10 (Sink 15 mA max) LCD segment multiplexed pins 20 Timer / Counter 4 Input capture 8 bit × 1 Timer output 3 (PWM output possible for 2) Event input 2 (edge selection possible for 1) Serial interface 1 (8-bit syncronous) DTMF generation circuit Available A/D converter 8 bit × 4 channels LCD controller / driver circuit Max. 52 seg × 4 com Interrupts External 5 (edge selection possible for 3) Internal 6 Low-Power Dissipation Mode 4 Stop mode Available Watch mode Available Standby mode Available Subactive mode Available Main Oscillator Sub oscillator Ceramic oscillation 400 kHz, 800 kHz, 2 MHz, 4 MHz Crystal oscillation 400 kHz, 800 kHz, 2 MHz, 4 MHz Crystal oscillation 32.768 kHz Minimum instruction execution time 1 µs (fOSC = 4 MHz) Operating voltage (V) 2.7 to 6.0 Package 100-pin plastic QFP (FP-100B) 100-pin plastic QFP (FP-100A) 100-pin plastic TQFP (TFP-100B) Guaranteed operation temperature (˚C) 4 –20 to +75 — 2.7 to 5.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 AVCC AN 0 AN 1 AN 2 AN 3 AV SS TEST OSC 1 OSC 2 RESET X1 X2 GND D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 /STOPC D11/INT0 R00 /INT1 R01 /INT2 R02 /INT3 R03 /INT4 R10 /TOB R11 /TOC R12 /TOD R13 /EVNB R20 /EVND R21 /SCK R22 /SI R23 /SO R30 /SEG1 R31 /SEG2 R32 /SEG3 R33 /SEG4 R40 /SEG5 R41 /SEG6 R42 /SEG7 R43 /SEG8 R50 /SEG9 R51 /SEG10 R52 /SEG11 R53 /SEG12 R60 /SEG13 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VTref TONER TONEC VCC V3 V2 V1 COM4 COM3 COM2 COM1 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 HD404629R Series Pin Arrangement FP-100B TFP-100B 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 R73 /SEG20 R72 /SEG19 R71 /SEG18 R70 /SEG17 R63 /SEG16 R62 /SEG15 R61 /SEG14 Top view 5 HD404629R Series 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 TONEC V CC V3 V2 V1 COM4 COM3 COM2 COM1 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 Pin Arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 FP-100A R03 /INT 4 R10 /TOB R11 /TOC R12 /TOD R13 /EVNB R2 0 /EVND R21 /SCK R22 /SI R23 /SO R3 0 /SEG1 R3 1 /SEG2 R3 2 /SEG3 R3 3 /SEG4 R4 0 /SEG5 R4 1 /SEG6 R4 2 /SEG7 R4 3 /SEG8 R5 0 /SEG9 R5 1 /SEG10 R5 2 /SEG11 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 TONER VTref AV CC AN 0 AN 1 AN 2 AN 3 AV SS TEST OSC 1 OSC 2 RESET X1 X2 GND D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 /STOPC D11 /INT 0 R00 /INT 1 R01 /INT 2 R02 /INT 3 6 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 R7 3 /SEG20 R7 2 /SEG19 R7 1 /SEG18 R7 0 /SEG17 R6 3 /SEG16 R6 2 /SEG15 R6 1 /SEG14 R6 0 /SEG13 R5 3 /SEG12 HD404629R Series Pin Description Pin Number Item Symbol FP-100B TFP-100B FP-100A Power supply VCC 97 99 Applies power voltage GND 13 15 Connected to ground Test TEST 7 9 I Used for factory testing only: Connect this pin to VCC Reset RESET 10 12 I Resets the MCU Oscillato r OSC 1 8 10 I Input/output pins for the internal oscillator circuit: OSC 2 9 11 O Connect them to a ceramic oscillator ,crystal oscillator or connect OSC1 to an external oscillator curcuit X1 11 13 I Used for a 32.768-kHz crystal for clock purposes. X2 12 14 O If not to be used, fix the X1 pin to VCC and leave the X2 pin open. D0–D 9 14–23 16–25 I/O Input/output pins addressed by individual bits; pins D 0–D 9 are high-current pins that can each supply up to 15 mA D10, D11 24, 25 26, 27 I Input pins addressable by individual bits R0 0–R7 3 26–57 28–59 I/O Input/output pins addressable in 4-bit units Interrupt INT0, INT1, INT2–INT4 25–29 27–31 I Input pins for external interrupts Stop clear STOPC 24 26 I Input pin for transition from stop mode to active mode Serial SCK 35 37 I/O Serial interface clock input/output pin interface SI 36 38 I Serial interface receive data input pin SO 37 39 O Serial interface transmit data output pin TOB, TOC, TOD 30–32 32–34 O Timer output pins EVNB, EVND 33, 34 35, 36 I Event count input pins V1, V2, V3 94–96 96–98 COM1–COM4 90–93 92–95 O Common signal pins for LCD SEG1–SEG52 38–89 40–91 O Segment signal pins for LCD Port Timer LCD I/O Function Power pins for LCD controller/driver; may be left open during operation since they are connected by internal voltage division resistors. Voltage conditions are: VCC ≥ V1 ≥ V2 ≥ V3 ≥ GND 7 HD404629R Series Pin Number Item Symbol FP-100B TFP-100B FP-100A A/D converter AV CC 1 3 Power pin for A/D converter: Connect it to the same potential as V CC, as physically close to the V CC pin as possible AV SS 6 8 Ground for AVCC: Connect it to the same potential as GND, as physically close to the GND pin as possible AN0–AN 3 2–5 4–7 I Analog input pins for A/D converter TONER 99 1 O Output pin for DTMF row signals TONEC 98 100 O Output pin for DTMF column signals VTref 100 2 DTMF 8 I/O Function Reference voltage pin for DTMF signals. Voltage conditions are: VCC ≥ VTref ≥ GND HD404629R Series VCC GND RESET TEST STOPC OSC1 OSC2 X1 X2 Block Diagram D Port R0 Port R1 Port Timer D 8-bit free-running / reload timer V1 V2 V3 COM1 COM2 COM3 COM4 SEG1 SEG2 SEG3 to SEG52 R2 Port EVND TOD AVcc AVss AN0 AN1 AN2 AN3 R3 Port Timer C 8-bit free-running / reload timer VTref TONER TONEC R20 R21 R22 R23 R30 R31 R32 R33 R4 Port Timer B 8-bit free-running / reload timer TOC SCK SI SO R10 R11 R12 R13 R40 R41 R42 R43 R50 R51 R52 R53 R60 R61 R62 R63 R70 R71 R72 R73 External interrupt control circuit Timer A 8-bit free-running timer EVNB TOB R00 R01 R02 R03 R5 Port INT0 INT1 INT2 INT3 INT4 RAM R6 Port ROM D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 R7 Port HMCS400 CPU Clock-synchronous 8-bit serial interface DTMF generation circuit A/D converter 4 channels x 8 bits LCD controller / driver circuit 52 segments x 4 commons : High current pins 9 HD404629R Series Memory Map ROM Memory Map The ROM memory map is shown in figure 1 and described below. ROM address ROM address $0000 $000F $0010 Vector address (16 words) Zero-page subroutine (64 words) $003F $0040 Pattern (4,096 words) $0FFF $1000 $1FFF $2000 $2FFF $3000 $3FFF HD404628R Program (8,192 words) $0000 JMPL instruction $0001 (jump to RESET, STOPC routine) JMPL instruction $0002 (jump to INT 0 routine) $0003 JMPL instruction $0004 (jump to INT1 routine) $0005 JMPL instruction $0006 (jump to timer A routine) $0007 $0008 JMPL instruction $0009 (jump to timer B, INT 2 routine) $000A JMPL instruction $000B (jump to timer C, INT 3 routine) $000C JMPL instruction $000D (jump to timer D, INT 4 routine) $000E JMPL instruction (jump to A/D, serial routine) $000F HD4046212R Program (12,288 words) HD404629R, HD4074629 Program (16,384 words) Figure 1 ROM Memory Map Vector Address Area ($0000–$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the vector address. Zero-Page Subroutine Area ($0000–$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000–$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area ($0000–$1FFF: HD404628R; $0000–$2FFF: HD4046212R; $0000–$3FFF; HD404629R, HD4074629): Used for program coding. 10 HD404629R Series RAM Memory Map The MCU contains a 1,876-digit × 4-bit RAM area consisting of a memory register area, an LCD data area, a data area, and a stack area. In addition, an interrupt control bits area, special register area, and register flag area are mapped onto the same RAM memory space as a RAM-mapped register area outside the above areas. The RAM memory map is shown in figure 2 and described below. RAM-Mapped Register Area ($000–$03F): • Interrupt Control Bits Area ($000–$003) This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. • Special Function Register Area ($004–$01F, $024–$03F) This area is used as mode registers and data registers for external interrupts, serial interface, timer/counters, LCD, A/D converter, and as data control registers for I/O ports. The structure is shown in figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and read/write (R/W). The SEM, SEMD, REM, and REMD instructions can be used for the LCD control register (LCR: $01B), but RAM bit manipulation instructions cannot be used for other registers. • Register Flag Area ($020–$023) • This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. 11 HD404629R Series RAM address RAM address $000 RAM-mapped register area $040 Memory registers (10 digits) $050 LCD display area (52 digits) $084 $090 Not used Data (464 digits × 3) V = 0 (bank 0) V = 1 (bank 1) V = 2 (bank 2) *1 $260 Data (352 digits) $3C0 Stack (64 digits) $3FF $090 Data (464 digits) V=0 (bank = 0) Data (464 digits) V=1 (bank = 1) Data (464 digits) V=2 (bank = 2) $25F Notes: 1. The data area has three banks: bank 0 (V = 0) to bank 2 (V = 2). 2. Two registers are mapped on the same area. Read only R: Write only W: R/W: Read/write 10 $000 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01A $01B $01C $01D $01E $01F $020 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C $02D $02E $02F $030 $031 $032 $033 $034 $035 $036 $037 $038 $03E $03F Interrupt control bits area Port mode register A (PMRA) Serial mode register A (SMRA) Serial data register lower (SRL) Serial data register upper (SRU) Timer mode register A (TMA) Timer mode register B1 (TMB1) Timer B (TRBL/TWBL) (TRBU/TWBU) Miscellaneous register (MIS) Timer mode register C1 (TMC1) Timer C (TRCL/TWCL) (TRCU/TWCU) Timer mode register D1 (TMD1) Timer D (TRDL/TWDL) (TRDU/TWDU) Timer mode register B2 Timer mode register C2 Timer mode register D2 A/D mode register A/D data register lower A/D data register upper TG mode register TG control register LCD control register LCD mode register LCD output register 1 LCD output register 2 LCD output register 3 Register flag area Port mode register B Port mode register C (PMRB) (PMRC) Detection edge select register 1 (ESR1) Detection edge select register 2 (ESR2) Serial mode register B (SMRB) System clock select register (SSR) W W W W W W Not used Port D0–D3 DCR Port D4–D7 DCR Port D8 and D9 DCR Not used Port R0 DCR Port R1 DCR Port R2 DCR Port R3 DCR Port R4 DCR Port R5 DCR Port R6 DCR Port R7 DCR (DCD0) (DCD1) (DCD2) W W W (DCR0) (DCR1) (DCR2) (DCR3) (DCR4) (DCR5) (DCR6) (DCR7) W W W W W W W W Not used V register (V) R/W 11 Timer read register B lower (TRBL) R Timer write register B lower (TWBL) W $00A Timer read register B upper (TRBU) R Timer write register B upper (TWBU) W $00B 14 15 Timer read register C lower (TRCL) R Timer write register C lower (TWCL) W $00E Timer read register C upper (TRCU) R Timer write register C upper (TWCU) W $00F 17 18 Timer read register D lower (TRDL) R Timer write register D lower (TWDL) W $011 Timer read register D upper (TRDU) R Timer write register D upper (TWDU) W $012 Figure 2 RAM Memory Map 12 (TMB2) (TMC2) (TMD2) (AMR) (ADRL) (ADRU) (TGM) (TGC) (LCR) (LMR) (LOR1) (LOR2) (LOR3) W W R/W R/W W W R/W R/W W W R/W R/W W R/W R/W R/W R/W R/W W R R W W W W W W W *2 HD404629R Series Bit 3 Bit 2 Bit 1 Bit 0 $000 IM0 (IM of INT0) IF0 (IF of INT0) RSP (Reset SP bit) IE (Interrupt enable flag) $001 IMTA (IM of timer A) IFTA (IF of timer A) IM1 (IM of INT1) IF1 (IF of INT1) $002 IMTC (IM of timer C) IFTC (IF of timer C) IMTB (IM of timer B) IFTB (IF of timer B) $003 IMAD (IM of A/D) IFAD (IF of A/D) IMTD (IM of timer D) IFTD (IF of timer D) Interrupt control bits area Bit 2 Bit 1 Bit 0 $020 DTON (Direct transfer on flag) Bit 3 ADSF (A/D start flag) WDON (Watchdog on flag) LSON (Low speed on flag) $021 RAME (RAM enable flag) Not used ICEF (Input capture error flag) ICSF (Input capture status flag) $022 IM3 (IM of INT3) IF3 (IF of INT3) IM2 (IM of INT2) IF2 (IF of INT2) $023 IMS (IM of serial interface) IFS (IF of serial interface) IM4 (IM of INT4) IF4 (IF of INT4) IF: IM: IE: SP: Interrupt request flag Interrupt mask Interrupt enable flag Stack pointer Register flag area Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas IE IM LSON IF ICSF ICEF RAME RSP WDON ADSF DTON Not used SEM/SEMD REM/REMD TM/TMD Allowed Allowed Allowed Not executed Allowed Allowed Not executed Allowed Allowed Not executed in active mode Used in subactive mode Not executed Allowed Not executed Inhibited Inhibited Inhibited Allowed Allowed Allowed Not executed Inhibited Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. The REM or REMD instuction must not be executed for ADSF during A/D conversion. DTON is always reset in active mode. If the TM or TMD instruction is executed for the inhibited bits or non-existing bits, the value in ST becomes invalid. Figure 4 Usage Limitations of RAM Bit Manipulation Instructions 13 HD404629R Series RAM address Bit 3 Bit 2 Bit 1 Bit 0 $000 Interrupt control bits area $003 PMRA $004 Not used SMRA $005 R21/SCK Not used R22/SI SRL $006 Serial data register (lower digit) SRU $007 Serial data register (upper digit) TMA $008 *1 TMB1 $009 *2 Clock source setting (timer A) Clock source setting (timer B) Timer B register (lower digit) TRBL/TWBL $00A Timer B register (upper digit) TRBU/TWBU $00B MIS $00C *3 TMCI $00D *2 R23 /SO PMOS control Interrupt frame period selection Clock source setting (timer C) Timer C register (lower digit) TRCL/TWCL $00E Timer C register (upper digit) TRCU/TWCU $00F TMDI $010 *2 Clock source setting (timer D) Timer D register (lower digit) TRDL/TWDL $011 Timer D register (upper digit) TRDU/TWDU $012 TMB2 $013 TMC2 $014 TMD2 $015 AMR $016 Not used Not used *4 Not used Timer-B output mode selection Timer-C output mode setting Timer-D output mode setting *5 Not used Analog channel selection ADRL $017 A/D data register (lower digit) ADRU $018 A/D data register (upper digit) TGM $019 TGC $01A R23/SO Serial transmit clock speed selection TONEC output frequency *6 *7 *8 Not used LCR $01B LMR $01C LCD input clock source selection R33/SEG4 R32/SEG3 LOR1 $01D LOR2 $01E R43/SEG8 LOR3 $01F Not used R42/SEG7 TONER output frequency DTMF enable Not used *9 * 10 LCD duty cycle selection R31/SEG2 R30/SEG1 R41/SEG6 R40/SEG5 R7/SEG17–20 R6/SEG13–16 R5/SEG9–12 $020 Register flag area $023 PMRB $024 R03/INT4 R02/INT3 R01/INT2 R00/INT1 PMRC $025 D11/INT0 D10/STOPC R20/EVND R13/EVNB ESR1 $026 INT3 detection edge selection INT2 detection edge selection ESR2 $027 EVND detection edge selection INT4 detection edge selection * 11 * 12 SMRB $028 Not used Not used SSR $029 * 13 * 14 Clock select Not used DCD0 $02C Port D3 DCR Port D2 DCR Port D1 DCR Port D0 DCR DCD1 $02D Port D7 DCR Port D6 DCR Port D5 DCR Port D4 DCR DCD2 $02E Not used Not used Port D9 DCR Port D8 DCR Not used DCR0 $030 Port R03 DCR Port R02 DCR Port R01 DCR Port R00 DCR DCR1 $031 Port R13 DCR Port R12 DCR Port R11 DCR Port R10 DCR DCR2 $032 Port R23 DCR Port R22 DCR Port R21 DCR Port R20 DCR DCR3 $033 Port R33 DCR Port R32 DCR Port R31 DCR Port R30 DCR DCR4 $034 Port R43 DCR Port R42 DCR Port R41 DCR Port R40 DCR DCR5 $035 Port R53 DCR Port R52 DCR Port R51 DCR Port R50 DCR DCR6 $036 Port R63 DCR Port R62 DCR Port R61 DCR Port R60 DCR DCR7 $037 Port R73 DCR Port R72 DCR Port R71 DCR Port R70 DCR Not used V $03F Not used Not used Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Timer-A/time-base Auto-reload on/off Pull-up MOS control Input capture selection A/D conversion time TONEC output control TONER output control Display on/off in watch mode LCD power switch LCD display on/off SO idle H/L setting Transmit clock source selection 32-kHz oscillation stop setting 32-kHz oscillation division ratio Bank 0 to bank 2 selection Figure 5 Special Function Register Area 14 HD404629R Series Memory Register (MR) Area ($040–$04F): Consisting of 16 addresses, this area (MR0–MR15) can be accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6. Memory registers MR(0) $040 MR(1) $041 MR(2) $042 MR(3) $043 MR(4) $044 MR(5) $045 MR(6) $046 MR(7) $047 MR(8) $048 MR(9) $049 MR(10) $04A MR(11) $04B MR(12) $04C MR(13) $04D MR(14) $04E MR(15) $04F $3C0 $3FF Stack area Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 Level 1 Bit 3 Bit 2 Bit 1 Bit 0 $3FC ST PC13 PC 12 PC11 $3FD PC 10 PC9 PC 8 PC7 $3FE CA PC6 PC 5 PC4 $3FF PC 3 PC2 PC 1 PC0 PC13 –PC0 : Program counter ST: Status flag CA: Carry flag Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position 15 HD404629R Series LCD Data Area ($050–$083): Used for storing 52-digit LCD data which is automatically output to LCD segments as display data. Data 1 lights the corresponding LCD segment; data 0 extinguishes it. Refer to the LCD description for details. Data Area ($090–$3BF): 464 digits from $090 to $25F have three banks, which can be selected by setting the bank register (V: $03F). Before accessing this area, set the bank register to the required value (figure 7). The area from $260 to $3BF is accessed without setting the bank register. Bank register (V: $03F) Bit 3 2 1 0 Initial value — — 0 0 Read/Write — — R/W R/W V1 V0 Bit name Not used Not used Bank area selection V1 V0 0 0 Bank 0 is selected 1 Bank 1 is selected 0 Bank 2 is selected 1 Not Used 1 Note: After reset, the value in the bank register is 0, and therefore bank 0 is selected. If V1 = 1 and V0 = 1, no bank is selected, and the operation is not guaranteed. Figure 7 Bank Register (V) Stack Area ($3C0–$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a 16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save conditions are shown in figure 6. The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can only be restored by the RTNI instruction. Any unused space in this area is used for data storage. 16 HD404629R Series Functional Description Registers and Flags The MCU has nine registers and two flags for CPU operations. They are shown in figure 8 and described below. 3 Accumulator 0 (A) Initial value: Undefined, R/W 3 B register Initial value: Undefined, R/W W register Initial value: Undefined, R/W 0 (B) 1 0 (W) 3 X register Initial value: Undefined, R/W 0 (X) 3 Y register Initial value: Undefined, R/W SPX register Initial value: Undefined, R/W SPY register Initial value: Undefined, R/W 0 (Y) 3 0 (SPX) 3 0 (SPY) 0 Carry Initial value: Undefined, R/W Status Initial value: 1, R/W not possible (CA) 0 Program counter Initial value: $0000, R/W not possible (ST) 13 0 (PC) 9 Stack pointer Initial value: $3FF, R/W not possible 1 5 1 1 1 0 (SP) Figure 8 Registers and Flags Accumulator (A) and B Register (B): A and B are 4-bit registers, and are used to hold the results of ALU (arithmetic and logical unit) operations and to transfer data between memory, I/O ports, and other registers. W Register (W), X Register (X), and Y Register (Y): W is a 2-bit register and X and Y are 4-bit registers. These registers are used in RAM register indirect addressing. The Y register is also used in D port addressing. 17 HD404629R Series SPX Register (SPX) and SPY Register (SPY): The SPX and SPY registers are 4-bit registers used to supplement the X and Y registers. Carry Flag (CA): CA is a 1-bit flag that stores ALU overflow generated by an arithmetic operation. CA is set to 1 when an overflow is generated, and is cleared to 0 after operations in which no overflow occurred. CA is also affected by the carry set/carry clear instructions (SEC and REC), and by the rotate with carry instructions (ROTL and ROTR). During interrupt handling, CA is saved on the stack, and is restored from the stack by the RTNI instruction. Status Flag (ST): ST is a 1-bit flag that stores the results of arithmetic instructions, compare instructions, and bit test instructions, and is used as the branch condition for the BR, BRL, CAL, and CALL conditional branch instructions. The contents of the ST flag are held until the next arithmetic, compare, bit test, or conditional branch instruction is executed. After the execution of a conditional branch instruction, the value of ST is set to 1 without regard to the condition. During interrupt handling, ST is saved on the stack, and is restored from the stack by the RTNI instruction. Program Counter (PC): The PC is a 14-bit counter that indicates the ROM address of the next instruction the CPU will execute. Stack Pointer (SP): The SP is a 10-bit register that indicates the RAM address of the next stack frame in the stack area. The SP is initialized to $3FF by a reset. The SP is decremented by 4 by a subroutine call or by interrupt handling, and is incremented by 4 when the saved data has been restored by a return instruction. The upper 4 bits of the SP are fixed at 1111; the maximum number of stack levels is thus 16. In addition to the reset method described above, the SP can also be initialized to $3FF by clearing the reset stack pointer (RSP) in the interrupt control bits area with a RAM bit manipulation instruction, i.e., REM or REMD. Reset The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is cancelled, RESET must be high for at least one tRC to enable the oscillator to stabilize. During operation, RESET must be high for at least two instruction cycles. Initial values after MCU reset are listed in table 1. 18 HD404629R Series Table 1 Initial Values After MCU Reset Item Abbr. Initial Value Contents Program counter (PC) $0000 Indicates program execution point from start Status flag (ST) 1 Enables conditional branching address of ROM area Stack pointer (SP) $3FF Stack level 0 Interrupt Interrupt enable flag (IE) 0 Inhibits all interrupts flags/mask Interrupt request flag (IF) 0 Indicates there is no interrupt request Interrupt mask (IM) 1 Prevents (masks) interrupt requests Port data register (PDR) All bits 1 Enables output at level 1 Data control register (DCD0, DCD1) All bits 0 Turns output buffer off (to high impedance) (DCD2) - - 00 (DCR0, –DCR7) All bits 0 Port mode register A (PMRA) - - 00 Refer to description of port mode register A Port mode register B (PMRB) 0000 Refer to description of port mode register B Port mode register C bits 3, 1, 0 (PMRC3, PMRC1, PMRC0) 000 Refer to description of port mode register C Detection edge select register 1 (ESR1) 0000 Disables edge detection Detection edge select register 2 (ESR2) 0000 Disables edge detection Timer mode register A (TMA) 0000 Refer to description of timer mode register A I/O Timer/ counters, Timer mode register B1 (TMB1) 0000 Refer to description of timer mode register B1 serial Timer mode register B2 (TMB2) - - 00 Refer to description of timer mode register B2 interface Timer mode register C1 (TMC1) 0000 Refer to description of timer mode register C1 Timer mode register C2 (TMC2) - 000 Refer to description of timer mode register C2 Timer mode register D1 (TMD1) 0000 Refer to description of timer mode register D1 Timer mode register D2 (TMD2) 0000 Refer to description of timer mode register D2 Serial mode register A (SMRA) 0000 Refer to description of serial mode register A Serial mode register B (SMRB) - - X0 Refer to description of serial mode register B Prescaler S (PSS) $000 — Prescaler W (PSW) $00 — Timer counter A (TCA) $00 — Timer counter B (TCB) $00 — Timer counter C (TCC) $00 — Timer counter D (TCD) $00 — 19 HD404629R Series Table 1 Initial Values After MCU Reset (cont) Item Abbr. Initial Value Contents Timer/ counters, Timer write register B (TWBU, TWBL) $X0 — serial interface Timer write register C (TWCU, TWCL) $X0 — Timer write register D (TWDU, TWDL) $X0 — Octal counter (OC) 000 — A/D mode register (AMR) 00 - 0 Refer to description of A/D mode register A/D data register (ADRL, ADRU) $80 Refer to description of A/D data register LCD control register (LCR) - 000 Refer to description of LCD control register LCD mode register (LMR) 0000 Refer to description of LCD duty-cycle/clock control register LCD output register 1 (LOR1) 0000 Sets R-port/LCD segment pins to R port mode LCD output register 2 (LOR2) 0000 LCD output register 3 (LOR3) - 000 Tone generator mode register (TGM) 0000 Refer to description of tone generator mode register Tone generator control register (TGC) 000 - Refer to description of tone generator control register Low speed on flag (LSON) 0 Refer to description of operating modes Watchdog timer on flag (WDON) 0 Refer to description of timer C A/D start flag (ADSF) 0 Refer to description of A/D converter Direct transfer on flag (DTON) 0 Refer to description of operating modes Input capture status flag (ICSF) 0 Refer to description of timer D Input capture error flag (ICEF) 0 Refer to description of timer D Miscellaneous register (MIS) 0000 Refer to description of operating modes, I/O, and serial interface System clock select register (SSR) 0000 Refer to description of operating modes, oscillation circuits, and DTMF generator Bank register (V) - - 00 Refer to description of RAM memory map A/D LCD DTMF Bit registers Others Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table. 2. X indicates invalid value. – indicates that the bit does not exist. 20 HD404629R Series Item Abbr. Status After Cancellation of Stop Mode by STOPC Input Carry flag (CA) Pre-stop-mode values are not guaranteed; Pre-MCU-reset values Accumulator (A) values must be initialized by program are not guaranteed; val- B register (B) ues must be initialized by W register (W) program X/SPX register (X/SPX) Y/SPY register (Y/SPY) Serial data register (SRL, SRU) RAM Status After Cancellation of Stop Mode by RESET Input Status After all Other Types of Reset Pre-stop-mode values are retained RAM enable flag (RAME) 1 0 0 Port mode register C bit 2 (PMRC2) Pre-stop-mode values are retained 0 0 System clock select register bit 3 (SSR3) Interrupts The MCU has 11 interrupt sources: five external signals (INT0, INT1, INT 2–INT 4), four timer/ counters (timers A, B, C, and D), serial interface, and A/D converter. An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt source, and an interrupt enable flag (IE) controls the entire interrupt process. Some vector addresses are shared by two different interrupts. They are timer B and INT 2, timer C and INT 3, timer D and INT4, and A/D converter and serial interface interrupts. So the type of request that has occurred must be checked at the beginning of interrupt processing. Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $022 to $023 in RAM are reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions. The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE) and the IF to 0 and the interrupt mask (IM) to 1. A block diagram of the interrupt control circuit is shown in figure 9, interrupt priorities and vector addresses are listed in table 2, and interrupt processing conditions for the 11 interrupt sources are listed in table 3. An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to that interrupt source. The interrupt processing sequence is shown in figure 10 and an interrupt processing flowchart is shown in figure 11. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack 21 HD404629R Series during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. Program the JMPL instruction at each vector address, to branch the program to the start address of the interrupt program, and reset the IF by a software instruction within the interrupt program. Table 2 Vector Addresses and Interrupt Priorities Reset/Interrupt Priority Vector Address RESET, STOPC* — $0000 INT0 1 $0002 INT1 2 $0004 Timer A 3 $0006 Timer B, INT2 4 $0008 Timer C, INT3 5 $000A Timer D, INT4 6 $000C A/D, Serial 7 $000E Note: * The STOPC interrupt request is valid only in stop mode. 22 HD404629R Series $ 000,0 IE Interrupt request INT0 interrupt $ 000,2 IFO $ 000,3 IMO INT1 interrupt Vector address Priority controller $ 001,0 IF1 $ 001,1 IM1 Timer A interrupt $ 001,2 IFTA $ 001,3 IMTA Timer B interrupt Timer C interrupt Timer D interrupt $ 002,0 IFTB $ 022,0 IF2 INT2 interrupt $ 002,1 IMTB $ 022,1 IM2 $ 002,2 IFTC $ 022,2 IF3 INT3 interrupt $ 002,3 IMTC $ 022,3 IM3 $ 003,0 IFTD $ 023,0 IF4 INT4 interrupt $ 003,1 $ 023,1 IM4 IMTD A/D interrupt $ 003,2 IFAD $ 023,2 Serial interrupt IFS $ 003,3 IMAD $ 023,3 IMS Note: $m,n is RAM address $m, bit number n. Figure 9 Interrupt Control Circuit 23 HD404629R Series Table 3 Interrupt Processing and Activation Conditions Interrupt Source Interrupt Cuntrol Bit INT0 INT1 Timer A Timer B or INT2 Timer C or INT3 Timer D or INT4 A/D or Serial IE 1 1 1 1 1 1 1 IF0 . IM0 IF1 . IM1 IFTA . IMTA 1 0 0 0 0 0 0 * 1 0 0 0 0 0 * * 1 0 0 0 0 IFTB . + IF2 . IFTC . + IF3 . IMTB IM2 * * * 1 0 0 0 IMTC IM3 * * * * 1 0 0 IFTD . IMTD + IF4 . IM4 IFAD . IMAD + IFS . IMS * * * * * 1 0 * * * * * * 1 Note: Bits marked * can be either 0 or 1. Their values have no effect on operation. Instruction cycles 1 2 3 4 5 6 Instruction execution* Interrupt acceptance Stacking IE reset Vector address generation Execution of JMPL instruction at vector address Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a 2-cycle instruction. Figure 10 Interrupt Processing Sequence 24 Execution of instruction at start address of interrupt routine HD404629R Series Power on RESET = 1? Yes No Interrupt request? No Yes No IE = 1? Yes Reset MCU Accept interrupt Execute instruction IE ← 0 Stack ← (PC) Stack ← (CA) Stack ← (ST) PC ←(PC) + 1 PC← $0002 Yes INT0 interrupt? No PC← $0004 Yes INT1 interrupt? No PC← $0006 Yes Timer-A interrupt? No PC← $0008 Yes Timer-B/INT 2 interrupt? No PC ← $000A Yes Timer-C/INT 3 interrupt? No PC ← $000C Yes Timer-D/INT 4 interrupt? No PC ← $000E (A/D, serial interrupt) Figure 11 Interrupt Processing Flowchart 25 HD404629R Series Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt processing and set by the RTNI instruction, as listed in table 4. Table 4 Interrupt Enable Flag (IE: $000, Bit 0) IE Interrupt Enabled/Disabled 0 Disabled 1 Enabled External Interrupts (INT0, INT1, INT2–INT4): Five external interrupt signals. External Interrupt Request Flags (IF0–IF4: $000, $001, $022, $023): IF0 and IF1 are set at the falling edge of signals input to INT0 and INT1, and IF2–IF4 are set at the rising or falling edge of signals input to INT 2–INT 4, as listed in table 5. The INT2–INT4 interrupt edges are selected by the detection edge select registers (ESR1, ESR2: $026, $027) as shown in figures 12 and 13. Table 5 External Interrupt Request Flags (IF0–IF4: $000, $001, $022, $023) IF0–IF4 Interrupt Request 0 No 1 Yes Detection edge selection register 1 (ESR1: $026) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W ESR13 ESR12 ESR11 ESR10 Bit name INT3 detection edge ESR13 ESR12 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Double-edge detection * 1 INT2 detection edge ESR11 ESR10 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Double-edge detection 1 Note: * Both falling and rising edges are detected. Figure 12 Detection Edge Selection Register 1 (ESR1) 26 * HD404629R Series Detection edge selection register 2 (ESR2: $027) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write W W W W ESR23 ESR22 ESR21 ESR20 Bit name EVND detection edge ESR23 ESR22 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Double-edge detection * 1 INT4 detection edge ESR21 ESR20 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Double-edge detection* 1 Note: * Both falling and rising edges are detected. Figure 13 Detection Edge Selection Register 2 (ESR2) External Interrupt Masks (IM0–IM4: $000, $001, $022, $023): Prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as listed in table 6. Table 6 External Interrupt Masks (IM0–IM4: $000, $001, $022, $023) IM0–IM4 Interrupt Request 0 Enabled 1 Disabled (masked) Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in table 7. Table 7 Timer A Interrupt Request Flag (IFTA: $001, Bit 2) IFTA Interrupt Request 0 No 1 Yes 27 HD404629R Series Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer A interrupt request flag, as listed in table 8. Table 8 Timer A Interrupt Mask (IMTA: $001, Bit 3) IMTA Interrupt Request 0 Enabled 1 Disabled (masked) Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B, as listed in table 9. Table 9 Timer B Interrupt Request Flag (IFTB: $002, Bit 0) IFTB Interrupt Request 0 No 1 Yes Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the timer B interrupt request flag, as listed in table 10. Table 10 Timer B Interrupt Mask (IMTB: $002, Bit 1) IMTB Interrupt Request 0 Enabled 1 Disabled (masked) Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in table 11. Table 11 Timer C Interrupt Request Flag (IFTC: $002, Bit 2) IFTC Interrupt Request 0 No 1 Yes 28 HD404629R Series Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer C interrupt request flag, as listed in table 12. Table 12 Timer C Interrupt Mask (IMTC: $002, Bit 3) IMTC Interrupt Request 0 Enabled 1 Disabled (masked) Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the rising or falling of signals input to EVND when the input capture function is used, as listed in table 13. Table 13 Timer D Interrupt Request Flag (IFTD: $003, Bit 0) IFTD Interrupt Request 0 No 1 Yes Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the timer D interrupt request flag, as listed in table 14. Table 14 Timer D Interrupt Mask (IMTD: $003, Bit 1) IMTD Interrupt Request 0 Enabled 1 Disabled (masked) Serial Interrupt Request Flag (IFS: $023, Bit 2): Set when data transfer is completed or when data transfer is suspended, as listed in table 15. Table 15 Serial Interrupt Request Flag (IFS: $023, Bit 2) IFS Interrupt Request 0 No 1 Yes 29 HD404629R Series Serial Interrupt Mask (IMS: $023, Bit 3): Prevents (masks) an interrupt request caused by the serial interrupt request flag, as listed in table 16. Table 16 Serial Interrupt Mask (IMS: $023, Bit 3) IMS Interrupt Request 0 Enabled 1 Disabled (masked) A/D Interrupt Request Flag (IFAD: $003, Bit 2): Set at the completion of A/D conversion, as listed in table 17. Table 17 A/D Interrupt Request Flag (IFAD: $003, Bit 2) IFAD Interrupt Request 0 No 1 Yes A/D Interrupt Mask (IMAD: $003, Bit 3): Prevents (masks) an interrupt request caused by the A/D interrupt request flag, as listed in table 18. Table 18 A/D Interrupt Mask (IMAD: $003, Bit 3) IMAD Interrupt Request 0 Enabled 1 Disabled (masked) 30 HD404629R Series Operating Modes The MCU has five operating modes as shown in table 19. The operations in each mode are listed in tables 20 and 21. Transitions between operating modes are shown in figure 14. Active Mode: All MCU functions operate according to the clock generated by the system oscillator OSC1 and OSC2. Table 19 Operating Modes and Clock Status Mode Name Active Standby Stop Watch Subactive*2 RESET cancellation, interrupt request, STOPC cancellation in stop mode, STOP/SBY instruction in subactive mode (when direct transfer is selected) SBY instruction STOP instruction when TMA3 = 0 STOP instruction when TMA3 = 1 INT0 or timer A interrupt request from watch mode System oscillator OP OP Stopped Stopped Stopped Subsystem oscillator OP OP OP*1 OP OP RESET input, STOP/SBY instruction RESET input, RESET input, interrupt STOPC input request in stop mode RESET input, INT0 or timer A interrupt request RESET input, STOP/SBY instruction Activation method Status Cancellation method Notes: OP implies in operation. 1. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select register (SSR: $029). 2. Subactive mode is an optional function; specify it on the function option list. 31 HD404629R Series Table 20 Operations in Low-Power Dissipation Modes Function Stop Mode Watch Mode Standby Mode Subactive Mode*2 CPU Reset Retained Retained OP RAM Retained Retained Retained OP Timer A Reset OP OP OP Timer B Reset Stopped OP OP Timer C Reset Stopped OP OP Timer D Reset Stopped OP OP Serial interface Reset Stopped *3 OP OP A/D Reset Stopped OP Stopped LCD Reset OP *4 OP OP DTMF Reset Reset Stopped Reset I/O Reset *1 Retained Retained OP Notes: OP implies in operation. 1. Output pins are at high impedance. 2. Subactive mode is an optional function specified on the function option list. 3. Transmission/Reception is activated if a clock is input in external clock mode. However, interrupts stop. 4. When a 32-kHz clock source is used. Table 21 I/O Status in Low-Power Dissipation Modes Output Input Standby Mode, Watch Mode Stop Mode Active Mode, Subactive Mode D0–D 9 Retained High impedance Input enabled D10–D 11 — — Input enabled R0–R7 Retained or output of peripheral functions High impedance Input enabled 32 HD404629R Series Reset by RESET input or by watchdog timer Stop mode (TMA3 = 0, SSR3 = 0) RAME = 0 RAME = 1 RESET1 RESET2 STOPC STOPC STOP Oscillate Oscillate Stop fcyc fcyc Stop Oscillate Stop Stop Stop Active mode Standby mode fOSC: fX: ø CPU : ø CLK : ø PER : fOSC: fX: ø CPU : ø CLK : ø PER : SBY Interrupt fOSC: fX: ø CPU : ø CLK : ø PER : Oscillate Oscillate fcyc fcyc fcyc (TMA3 = 0, SSR3 = 1) STOP fOSC: fX: ø CPU : ø CLK : ø PER : Stop Stop Stop Stop Stop (TMA3 = 0) Watch mode (TMA3 = 1) fOSC: fX: ø CPU : ø CLK : ø PER : Oscillate Oscillate Stop fW fcyc SBY Interrupt fOSC: fX: ø CPU : ø CLK : ø PER : Oscillate Oscillate fcyc fW fcyc (TMA3 = 1, LSON = 0) STOP INT0, timer A*1 fOSC: fX: ø CPU : ø CLK : ø PER : Stop Oscillate Stop fW Stop *3 fOSC: fX: Main oscillation frequency Suboscillation frequency for time-base fOSC/4 fcyc: fSUB: fX/8 or fX/4 (software selectable) fW: fX/8 ø CPU : CPU operating clock ø CLK : Timer A operating clock ø PER : Clock for peripheral functions (except timer A) LSON: Low speed on flag DTON: Direct transfer on flag *2 Subactive mode fOSC: fX: ø CPU : ø CLK : ø PER : STOP Stop Oscillate fSUB fW fSUB Notes: 1. 2. 3. 4. *4 INT0, timer A*1 (TMA3 = 1, LSON = 1) fOSC: fX: ø CPU : ø CLK : ø PER : Stop Oscillate Stop fW Stop Interrupt source STOP/SBY (DTON = 1, LSON = 0) STOP/SBY (DTON = 0, LSON = 0) STOP/SBY (DTON = Don’t care, LSON = 1) Figure 14 MCU Status Transitions 33 HD404629R Series Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and serial interface continue to operate. The power dissipation in this mode is lower than in active mode because the CPU stops. The MCU enters standby mode when the SBY instruction is executed in active mode. Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input, the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. A flowchart of operation in standby mode is shown in figure 15. Stop mode Standby mode RESET = 1? RESET = 1? No Yes Watch mode No Yes IF0 • IM0 = 1? No No STOPC = 0? Yes IF1 • IM1 = 1? No Yes Yes*1 RAME = 1 RAME = 0 No IFTA • IMTA = 1? Yes IFTB • IMTB + IF2 • IM2 = 1? Yes*1 No IFTC • IMTC + IF3 • IM3 = 1? Yes*1 No IFTD • IMTD + IF4 • IM4 = 1? Yes*1 No IFAD • No IMAD + IFS • IMS = 1? Yes*1 System clock oscillator started Next instruction execution System reset No IF = 1, IM = 0, IE = 1? Yes Note: 1. Only when clearing from standby mode Next instruction execution Interrupts enabled Figure 15 MCU Operation Flowchart 34 System clock oscillator started , HD404629R Series Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power dissipation in this mode is the least of all modes. The OSC 1 and OSC2 oscillator stops. For the X1 and X2 oscillator to operate or stop can be selected by setting bit 3 of the system clock select register (SSR: $029; operating: SSR3 = 0, stop: SSR3 = 1) (figure 27). The MCU enters stop mode if the STOP instruction is executed in active mode when bit 3 of timer mode register A (TMA: $008) is set to 0 (TMA3 = 0) (figure 44). Stop mode is terminated by a RESET input or a STOPC input as shown in figure 16. RESET or STOPC must be applied for at least one t RC to stabilize oscillation (refer to the AC Characteristics section). When the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained, but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register, carry flag, and serial data register cannot be guaranteed. Stop mode Oscillator Internal clock RESET STOPC tres STOP instruction execution (at least equal to oscillator stabilization time tRC) Figure 16 Timing of Stop Mode Cancellation Watch Mode: In watch mode, the clock function (timer A) using the X1 and X2 oscillator and the LCD function operate, but other function operations stop. Therefore, the power dissipation in this mode is the second least to stop mode, and this mode is convenient when only clock display is used. In this mode, the OSC1 and OSC2 oscillator stops, but the X1 and X2 oscillator operates. The MCU enters watch mode if the STOP instruction is executed in active mode when TMA3 = 1, or if the STOP or SBY instruction is executed in subactive mode. Watch mode is terminated by a RESET input or a timer-A/INT0 interrupt request. For details of RESET input, refer to the Stop Mode section. When terminated by a timer-A/INT0 interrupt request, the MCU enters active mode if LSON = 0, or subactive mode if LSON = 1. After an interrupt request is generated, the time required to enter active mode is tRC for a timer A interrupt, and TX (where T + tRC < TX < 2T + tRC) for an INT0 interrupt, as shown in figures 17 and 18. Operation during mode transition is the same as that at standby mode cancellation (figure 15). 35 HD404629R Series Subactive Mode: The OSC1 and OSC2 oscillator stops and the MCU operates with a clock generated by the X1 and X2 oscillator. In this mode, functions except the A/D conversion operate. However, because the operating clock is slow, the power dissipation becomes low, next to watch mode. The CPU instruction execution speed can be selected as 244 µs or 122 µs by setting bit 2 (SSR2) of the system clock select register (SSR: $029). Note that the SSR2 value must be changed in active mode. If the value is changed in subactive mode, the MCU may malfunction. When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active mode, depending on the statuses of the low speed on flag (LSON: $020, bit 0) and the direct transfer on flag (DTON: $020, bit 3). Subactive mode is an optional function that the user must specify on the function option list. Interrupt Frame: In watch and subactive modes, φCLK is applied to timer A and the INT0Icircuit. Prescaler W and timer A operate as the time-base and generate the timing clock for the interrupt frame. Three interrupt frame lengths (T) can be selected by setting the miscellaneous register (MIS: $00C) (figure 18). In watch and subactive modes, the timer-A/INT0 interrupt is generated synchronously with the interrupt frame. The interrupt request is generated synchronously with the interrupt strobe timing except during transition to active mode. The falling edge of the INT0 signal is input asynchronously with the interrupt frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the falling edge. An overflow and interrupt request in timer A is generated synchronously with the interrupt strobe timing. 36 HD404629R Series Oscillation stabilization period Active mode Watch mode Active mode Interrupt strobe INT0 Interrupt request generation (During the transition from watch mode to active mode only) T T tRC TX T: Interrupt frame period t RC : Oscillation stabilization period Note: If the time from the fall of the INT0 signal until the interrrupt is accepted and active mode is entered is designated Tx, then Tx will be in the following range: T + tRC ≤ Tx ≤ 2T + tRC Figure 17 Interrupt Frame 37 HD404629R Series Direct Transition from Subactive Mode to Active Mode: Available by controlling the direct transfer on flag (DTON: $020, bit 3) and the low speed on flag (LSON: $020, bit 0). The procedures are described below: • Set LSON to 0 and DTON to 1 in subactive mode. • Execute the STOP or SBY instruction. • The MCU automatically enters active mode from subactive mode after waiting for the MCU internal processing time and oscillation stabilization time (figure 19). Notes: 1. The DTON flag can be set only in subactive mode. It is always reset in active mode. 2. The transition time (TD) from subactive mode to active mode: tRC < TD < T + tRC Miscellaneous register (MIS: $00C) Bit 3 2 1 Initial value 0 0 0 0 Read/Write W W W W MIS3 MIS2 MIS1 MIS0 Bit name MIS3 MIS2 Buffer control. Refer to figure 41. MIS1 MIS0 0 0 0 T*1 tRC * 1 Oscillation circuit conditions 0.24414 ms 0.12207 ms External clock input 0.24414 ms* 2 0 1 1 0 1 1 Ceramic oscillator 15.625 ms 7.8125 ms 62.5 ms 31.25 ms Crystal oscillator Not used Not used — Notes: 1. Values of T and tRC when a 32.768-kHz crystal oscillator is used to pins x1 and x2. 2. The value is applied only when direct transfer operation is used. Figure 18 Miscellaneous Register (MIS) STOP/SBY instruction execution MCU internal Subactive mode processing time Oscillation stabilization time (Set LSON = 0, DTON = 1) Interrupt strobe Direct transfer completion timing t RC T TD T: Interrupt frame length t RC : Oscillation stabilization period TD : Direct transition time Figure 19 Direct Transition Timing 38 Active mode HD404629R Series Stop Mode Cancellation by STOPC : The MCU enters active mode from stop mode by inputting STOPC as well as by RESET. In either case, the MCU starts instruction execution from the starting address (address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs between cancellation by STOPC and by RESET. When stop mode is cancelled by RESET, RAME = 0; when cancelled by STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop mode; STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop mode has been cancelled by STOPC (for example, when the RAM contents before entering stop mode is used after transition to active mode), execute the TEST instruction to the RAM enable flag (RAME) at the beginning of the program. MCU Operation Sequence: The MCU operates in the sequence shown in figures 20 to 22. It is reset by an asynchronous RESET input, regardless of its status. The low-power mode operation sequence is shown in figure 22. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt flags are cleared or all interrupts are masked. Power on RESET = 1 ? No Yes RAME = 0 MCU operation cycle Reset MCU Figure 20 MCU Operating Sequence (Power On) 39 HD404629R Series MCU operation cycle IF = 1? No Instruction execution Yes SBY/STOP instruction? Yes No IM = 0 and IE = 1? Yes IE ← 0 Stack ← (PC), (CA), (ST) No Low-power mode operation cycle IF: IM: IE: PC: CA: ST: PC ← Next location PC ← Vector address Interrupt request flag Interrupt mask Interrupt enable flag Program counter Carry flag Status flag Figure 21 MCU Operating Sequence (MCU Operation Cycle) 40 HD404629R Series STOP/SBY instruction IF = 1 and IM = 0? No Yes Standby/watch mode No Interrupt service routine IE = 0 * No Yes Stop mode IF = 1 and IM = 0? No STOPC = 0? Yes Yes Hardware NOP execution Hardware NOP execution RAME = 1 PC ← (PC)+1 PC ← (PC)+1 Reset MCU Instruction execution MCU operation cycle Note: * Refer to figure 15, Flowchart for Exiting Low Power Modes, for IF and IM operation. Figure 22 MCU Operating Sequence (Low-Power Mode Operation) 41 HD404629R Series Notes: 1. When watch or subactive mode on HD404629R Series/HD4074629 is used and the LCD function is off in that mode, the watch mode or subactive mode current is larger, and consequently the following settings should be made. Perform the following writes in the order shown before the transition to watch mode (before execution of the STOP instruction): Write $0 to LCR Write $3 to LMR Also, when returning to active mode from watch mode or subactive mode, perform the following writes in the order shown: Write a value appropriate to the conditions of use to LMR Write a value appropriate to the conditions of use to LCR A sample programming flowchart for the above procedures is shown in figure 23. .. . LMR LCR .. . Set appropriate values for active mode Initialization routine .. . LCR = $0 LMR. = $3 .. Include these operations Main routine STOP instruction Watch mode Or transition to subactive mode After the MCU enters active mode again .. . LMR LCR .. . Set appropriate values for active mode INT 0 or timer A interrupt processing routine Figure 23 Programming Flowchart (LCD Display Off in Watch or Subactive Mode) 42 HD404629R Series Notes: 2. When the MCU is in watch mode or subactive mode, if the high level period before the falling edge of INT0 is shorter than the interrupt frame, INT0 is not detected. Also, if the low level period after the falling edge of INT0 is shorter than the interrupt frame, INT0 is not detected. Edge detection is shown in figure 24. The level of the INT0 signal is sampled by a sampling clock. When this sampled value changes to low from high, a falling edge is detected. In figure 25, the level of the INT0 signal is sampled by an interrupt frame. In (a) the sampled value is low at point A, and also low at point B. Therefore, a falling edge is not detected. In (b), the sampled value is high at point A, and also high at point B. A falling edge is not detected in this case either. When the MCU is in watch mode or subactive mode, keep the high level and low level period of INT 0 longer than interrupt frame. INT0 Sampling High Low Low Figure 24 Edge Detection INT0 INT0 Interrupt frame Interrupt frame A: Low B: Low (a) High level period A: High B: High (b) Low level period Figure 25 Sampling Example 43 HD404629R Series Internal Oscillator Circuit A block diagram of the clock generation circuit is shown in figure 26. As shown in table 22, a ceramic oscillator can be connected to OSC1 and OSC2, and a 32.768-kHz oscillator can be connected to X1 and X2. The system oscillator can also be operated by an external clock. Bit 0 and 1 (SSR1) of the system clock select register (SSR: $029) must be set according to the frequency of the oscillator connected to OSC1 and OSC2 (figure 27). Note: If the system clock select register (SSR: $029) setting does not match the oscillator frequency, DTMF generator and subsystems using the 32.768-kHz oscillation will malfunction. LSON OSC2 1/4 System fOSC division clock circuit oscillator fcyc tcyc Timing generation circuit OSC1 fX X1 X2 Subsystem clock oscillator CPU with ROM, RAM, registers, flags, and I/O øCPU System clock selection circuit øPER Internal Peripheral module interrupts (other than timer A) fSUB 1/8 or 1/4 Timing division tsubcyc generator circuit* circuit TMA3 bit 1/8 division circuit fW tWcyc Timing generation circuit Clock Time-base clock øCLK selection circuit Note: * 1/8 or 1/4 division ratio can be selected by setting bit 2 of the system clock select register (SSR: $029). Figure 26 Clock Generation Circuit 44 Timer A interrupt HD404629R Series System clock select register (SSR: $029) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W SSR3 SSR2 SSR1 SSR0 Bit name SSR3 32-kHz oscillation stop SSR1 SSR0 System clock selection 0 Oscillation operates in stop mode 0 0 400 kHz 1 Oscillation stops in stop mode 0 1 800 kHz 1 0 2 MHz 1 1 4 MHz SSR2 32-kHz oscillation division ratio selection 0 fSUB = fX/8 1 fSUB = fX/4 Note: SSR3 is cleared only by a RESET input. SSR3 will not be cleared by a STOPC input during stop mode, and will retain its value. SSR3 will also not be cleared upon entering stop mode. Figure 27 System Clock Select Register (SSR) D0 GND X2 X1 RESET OSC2 OSC1 TEST GND AVSS Figure 28 Typical Layouts of Crystal and Ceramic Oscillator 45 HD404629R Series Table 22 Oscillator Circuit Examples Circuit Configuration Circuit Constants — External clock operation External oscillator OSC 1 Open OSC 2 Ceramic oscillator Ceramic oscillator: CSB400P22 (Murata) CSB400P (Murata) Rf = 1 MΩ ± 20% C1 = C2 = 220 pF ± 5% C1 (OSC1, OSC2) OSC1 Ceramic oscillator Rf Ceramic oscillator: CSB800J122 (Murata), CSB800J (Murata) Rf = 1 MΩ ± 20% C1 = C2 = 220 pF ± 5% OSC2 C2 GND Ceramic oscillator: CSA2.00MG (Murata) Rf = 1 MΩ ± 20% C1 = C2 = 30 pF ± 20% Ceramic oscillator: CSA4.00MG (Murata) Rf = 1 MΩ ± 20% C1 = C2 = 30 pF ± 20% Rf = 1 MΩ ± 20% C1 = C2 = 10 to 22pF ± 20% C1 Crystal oscillator (OSC1, OSC2) OSC1 Rf Crystal oscillator Crystal : Equivalent circuit at left C0 =7pF max Rs = 100Ω max f = 400kHz, 800kHz, 2MHz, 4MHz OSC2 C2 GND L OSC1 CS RS OSC2 C0 C1 Crystal oscillator Crystal oscillator: 32.768 kHz: MX38T (Nippon Denpa) C1 = C2 = 20 pF ± 20% RS: 14 kΩ C0: 1.5 pF X1 (X1, X2) Crystal oscillator X2 C2 GND L CS RS X1 X2 C0 46 HD404629R Series Notes: 1. Circuit constants differ by the different types of crystal oscillators, ceramic oscillators, and with the stray capacitance of the board, so consult the manufacturer of the oscillator to determine the circuit parameters. 2. The wiring between the OSC1, OSC 2 (X1 and X2 pins), and the other elements should be as short as possible, and must not cross other wiring. Refer to figure 28. 3. If not using a 32.768-kHz crystal oscillator, fix the X1 pin to VCC and leave the X2 pin open. Input/Output The MCU has 42 input/output pins (D 0–D 9, R00–R7 3 ) and 2 input pins (D 10 , D11 ). The features are described below. • Ten pins (D0–D9) are high-current input/output pins. • The D10 and D11, and R0 0–R7 3 input/output pins are multiplexed with peripheral function pins such as for the timers or serial interface. For these pins, the peripheral function setting is done prior to the D or R port setting. Therefore, when a peripheral function is selected for a pin, the pin function and input/output selection are automatically switched according to the setting. • Input or output selection for input/output pins and port or peripheral function selection for multiplexed pins are set by software. • Peripheral function output pins are CMOS output pins. Only the R23/SO pin can be set to NMOS opendrain output by software. • In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output pins are in high-impedance state. • Each input/output pin has a built-in pull-up MOS, which can be individually turned on or off by software. I/O buffer configuration is shown in figure 29, programmable I/O circuits are listed in table 23, and I/O pin circuit types are shown in table 24. Table 23 Programmable I/O Circuits MIS3 (bit 3 of MIS) 0 DCD, DCR 0 PDR CMOS buffer 1 1 0 1 0 1 0 1 0 1 0 1 PMOS — — — On — — — On NMOS — — On — — — On — — — — — — On — On Pull-up MOS Note: — indicates off status. 47 HD404629R Series HLT Pull-up control signal VCC MIS3 VCC Pull-up MOS Buffer control signal DCD, DCR Output data PDR Input data Input control signal Figure 29 I/O Buffer Configuration Table 24 Circuit Configurations of I/O Pins I/O Pin Type Input/output pins Circuit Pins HLT VCC VCC Pull-up control signal Buffer control signal MIS3 DCD, DCR Output data PDR Input data D0 – D9 R0 0–R0 3 R1 0–R1 3 R2 0–R2 2 R3 0–R3 3 R4 0–R4 3 R5 0–R5 3 R6 0–R6 3 R7 0–R7 3 Input control signal VCC HLT VCC Pull-up control signal Buffer control signal Output data R2 3 MIS3 DCR MIS2 PDR Input data Input control signal Input pins Input data Input control signal 48 D10, D11 HD404629R Series Table 24 Circuit Configurations of I/O Pins (cont) I/O Pin Type Peripheral function pins Circuit Input/output pins Pins HLT VCC VCC Pull-up control signal MIS3 Output data Input data Output pins SCK SCK HLT VCC VCC Pull-up control signal Output data VCC Output data Input pins MIS2 SO HLT Pull-up control signal VCC Input data TOB, TOC, TOD MIS3 TOB, TOC, TOD HLT MIS3 PDR Input data SO MIS3 PMOS control signal VCC SCK SI, INT1, INT2, INT3, INT4, EVNB, EVND SI, INT1, etc INT0, STOPC INT0, STOPC Notes: 1. The MCU is reset in stop mode, and peripheral function selection is cancelled. The HLT signal becomes low, and input/output pins enter high-impedance state. 2. The HLT signal is 1 in watch and subactive modes. 49 HD404629R Series D Port (D0–D11): Consist of 10 input/output pins and 2 input pins addressed by one bit. D0–D9 are highcurrent I/O pins, and D10 and D11 are input-only pins. Pins D 0–D 9 are set by the SED and SEDD instructions, and reset by the RED and REDD instructions. Output data is stored in the port data register (PDR) for each pin. All pins D0–D11 are tested by the TD and TDD instructions. The on/off statuses of the output buffers are controlled by D-port data control registers (DCD0–DCD2: $02C–$02E) that are mapped to memory addresses (figure 30). Pins D10 and D 11 are multiplexed with peripheral function pins S TOP C and INT0, respectively. The peripheral function modes of these pins are selected by bits 2 and 3 (PMRC2, PMRC3) of port mode register C (PMRC: $025) (figure 31). R Ports (R0 0–R73): 32 input/output pins addressed in 4-bit units. Data is input to these ports by the LAR and LBR instructions, and output from them by the LRA and LRB instructions. Output data is stored in the port data register (PDR) for each pin. The on/off statuses of the output buffers of the R ports are controlled by R-port data control registers (DCR0–DCR7: $030–$037) that are mapped to memory addresses (figure 30). Pins R0 0–R0 3 are multiplexed with peripheral pins INT1–INT 4, respectively. The peripheral function modes of these pins are selected by bits 0–3 (PMRB0–PMRB3) of port mode register B (PMRB: $024) (figure 32). Pins R10–R12 are multiplexed with peripheral pins TOB, TOC, and TOD, respectively. The peripheral function modes of these pins are selected by bits 0 and 1 (TMB20, TMB21) of timer mode register B2 (TMB2: $013), bits 0–2 (TMC20–TMC22) of timer mode register C2 (TMC2: $014), and bits 0–3 (TMD20–TMD23) of timer mode register D2 (TMD2: $015) (figures 33, 34, and 35). Pins R13 and R20 are multiplexed with peripheral pins EVNB and EVND, respectively. The peripheral function modes of these pins are selected by bits 0 and 1 (PMRC0, PMRC1) of port mode register C (PMRC: $025) (figure 31). Pins R21–R23 are multiplexed with peripheral pins SCK, SI, and SO, respectively. The peripheral function modes of these pins are selected by bit 3 (SMRA3) of serial mode register A (SMRA: $005), and bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004), as shown in figures 36 and 37. Ports R3 and R4 are multiplexed with segment pins SEG1–SEG8, respectively. The function modes of these pins can be selected by individual pins, by setting LCD output registers 1 and 2 (LOR1, LOR2: $01D, $01F) (figures 38 and 39). Ports R5–R7 are multiplexed with segment pins SEG9–SEG20, respectively. The function modes of these pins can be selected in 4-pin units by setting LCD output register 3 (LOR3: $01F) (figure 40). 50 HD404629R Series Data control register DCD0, DCD1 Bit (DCD0 to 2: $02C to $02E) (DCR0 to 7: $030 to $037) 3 2 0 1 Initial value 0 0 0 0 Read/Write W W W W Bit name DCD03, DCD02, DCD01, DCD00, DCD13 DCD12 DCD11 DCD10 DCD2 Bit 3 2 Initial value — — 0 0 Read/Write — — W W Bit name Not used Not used DCD21 DCR0 to DCR7 Bit 3 2 0 1 DCD20 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name DCR03– DCR02– DCR01– DCR00– DCR73 DCR72 DCR71 DCR70 All Bits CMOS Buffer On/Off Selection 0 Off (high-impedance) 1 On Correspondence between ports and DCD/DCR bits Register Name Bit 3 Bit 2 Bit 1 Bit 0 DCD0 D3 D2 D1 D0 DCD1 D7 D6 D5 D4 DCD2 — — D9 D8 DCR0 R0 3 R0 2 R0 1 R0 0 DCR1 R1 3 R1 2 R1 1 R1 0 DCR2 R2 3 R2 2 R2 1 R2 0 DCR3 R3 3 R3 2 R3 1 R3 0 DCR4 R4 3 R4 2 R4 1 R4 0 DCR5 R5 3 R5 2 R5 1 R5 0 DCR6 R6 3 R6 2 R6 1 R6 0 DCR7 R7 3 R7 2 R7 1 R7 0 Figure 30 Data Control Registers (DCD, DCR) 51 HD404629R Series Port mode register C (PMRC: $025) Bit 3 2 1 0 Initial value 0 0 0 0 W W Read/Write Bit name PMRC3 W PMRC3 PMRC2 * PMRC1 D11/INT0 mode selection W PMRC0 PMRC0 R13/EVNB mode selection 0 D11 0 R13 1 INT0 1 EVNB PMRC2 D10/STOPC mode selection PMRC1 R20/EVND mode selection 0 D10 0 R20 1 STOPC 1 EVND Note: * PMRC2 is reset to 0 only by RESET input. When STOPC is input in stop mode, PMRC2 is not reset but retains its value. Figure 31 Port Mode Register C (PMRC) Port mode register B (PMRB: $024) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name PMRB3 PMRB3 PMRB2 PMRB1 PMRB0 R03/INT4 mode selection PMRB0 R00/INT1 mode selection 0 R03 0 R00 1 INT4 1 INT1 PMRB2 R02/INT3 mode selection PMRB1 R01/INT2 mode selection 0 R02 0 R01 1 INT3 1 INT2 Figure 32 Port Mode Register B (PMRB) 52 HD404629R Series Timer mode register B2 (TMB2: $013) Bit 3 2 Initial value — — 0 0 Read/Write — — R/W R/W Bit name 0 1 Not used Not used TMB21 TMB20 R10/TOB mode selection TMB21 TMB20 0 0 R10 R10 port 1 TOB Toggle output 0 TOB 0 output 1 TOB 1 output 1 Figure 33 Timer Mode Register B2 (TMB2) Timer mode register C2 (TMC2: $014) Bit 3 2 1 0 Initial value — 0 0 0 Read/Write — R/W R/W R/W TMC21 TMC20 Bit name Not used TMC22 R11/TOC mode selection TMC22 TMC21 TMC20 0 0 0 R11 R11 port 1 TOC Toggle output 0 TOC 0 output 1 TOC 1 output 0 — Not Used TOC PWM output 1 1 0 1 1 0 1 Figure 34 Timer Mode Register C2 (TMC2) 53 HD404629R Series Timer mode register D2 (TMD2: $015) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write R/W R/W R/W R/W TMD23 TMD22 TMD21 TMD20 Bit name R12/TOD mode selection TMD23 TMD22 TMD21 TMD20 0 0 0 0 R12 R12 port 1 TOD Toggle output 0 TOD 0 output 1 TOD 1 output 0 — Not used 1 TOD PWM output ✕ R12 Input capture (R12 port) 1 1 0 1 1 ✕ 1 0 ✕ ✕ : Don’t care Figure 35 Timer Mode Register D2 (TMD2) Serial mode register A (SMRA: $005) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write W W W W Bit name SMRA3 SMRA3 SMRA2 SMRA1 SMRA0 R21/SCK mode selection 0 R21 1 SCK SMRA2 SMRA1 SMRA0 0 0 1 1 0 1 SCK Clock source Prescaler division ratio 0 Output Prescaler ÷2048 1 Output Prescaler ÷512 0 Output Prescaler ÷128 1 Output Prescaler ÷32 0 Output Prescaler ÷8 1 Output Prescaler ÷2 0 Output System clock — 1 Input External clock — Figure 36 Serial Mode Register A (SMRA) 54 HD404629R Series Port mode register A (PMRA: $004) Bit 3 2 1 0 Initial value — — 0 0 — — W W Read/Write Bit name PMRA1 Not used Not used PMRA1 PMRA0 R22/SI mode selection PMRA0 R23/SO mode selection 0 R22 0 R23 1 SI 1 SO Figure 37 Port Mode Register A (PMRA) LCD output register 1 (LOR1: $01D) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W LOR13 LOR12 LOR11 LOR10 Bit name LOR13 R33/SEG4 mode selection LOR11 R31/SEG2 mode selection 0 R33 0 R31 1 SEG4 1 SEG2 LOR12 R32/SEG3 mode selection LOR10 R30/SEG1 mode selection 0 R32 0 R30 1 SEG3 1 SEG1 Figure 38 LCD Output Register 1 (LOR1) 55 HD404629R Series LCD output register 2 (LOR2: $01E) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W LOR23 LOR22 LOR21 LOR20 Bit name LOR23 R43/SEG8 mode selection LOR21 R41/SEG6 mode selection 0 R43 0 R41 1 SEG8 1 SEG6 LOR22 R42/SEG7 mode selection LOR20 R40/SEG5 mode selection 0 R42 0 R40 1 SEG7 1 SEG5 Figure 39 LCD Output Register 2 (LOR2) LCD output register 3 (LOR3: $01F) Bit 3 2 1 0 Initial value — 0 0 0 Read/Write — W W W LOR31 LOR30 Bit name LOR32 Not used LOR32 R70/SEG17–R73/SEG20 mode selection LOR31 R60/SEG13–R63/SEG16 mode selection 0 R70 to R73 0 R60 to R63 1 SEG17–SEG20 1 SEG13–SEG16 LOR30 R50/SEG9–R53/SEG12 mode selection 0 R50 to R53 1 SEG9–SEG12 Figure 40 LCD Output Register 3 (LOR3) 56 HD404629R Series Pull-Up MOS Transistor Control: A program-controlled pull-up MOS transistor is provided for each input/output pin other than input-only pins D 10 and D11 . The on/off status of all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off status of an individual transistor can also be controlled by the port data register (PDR) of the corresponding pin—enabling on/off control of that pin alone (table 23 and figure 41). The on/off status of each transistor and the peripheral function mode of each pin can be set independently. How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be connected to V CC to prevent LSI malfunctions due to noise. These pins must either be pulled up to VCC by their pull-up MOS transistors or by resistors of about 100 kΩ. Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name MIS3 W W W W MIS3 MIS2 MIS1 MIS0 MIS2 CMOS buffer on/off selection for pin R23 /SO Pull-up MOS on/off selection 0 Off 0 On 1 On 1 Off MIS1 MIS0 tRC selection. Refer to figure 18 in the operation modes section. Figure 41 Miscellaneous Register (MIS) 57 HD404629R Series Prescalers The MCU has the following two prescalers, S and W. The prescalers operating conditions are listed in table 25, and the prescalers output supply is shown in figure 42. The timers A–D input clocks except external events, the serial transmit clock except the external clock, and the LCD circuit operating clock are selected from the prescaler outputs, depending on corresponding mode registers. Prescaler Operation Prescaler S: 11-bit counter that inputs the system clock signal. After being reset to $000 by MCU reset, prescaler S divides the system clock. Prescaler S keeps counting, except in watch and subactive modes and at MCU reset. Prescaler W: Five-bit counter that inputs the X1 input clock signal (32-kHz crystal oscillation) divided by eight. After being reset to $00 by MCU reset, prescaler W divides the input clock. Prescaler W can be reset by software. Table 25 Prescaler Operating Conditions Prescaler Input Clock Reset Conditions Stop Conditions Prescaler S System clock (in active and standby mode), Subsystem clock (in subactive mode) MCU reset MCU reset, stop mode, watch mode Prescaler W 32-kHz crystal oscillation MCU reset, software MCU reset, stop mode LCD Subsystem clock Prescaler W Timer A Timer B Timer C System clock Clock selector Prescaler S Timer D Serial Figure 42 Prescaler Output Supply 58 HD404629R Series Timers The MCU has four timer/counters (A to D). • • • • Timer A: Timer B: Timer C: Timer D: Free-running timer Multifunction timer Multifunction timer Multifunction timer Timer A is an 8-bit free-running timer. Timers B–D are 8-bit multifunction timers, whose functions are listed in table 26. The operating modes are selected by software. Table 26 Timer Functions Functions Timer A Timer B Timer C Timer D Clock Prescaler S Available Available Available Available source Prescaler W Available — — — External event — Available — Available Timer Free-running Available Available Available Available functions Time-base Available — — — Event counter — Available — Available Reload — Available Available Available Watchdog — — Available — Input capture — — — Available Timer Toggle — Available Available Available outputs 0 output — Available Available Available 1 output — Available Available Available PWM — — Available Available Note: — implies not available. Timer A Timer A Functions: Timer A has the following functions. • Free-running timer • Clock time-base The block diagram of timer A is shown in figure 43. 59 HD404629R Series 1/4 1/2 2 fW fW twcyc Timer A interrupt request flag (IFTA) Prescaler W (PSW) ÷2 ÷8 ÷ 16 ÷ 32 32.768-kHz oscillator 1/2 twcyc Clock Timer counter A (TCA) Overflow ø PER System clock ÷2 ÷4 ÷8 ÷ 32 ÷ 128 ÷ 512 ÷ 1024 ÷ 2048 Selector Internal data bus Selector Selector Prescaler S (PSS) 3 Timer mode register A (TMA) Data bus Clock line Signal line Figure 43 Block Diagram of Timer A Timer A Operations: • Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA: $008). • Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied to timer A after it has reached • $FF, an overflow is generated, and timer A is reset to $00. The overflow sets the timer A interrupt request flag (IFTA: $001, bit 2). Timer A continues to be incremented after reset to $00, and therefore it generates regular interrupts every 256 clocks. • Clock time-base operation: Timer A is used as a clock time-base by setting bit 3 (TMA3) of timer mode register A (TMA: $008) to 1. The prescaler W output is applied to timer A, and timer A generates interrupts at the correct timing based on the 32.768-kHz crystal oscillation. In this case, prescaler W and timer A can be reset to $00 by software. Registers for Timer A Operation: Timer A operating modes are set by the following registers. • Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A’s operating mode and input clock source as shown in figure 44. 60 HD404629R Series Timer mode register A (TMA: $008) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write W W W W TMA3 TMA2 TMA1 TMA0 Bit name Source Input clock TMA3 TMA2 TMA1 TMA0 prescaler frequency Operating mode 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Timer A mode 0 PSS 2048tcyc 1 PSS 1024tcyc 0 PSS 512tcyc 1 PSS 128tcyc 0 PSS 32tcyc 1 PSS 8tcyc 0 PSS 4tcyc 1 PSS 2tcyc 0 PSW 32tWcyc 1 PSW 16tWcyc 0 PSW 8tWcyc 1 PSW 2tWcyc 0 — 1/2tWcyc 1 — Not used X — Reset PSW and TCA Time-base mode X : Don’t care Note: 1. tWcyc = 244.14 µs (when a 32.768-kHz crystal oscillator is used) 2. Timer counter overflow output period (seconds) = input clock period (seconds) × 256. 3. If PSW of TCA reset is selected while the LCD is operating, LCD operation halts (power switch goes off and all SEG and COM pins are grounded). When an LCD is connected for display, the PSW and TCA reset periods must be set in the program to the minimum. 4. The division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur. Figure 44 Timer Mode Register A (TMA) Timer B Timer B Functions: Timer B has the following functions. • Free-running/reload timer • External event counter • Timer output operation (toggle, 0, and 1 outputs) 61 HD404629R Series The block diagram of timer B is shown in figure 45. Timer B ineterrupt request flag (IFTB) Timer output control logic EVNB Timer read register BL (TRBL) ÷2 Timer read register BU (TRBU) Overflow 4 ÷8 ÷32 ÷128 Timer counter B ÷512 ÷2048 3 Free-runnning/Reload control φPER Selector System clock Prescaler S (PSS) ÷4 (TCBL) (TCBU) 4 4 Timer counter B (TWBL) Timer mode register B1 (TMB1) 2 Timer output control Timer mode register B2 (TMB2) Data bus Clock line Signal line Figure 45 Block Diagram of Timer B 62 (TWBU) Internal data bus TOB HD404629R Series Timer B Operations: • Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register B1 (TMB1: $009). Timer B is initialized to the value set in timer write register B (TWBL: $00A, TWBU: $00B) by software and incremented by one at each clock input. If an input clock is applied to timer B after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer B is initialized to its initial value set in timer write register B; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0). IFTB is reset by software or MCU reset. Refer to figure 3 and table 1 for details. • External event counter operation: Timer B is used as an external event counter by selecting external event input as input clock source. In this case, pin R13/EVNB must be set to EVNB by port mode register C (PMRC: $025). Timer B is incremented by one at each falling edge of signals input to pin EVNB. The other operation is basically the same as the free-running/reload timer operation. • Timer output operation: The following three output modes can be selected for timer B by setting timer mode register B2 (TMB2: $013). Toggle 0 output 1 output By selecting the timer output mode, pin R10/TOB is set to TOB. The output from TOB is reset low by MCU reset. Toggle output: When toggle output mode is selected, the output level is inverted if a clock is input after timer B has reached $FF. By using this function and reload timer function, clock signals can be output at a required frequency for the buzzer. The output waveform is shown in figure 46. 0 output: When 0 output mode is selected, the output level is pulled low if a clock is input after timer B has reached $FF. Note that this function must be used only when the output level is high. 1 output: When 1 output mode is selected, the output level is set high if a clock is input after timer B has reached $FF. Note that this function must be used only when the output level is low. 63 HD404629R Series Toggle output waveform (timers B, C, and D) Free-running timer 256 clock cycles 256 clock cycles Reload timer (256 – N) clock cycles (256 – N) clock cycles PWM output waveform (timers C and D) T × (N + 1) TMC13 = 0 TMD13 = 0 T T × 256 TMC13 = 1 TMD13 = 1 T × (256 – N) Note: The waveform is always fixed low when N = $FF. T: Input clock period to counter (figures 52 and 60) N: The value of the timer write register Figure 46 Timer Output Waveform 64 HD404629R Series Registers for Timer B Operation: By using the following registers, timer B operation modes are selected and the timer B count is read and written. Timer mode register B1 (TMB1: $009) Timer mode register B2 (TMB2: $013) Timer write register B (TWBL: $00A, TWBU: $00B) Timer read register B (TRBL: $00A, TRBU: $00B) Port mode register C (PMRC: $025) • Timer mode register B1 (TMB1: $009): Four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 47. It is reset to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register B1 write instruction. Setting timer B’s initialization by writing to timer write register B (TWBL: $00A, TWBU: $00B) must be done after a mode change becomes valid. Timer mode register B1 (TMB1: $009) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TMB13 TMB12 TMB11 TMB10 Bit name TMB13 Free-running/reload timer selection 0 Free-running timer 1 Reload timer Input clock period and input clock source TMB12 TMB11 TMB10 0 0 0 2048tcyc 1 512tcyc 0 128tcyc 1 32tcyc 0 8tcyc 1 4tcyc 0 2tcyc 1 R13/EVNB (external event input) 1 1 0 1 Figure 47 Timer Mode Register B1 (TMB1) 65 HD404629R Series Timer mode register B2 (TMB2: $013) Bit 3 2 Initial value — — 0 0 TMB21 TMB20 Read/Write — — R/W R/W 0 0 R10 R10 port 1 TOB Toggle output 0 TOB 0 output 1 TOB 1 output Bit name 0 1 Not used Not used TMB21 TMB20 1 R10/TOB mode selection Figure 48 Timer Mode Register B2 (TMB2) • Timer mode register B2 (TMB2: $013): Two-bit read/write register that selects the timer B output mode as shown in figure 48. It is reset to $0 by MCU reset. • Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of the lower digit (TWBL) and the upper digit (TWBU) as shown in figures 49 and 50. The lower digit is reset to $0 by MCU reset, but the upper digit value is invalid. Timer B is initialized by writing to timer write register B. In this case, the lower digit (TWBL) must be written to first, but writing only to the lower digit does not change the timer B value. Timer B is initialized to the value in timer write register B at the same time the upper digit (TWBU) is written to. When timer write register B is written to again and if the lower digit value needs no change, writing only to the upper digit initializes timer B. Timer write register B (lower digit) (TWBL: $00A) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TWBL3 TWBL2 TWBL1 TWBL0 Bit name Figure 49 Timer Write Register B Lower Digit (TWBL) Timer write register B (upper digit) (TWBU: $00B) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined W W W W TWBU3 TWBU2 TWBU1 TWBU0 Figure 50 Timer Write Register B Upper Digit (TWBU) • Timer read register B (TRBL: $00A, TRBU: $00B): Read-only register consisting of the lower digit (TRBL) and the upper digit (TRBU) that holds the count of the timer B upper digit (figures 51 and 52). 66 HD404629R Series The upper digit (TRBU) must be read first. At this time, the count of the timer B upper digit is obtained, and the count of the timer B lower digit is latched to the lower digit (TRBL). After this, by reading TRBL, the count of timer B when TRBU is read can be obtained. Timer read register B (lower digit) (TRBL: $00A) Bit 3 Initial value Read/Write Bit name 2 1 0 Undefined Undefined Undefined Undefined R R R R TRBL3 TRBL2 TRBL1 TRBL0 Figure 51 Timer Read Register B Lower Digit (TRBL) Timer read register B (upper digit) (TRBU: $00B) Bit 3 Initial value 1 0 Undefined Undefined Undefined Undefined Read/Write Bit name 2 R R R R TRBU3 TRBU2 TRBU1 TRBU0 Figure 52 Timer Read Register B Upper Digit (TRBU) • Port mode register C (PMRC: $025): Write-only register that selects R13/EVNB pin function as shown in figure 53. It is reset to $0 by MCU reset. Port mode register C (PMRC: $025) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name PMRC3 PMRC3 PMRC2 PMRC1 PMRC0 D11/INT0 mode selection PMRC1 R20/EVND mode selection 0 D11 0 R20 1 INT0 1 EVND PMRC2 D10/STOPC mode selection PMRC0 R13/EVNB mode selection 0 D10 0 R13 1 STOPC 1 EVNB Figure 53 Port Mode Register C (PMRC) 67 HD404629R Series Timer C Timer C Functions: Timer C has the following functions. • Free-running/reload timer • Watchdog timer • Timer output operation (toggle, 0, 1, and PWM outputs) The block diagram of timer C is shown in figure 54. System reset signal Watchdog on flag (WDON) TOC System clock Timer C interrupt request flag (IFTC) Watchdog timer control logic Timer output control logic ø PER Timer read register CL (TRCL) Timer read register CU (TRCU) ÷2 ÷8 Timer counter C Selector ÷ 512 ÷ 1024 ÷ 2048 3 Timer mode register C1 (TMC1) Free-running/reload control Prescalers ÷ 32 (PSS) ÷ 128 (TCCL) (TCCU) 4 4 Timer write register C (TWCL) 3 Timer output control Data bus Timer mode register C2 (TMC2) Clock line Signal line Figure 54 Block Diagram of Timer C 68 (TWCU) Internal data bus 4 ÷4 HD404629R Series Timer C Operations: • Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register C1 (TMC1: $00D). Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by software and incremented by one at each clock input. If an input clock is applied to timer C after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is initialized to its initial value set in timer write register C; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or MCU reset. Refer to figure 3 and table 1 for details. • Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of control and an overflow is generated, the MCU is reset. Program run can be controlled by initializing timer C by software before it reaches $FF. • Timer output operation: The following four output modes can be selected for timer C by setting timer mode register C2 (TMC2: $014). Toggle 0 output 1 output PWM output By selecting the timer output mode, pin R11/TOC is set to TOC. The output from TOC is reset low by MCU reset. Toggle output: The operation is basically the same as that of timer-B’s toggle output. 0 output: The operation is basically the same as that of timer-B’s 0 output. 1 output: The operation is basically the same as that of timer-B’s 1 output. PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output function. The output waveform differs depending on the contents of timer mode register C1 (TMC1: $00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is shown in figure 46. 69 HD404629R Series Registers for Timer C Operation: By using the following registers, timer C operation modes are selected and the timer C count is read and written. Timer mode register C1 (TMC1: $00D) Timer mode register C2 (TMC2: $014) Timer write register C (TWCL: $00E, TWCU: $00F) Timer read register C (TRCL: $00E, TRCU: $00F) • Timer mode register C1 (TMC1: $00D): Four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 55. It is reset to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register C1 write instruction. Setting timer C’s initialization by writing to timer write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid. Timer mode register C1 (TMC1: $00D) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TMC13 TMC12 TMC11 TMC10 Bit name TMC13 Free-running/reload timer selection 0 Free-running timer 1 Reload timer Input clock period TMC12 TMC11 TMC10 0 0 0 2048tcyc 1 1024tcyc 0 512tcyc 1 128tcyc 0 32tcyc 1 8tcyc 0 4tcyc 1 2tcyc 1 1 0 1 Figure 55 Timer Mode Register C1 (TMC1) • Timer mode register C2 (TMC2: $014): Three-bit read/write register that selects the timer C output mode as shown in figure 56. It is reset to $0 by MCU reset. • Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of the lower digit (TWCL) and the upper digit (TWCU). The operation of timer write register C is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B). • Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of the lower digit (TRCL) and the upper digit (TRCU) that holds the count of the timer C upper digit. The operation of timer read register C is basically the same as that of timer read register B (TRBL: $00A, TRBU: $00B). 70 HD404629R Series Timer mode register C2 (TMC2: $014) Bit 3 2 1 0 Initial value — 0 0 0 — R/W Read/Write Bit name Not used TMC22 R/W R/W TMC21 TMC20 TMC22 TMC21 TMC20 0 0 0 R11 R11 port 1 TOC Toggle output 0 TOC 0 output 1 TOC 1 output 0 — Not used TOC PWM output 1 1 0 R11/TOC mode selection 1 0 1 1 Figure 56 Timer Mode Register C2 (TMC2) Timer write register C (lower digit) (TWCL: $00E) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TWCL3 TWCL2 TWCL1 TWCL0 Bit name Figure 57 Timer Write Register C Lower Digit (TWCL) Timer write register C (upper digit) (TWCU: $00F) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined W W W W TWCU3 TWCU2 TWCU1 TWCU0 Figure 58 Timer Write Register C Upper Digit (TWCU) 71 HD404629R Series Timer read register C (lower digit) (TRCL: $00E) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRCL3 TRCL2 TRCL1 TRCL0 Figure 59 Timer Read Register C Lower Digit (TRCL) Timer read register C (upper digit) (TRCU: $00F) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRCU3 TRCU2 TRCU1 TRCU0 Figure 60 Timer Read Register C Upper Digit (TRCU) 72 HD404629R Series Timer D Timer D Functions: Timer D has the following functions. • • • • Free-running/reload timer External event counter Timer output operation (toggle, 0, 1, and PWM outputs) Input capture timer The block diagram for each operation mode of timer D is shown in figures 61 and 62. Timer D Operations: • Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register D1 (TMD1: $010). Timer D is initialized to the value set in timer write register D (TWDL: $011, TWDU: $012) by software and incremented by one at each clock input. If an input clock is applied to timer D after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer D is initialized to its initial value set in timer write register D; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer D interrupt request flag (IFTD: $003, bit 0). IFTD is reset by software or MCU reset. Refer to figure 3 and table 1 for details. • External event counter operation: Timer D is used as an external event counter by selecting the external event input as an input clock source. In this case, pin R20/EVND must be set to EVND by port mode register C (PMRC: $025). Either falling or rising edge, or both falling and rising edges of input signals can be selected as the external event detection edge by detection edge select register 2 (ESR2: $027). When both rising and falling edges detection is selected, the time between the falling edge and rising edge of input signals must be 2t cyc or longer. Timer D is incremented by one at each detection edge selected by detection edge select register 2 (ESR2: $027). The other operation is basically the same as the free-running/reload timer operation. Timer output operation: The following four output modes can be selected for timer D by setting timer mode register D2 (TMD2: $015). Toggle 0 output 1 output PWM output By selecting the timer output mode, pin R12/TOD is set to TOD. The output from TOD is reset low by MCU reset. Toggle output: The operation is basically the same as that of timer-B’s toggle output. 0 output: The operation is basically the same as that of timer-B’s 0 output. 73 HD404629R Series 1 output: The operation is basically the same as that of timer-B’s 1 output. PWM output: The operation is basically the same as that of timer-C’s PWM output. • Input capture timer operation: The input capture timer counts the clock cycles between trigger edges input to pin EVND. Either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by detection edge select register 2 (ESR2: $027). When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL: $011, TRDU: $012), and the timer D interrupt request flag (IFTD: $003, bit 0) and the input capture status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input capture error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing 0. By selecting the input capture operation, pin R1 2/TOD is set to R1 2 and timer D is reset to $00. 74 HD404629R Series Timer D interrupt request flag (IFTD) EVND Edge detection logic Timer read register øPER Timer read register DL (TRDL) 4 ÷4 ÷ 32 ÷ 128 Timer counter D ÷ 512 ÷ 2048 3 Free-running/reload control ÷8 Selector Prescaler S (PSS) ÷2 DU (TRDU) (TCDL) (TCDU) 4 4 Internal data bus System clock Timer write register D (TWDL) (TWDU) Timer mode register D1 (TMD1) 2 Edge detection control Edge detection selection register 2 (ESR2) Timer mode register D2 (TMD2) Data bus Clock line Timer output control logic Signal line 3 TOD Figure 61 Block Diagram of Timer D (Free-Running/Reload Timer) 75 HD404629R Series Input capture status flag (ICSF) Input capture error flag (ICEF) Timer D interrupt request flag (IFTD) Error control logic System clock Edge detection logic Read signal øPER Timer read register D (TRDL) 4 ÷8 ÷32 ÷128 Timer counter D (TCDL) (TCDU) ÷512 Edge detection control Overflow Input capture timer control ÷2048 3 2 4 ÷4 Selector Prescaler S (PSS) ÷2 (TRDU) Time mode register D1 (TMD1) Edge detection selection register 2 (ESR2) Internal data bus EVND Timer mode register D2 (TMD2) Data bus Clock line Signal line Figure 62 Block Diagram of Timer D (Input Capture Timer) Registers for Timer D Operation: By using the following registers, timer D operation modes are selected and the timer D count is read and written. 76 Timer mode register D1 (TMD1: $010) Timer mode register D2 (TMD2: $015) Timer write register D (TWDL: $011, TWDU: $012) Timer read register D (TRDL: $011, TRDU: $012) HD404629R Series Port mode register C (PMRC: $025) Detection edge select register 2 (ESR2: $027) • Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 63. It is reset to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register D1 (TMD1: $010) write instruction. Setting timer D’s initialization by writing to timer write register D (TWDL: $011, TWDU: $012) must be done after a mode change becomes valid. When selecting the input capture timer operation, select the internal clock as the input clock source. Timer mode register D1 (TMD1: $010) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name TMD13 W W W W TMD13 TMD12 TMD11 TMD10 Free-running/reload timer selection 0 Free-running timer 1 Reload timer Input clock period and input clock source TMD12 TMD11 TMD10 0 0 0 2048tcyc 1 512tcyc 0 128tcyc 1 32tcyc 0 8tcyc 1 4tcyc 0 2tcyc 1 R20/EVND (external event input) 1 1 0 1 Figure 63 Timer Mode Register D1 (TMD1) • Timer mode register D2 (TMD2: $015): Four-bit read/write register that selects the timer D output mode and input capture operation as shown in figure 64. It is reset to $0 by MCU reset. • Timer write register D (TWDL: $011, TWDU: $012): Write-only register consisting of the lower digit (TWDL) and the upper digit (TWDU). The operation of timer write register D is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B). • Timer read register D (TRDL: $011, TRDU: $012): Read-only register consisting of the lower digit (TRDL) and the upper digit (TRDU). The operation of timer read register D is basically the same as that of timer read register B (TRBL: $00A, TRBU: $00B). When the input capture timer operation is selected and if the count of timer D is read after a trigger is input, either the lower or upper digit can be read first. 77 HD404629R Series • Port mode register C (PMRC: $025): Write-only register that selects R20/EVND pin function as shown in figure 53. It is reset to $0 by MCU reset. • Detection edge select register 2 (ESR2: $027): Write-only register that selects the detection edge of signals input to pin EVND as shown in figure 69. It is reset to $0 by MCU reset. Timer mode register D2 (TMD2: $015) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write R/W R/W R/W R/W TMD23 TMD22 TMD21 TMD20 TMD23 TMD22 TMD21 TMD20 0 0 0 0 R12 R12 port 1 TOD Toggle output 0 TOD 0 output 1 TOD 1 output 0 — Not used Bit name 1 1 0 R12/TOD mode selection 1 1 ✕ 1 0 1 TOD PWM output ✕ ✕ R12 Input capture (R12 port) ✕ : Don’t care Figure 64 Timer Mode Register D2 (TMD2) Timer write register D (lower digit) (TWDL: $011) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W TWDL3 TWDL2 TWDL1 TWDL0 Figure 65 Timer Write Register D Lower Digit (TWDL) 78 HD404629R Series Timer write register D (upper digit) (TWDU: $012) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined W W W W TWDU3 TWDU2 TWDU1 TWDU0 Figure 66 Timer Write Register D Upper Digit (TWDU) Timer read register D (lower digit) (TRDL: $011) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRDL3 TRDL2 TRDL1 TRDL0 Figure 67 Timer Read Register D Lower Digit (TRDL) Timer read register D (upper digit) (TRDU: $012) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRDU3 TRDU2 TRDU1 TRDU0 Figure 68 Timer Read Register D Upper Digit (TRDU) 79 HD404629R Series Detection edge register 2 (ESR2: $027) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W ESR23 ESR22 ESR21 ESR20 EVND detection edge ESR23 ESR22 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Double-edge detection* 1 INT4 detection edge ESR21 ESR20 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Double-edge detection* 1 Note: * Both falling and rising edges are detected. Figure 69 Detection Edge Select Register 2 (ESR2) 80 HD404629R Series Note on Use When using the timer output as PWM output, note the following point. From the update of the timer write register untill the occurrence of the overflow interrupt, the PWM output differs from the period and duty settings, as shown in table 27. The PWM output should therefore not be used until after the overflow interrupt following the update of the timer write register. After the overflow, the PWM output will have the set period and duty cycle. Table 27 PWM Output Following Update of Timer Write Register PWM Output Mode Timer Write Register is Updated during High PWM Output Free running Timer write register rewrite (set value is N) Timer Write Register is Updated during Low PWM Output Timer write register rewrite (set value is N) Interrupt request generated T × (255 – N) T × (N + 1) Interrupt request generated T × (N' + 1) T × (255 – N) Timer write register rewrite (set value is N) Reload T Interrupt request generated T × (255 – N) T Timer write register rewrite (set value is N) T × (N + 1) Interrupt request generated T T × (255 – N) T 81 HD404629R Series Serial Interfaces The serial interface serially transfers and receives 8-bit data, and includes the following features. • Multiple transmit clock sources External clock Internal prescaler output clock System clock • Output level control in idle states Five registers, an octal counter, and a multiplexer are also configured for the serial interface as follows. Serial data register (SRL: $006, SRU: $007) Serial mode register A (SMRA: $005) Serial mode register B (SMRB: $028) Miscellaneous register (MIS: $00C) Octal counter (OC) Selector The block diagram of the serial interface is shown in figure 70. 82 HD404629R Series Octal counter (OC) SO Serial interrupt request flag (IFS) Idle control logic Clock I/O control logic Serial data register (SRL/U) Internal data bus SCK SI 1/2 Data bus Transfer control 1/2 Selector ÷2 ÷8 ÷32 ÷128 ÷512 ÷2048 Selector øPER Prescalers (PSS) System clock Serial mode register A (SMRA) Serial mode register B (SMRB) Clock line Signal line Figure 70 Block Diagram of Serial Interface 83 HD404629R Series Serial Interface Operation Selecting and Changing the Operating Mode: Table 28 lists the serial interface’s operating modes. To select an operating mode, use one of these combinations of port mode register A (PMRA: $004) and serial mode register A (SMRA: $005) settings; to change the operating mode, always initialize the serial interface internally by writing data to serial mode register A. Note that the serial interface is initialized by writing data to serial mode register A. Refer to the following Serial Mode Register A section for details. Pin Setting: The R21/SCK pin is controlled by writing data to serial mode register A (SMRA: $005). The R2 2/SI and R23/SO pins are controlled by writing data to port mode register A (PMRA: $004). Refer to the following Registers for Serial Interface section for details. Transmit Clock Source Setting: The transmit clock source is set by writing data to serial mode register A (SMRA: $005) and serial mode register B (SMRB: $028). Refer to the following Registers for Serial Interface section for details. Data Setting: Transmit data is set by writing data to the serial data register (SRL: $006, SRU: $007). Receive data is obtained by reading the contents of the serial data register. The serial data is shifted by the transmit clock and is input from or output to an external system. The output level of the SO pin is invalid until the first data is output after MCU reset, or until the output level control in idle states is performed. Table 28 Serial Interface Operating Modes SMRA PMRA Bit 3 Bit 1 Bit 0 Operating Mode 1 0 0 Continuous clock output mode 1 Transmit mode 0 Receive mode 1 Transmit/receive mode 1 Transfer Control: The serial interface is activated by the STS instruction. The octal counter is reset to 000 by this instruction, and it increments at the rising edge of the transmit clock. When the eighth transmit clock signal is input or when serial transmission/receive is discontinued, the octal counter is reset to 000, the serial interrupt request flag (IFS: $023, bit 2) is set, and the transfer stops. When the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4tcyc to 8192tcyc by setting bits 2 to 0 (SMRA2– SMRA0) of serial mode register A (SMRA: $005) and bit 0 (SMRB0) of serial mode register B (SMRB: $028) as listed in table 29. 84 HD404629R Series Table 29 Serial Transmit Clock (Prescaler Output) SMRB SMRA Bit 0 Bit 2 Bit 1 Bit 0 Prescaler Division Ratio Transmit Clock Frequency 0 0 0 0 ÷ 2048 4096t cyc 1 ÷ 512 1024t cyc 0 ÷ 128 256t cyc 1 ÷ 32 64t cyc 0 ÷8 16t cyc 1 ÷2 4t cyc 0 ÷ 4096 8192t cyc 1 ÷ 1024 2048t cyc 0 ÷ 256 512t cyc 1 ÷ 64 128t cyc 0 ÷ 16 32t cyc 1 ÷4 8t cyc 1 1 1 0 0 0 1 1 0 Operating States: The serial interface has the following operating states; transitions between them are shown in figure 71. STS wait state Transmit clock wait state Transfer state Continuous clock output state (only in internal clock mode) • STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 71). In STS wait state, the serial interface is initialized and the transmit clock is ignored. If the STS instruction is then executed (01, 11), the serial interface enters transmit clock wait state. • Transmit clock wait state: Transmit clock wait state is between the STS execution and the falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments the octal counter, shifts the serial data register, and enters the serial interface in transfer state. However, note that if continuous clock output mode is selected in internal clock mode, the serial interface does not enter transfer state but enters continuous clock output state (17). The serial interface enters STS wait state by writing data to serial mode register A (SMRA: $005) (04, 14) in transmit clock wait state. • Transfer state: Transfer state is between the falling edge of the first clock and the rising edge of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In internal clock mode, the transmit clock stops after outputting eight clocks. 85 HD404629R Series In transfer state, writing data to serial mode register A (SMRA: $005) (06, 16) initializes the serial interface, and STS wait state is entered. If the state changes from transfer to another state, the serial interrupt request flag (IFS: $023, bit 2) is set by the octal counter that is reset to 000. • Continuous clock output state (only in internal clock mode): Continuous clock output state is entered only in internal clock mode. In this state, the serial interface does not transmit/ receive data but only outputs the transmit clock from the SCK pin. When bits 1 and 0 (PMRA1, PMRA0) of port mode register A (PMRA: $004) are 00 in transmit clock wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state. If serial mode register A (SMRA: $005) is written to in continuous clock output mode (18), STS wait state is entered. External clock mode STS wait state (Octal counter = 000, transmit clock disabled) SMRA write 00 MCU reset 06 SMRA write (IFS ← 1) 04 01 STS instruction 02 Transmit clock Transmit clock wait state (Octal counter = 000) 03 8 transmit clocks Transfer state (Octal counter = 000) 05 STS instruction (IFS ← 1) Internal clock mode SMRA write 18 Continuous clock output state (PMRA 0, 1 = 00) STS wait state (Octal counter = 000, transmit clock disabled) 10 13 SMRA write 14 11 STS instruction MCU reset 8 transmit clocks 16 SMRA write (IFS ←1) Transmit clock 17 12 Transmit clock Transmit clock wait state (Octal counter = 000) Transfer state (Octal counter = 000) 15 STS instruction (IFS ← 1) Note: Refer to the Operating States section for the corresponding encircled numbers. Figure 71 Serial Interface State Transitions Output Level Control in Idle States: In idle states, that is, STS wait state and transmit clock wait state, the output level of the SO pin can be controlled by setting bit 1 (SMRB1) of serial mode register B (SMRB: $028) to 0 or 1. The output level control example is shown in figure 72. Note that the output level cannot be controlled in transfer state. 86 , HD404629R Series Transmit clock wait state State STS wait state Transmit clock wait state Transfer state STS wait state MCU reset Port selection PMRA write External clock selection SMRA write Output level control in idle states Dummy write for state transition Output level control in idle states SMRB write Data write for transmission SRL, SRU write STS instruction SCK pin (input) SO pin Undefined Idle LSB MSB Idle IFS External clock mode Flag reset at transfer completion Transmit clock wait state State STS wait state Transfer state STS wait state MCU reset Port selection PMRA write Internal clock selection SMRA write Output level control in idle states SMRB write Output level control in idle states Data write for transmission SRL, SRU write STS instruction SCK pin (output) SO pin Undefined Idle LSB MSB Idle IFS Internal clock mode Flag reset at transfer completion Figure 72 Example of Serial Interface Operation Sequence 87 HD404629R Series Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit clock error of this type can be detected as shown in figure 73. 88 , HD404629R Series Transfer completion (IFS ← 1) Interrupts inhibited IFS ← 0 SMRA write IFS = 1? Yes Transmit clock error processing No Normal termination Transmit clock error detection flowchart Transmit clock wait state Transmit clock wait state Transfer state State SCK pin (input) Transfer state Noise 1 SMRA write IFS 2 3 4 5 6 7 8 Transfer state has been entered by the transmit clock error. When SMRA is written, IFS is set. Flag set because octal counter reaches 000 Flag reset at transfer completion Transmit clock error detection procedure Figure 73 Transmit Clock Error Detection 89 HD404629R Series If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $023, bit 2) is set, and transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is entered. After the transfer completion processing is performed and IFS is reset, writing to serial mode register A (SMRA: $005) changes the state from transfer to STS wait. At this time IFS is set again, and therefore the error can be detected. Notes on Use: • Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode register A (SMRA: $005) again. • Serial interrupt request flag (IFS: $023, bit 2) set: If the state is changed from transfer to another by writing to serial mode register A (SMRA: $005) or executing the STS instruction during the first low pulse of the transmit clock, the serial interrupt request flag is not set. To set the serial interrupt request flag, serial mode register A write or STS instruction execution must be programmed to be executed after confirming that the SCK pin is at 1, that is, after executing the input instruction to port R2. Registers for Serial Interface The serial interface operation is selected, and serial data is read and written by the following registers. Serial Mode Register A (SMRA: $005) Serial Mode Register B (SMRB: $028) Serial Data Register (SRL: $006, SRU: $007) Port Mode Register A (PMRA: $004) Miscellaneous Register (MIS: $00C) Serial Mode Register A (SMRA: $005): This register has the following functions (figure 74). R2 1/SCK pin function selection Transfer clock selection Prescaler division ratio selection Serial interface initialization Serial mode register A (SMRA: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset. A write signal input to serial mode register A (SMRA: $005) discontinues the input of the transmit clock to the serial data register and octal counter, and the octal counter is reset to 000. Therefore, if a write is performed during data transfer, the serial interrupt request flag (IFS: $023, bit 2) is set. Written data is valid from the second instruction execution cycle after the write operation, so the STS instruction must be executed at least two cycles after that. 90 HD404629R Series Serial mode register A (SMRA: $005) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name SMRA3 SMRA3 SMRA2 SMRA1 SMRA0 R21/SCK mode selection 0 R21 1 SCK SCK Prescaler Clock source division ratio Output Prescaler Refer to table 29 0 Output System clock — 1 Input External clock — SMRA2 SMRA1 SMRA0 0 0 0 1 1 0 1 1 0 0 1 1 Figure 74 Serial Mode Register A (SMRA) Serial Mode Register B (SMRB: $028): This register has the following functions (figure 75). Prescaler division ratio selection Output level control in idle states Serial mode register B is a 2-bit write-only register. It cannot be written during data transfer. By setting bit 0 (SMRB0) of this register, the prescaler division ratio is selected. Only bit 0 (SMRB0) can be reset to 0 by MCU reset. By setting bit 1 (SMRB1), the output level of the SO pin is controlled in idle states. The output level changes at the same time that SMRB1 is written to. 91 HD404629R Series Serial mode register B (SMRB: $028) Bit 3 2 1 0 Initial value — — Undefined 0 Read/Write — — W W Bit name SMRB1 Not used Not used SMRB1 Output level control in idle states SMRB0 SMRB0 Transmit clock division ratio 0 Low level 0 Prescaler output divided by 2 1 High level 1 Prescaler output divided by 4 Figure 75 Serial Mode Register B (SMRB) Serial Data Register (SRL: $006, SRU: $007): This register has the following functions (figures 76 and 77). Transmission data write and shift Receive data shift and read Writing data in this register is output from the SO pin, LSB first, synchronously with the falling edge of the transmit clock; data is input, LSB first, through the SI pin at the rising edge of the transmit clock. Input/output timing is shown in figure 78. Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the accuracy of the resultant data cannot be guaranteed. Serial data register (lower digit) (SRL: $006) Bit 3 Initial value 2 1 0 Undefined Undefined Undefined Undefined Read/Write R/W R/W R/W R/W Bit name SR3 SR2 SR1 SR0 Figure 76 Serial Data Register (SRL) 92 HD404629R Series Serial data register (upper digit) (SRU: $007) Bit Initial value 1 2 3 0 Undefined Undefined Undefined Undefined Read/Write R/W R/W R/W R/W Bit name SR7 SR6 SR5 SR4 Figure 77 Serial Data Register (SRU) Transmit clock 1 Serial output data 2 3 4 5 6 LSB 7 8 MSB Serial input data latch timing Figure 78 Serial Interface Output Timing Port Mode Register A (PMRA: $004): This register has the following functions (figure 79). R2 2/SI pin function selection R2 3/SO pin function selection Port mode register A (PMRA: $004) is a 2-bit write-only register, and is reset to $0 by MCU reset. Port mode register A (PMRA: $004) Bit 3 2 1 0 Initial value — — 0 0 Read/Write — — W W Bit name PMRA1 Not used Not used PMRA1 PMRA0 R22/SI mode selection PMRA0 R23/SO mode selection 0 R22 0 R23 1 SI 1 SO Figure 79 Port Mode Register A (PMRA) 93 HD404629R Series Miscellaneous Register (MIS: $00C): This register has the following function (figure 80). R2 3/SO pin PMOS control Miscellaneous register (MIS: $00C) is a 4-bit write-only register and is reset to $0 by MCU reset. Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W MIS3 MIS2 MIS1 MIS0 Bit name MIS3 Pull-up MOS on/off selection 0 Off 1 On MIS2 On 1 Off MIS0 0 0 tRC 0.12207 ms 0.24414 ms R23/SO PMOS on/off selection 0 MIS1 1 1 7.8125 ms 0 31.25 ms 1 Not used Figure 80 Miscellaneous Register (MIS) A/D Converter The MCU has a built-in A/D converter that uses a successive approximation method with a resistor ladder. It can measure four analog inputs with 8-bit resolution. As shown in the block diagram of figure 81, the A/D converter has a 4-bit A/D mode register, a 1-bit A/D start flag, and a 4-bit plus 4-bit A/D data register. 94 HD404629R Series A/D interrupt request flag (IFAD) Encoder Selector AN0 AN1 AN2 AN3 + COMP – A/D control logic A/D data register (ADR) Conversion time control Internal data bus A/D mode register (AMR) 2 A/D start flag (ADSF) Off in stop, watch, and subactive modes AVCC AVSS Resistance ladder Data bus Signal line Figure 81 Block Diagram of A/D Converter A/D Mode Register (AMR: $016): Four-bit write-only register which selects the A/D conversion period and indicates analog input pin information. Bit 0 of the A/D mode register selects the A/D conversion period, and bits 3 and 2 select a channel, as shown in figure 82. 95 HD404629R Series A/D mode register (AMR: $016) Bit 3 2 1 0 Initial value 0 0 — 0 Read/Write W W — W Bit name AMR3 AMR2 Not used Analog input selection AMR0 AMR3 AMR2 0 0 AN0 0 34tcyc 0 1 AN1 1 67tcyc 1 0 AN2 1 1 AN3 AMR0 Conversion time Figure 82 A/D Mode Register (AMR) A/D Data Register (ADRL: $017, ADRU: $018): Eight-bit read-only register consisting of a 4-bit lower digit and 4-bit upper digit. This register is not cleared by reset. After the completion of A/D conversion, the resultant eight-bit data is held in this register until the start of the next conversion (figures 83, 84, and 85). ADRU: $018 3 2 1 ADRL: $017 0 3 2 1 MSB LSB Bit 7 Bit 0 Figure 83 A/D Data Registers (ADRU, ADRL) 96 0 HD404629R Series A/D data register (lower digit) (ADRL: $017) Bit 3 2 1 0 Initial value 0 0 0 0 R R R R ADRL3 ADRL2 ADRL1 ADRL0 Read/Write Bit name Figure 84 A/D Data Register Lower Digit (ADRL) A/D data register (upper digit) (ADRU: $018) Bit 3 2 1 0 Initial value 1 0 0 0 Read/Write R R R R ADRU3 ADRU2 Bit name ADRU1 ADRU0 Figure 85 A/D Data Register Upper Digit (ADRU) A/D Start Flag (ADSF: $020, Bit 2): One-bit flag that initiates A/D conversion when set to 1. At the completion of A/D conversion, the converted data is stored in the A/D data register and the A/D start flag is cleared. Refer to figure 86. A/D start flag (ADSF: $020, bit 2) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write R/W R/W R/W R/W DTON ADSF WDON LSON Bit name DTON WDON Refer to the description of operating modes Refer to the description of timers LSON ADSF (A/D start flag) 1 A/D conversion started 0 A/D conversion completed Refer to the description of operating modes Figure 86 A/D Start Flag (ADSF) 97 HD404629R Series Note on Use: Use the SEM and SEMD instructions to write data to the A/D start flag (ADSF: $020, bit 2), but make sure that the A/D start flag is not written to during A/D conversion. Data read from the A/D data register (ADRL: $017, ADRU: $018) during A/D conversion cannot be guaranteed. The A/D converter does not operate in the stop, watch, and subactive modes because of the OSC clock. During these low-power dissipation modes, current through the resistor ladder is cut off to decrease the power input. DTMF Generation Circuit The MCU provides a dual-tone multifrequency (DTMF) generation circuit. The DTMF signal consists of two sine waves to access the switching system. Figure 87 shows the DTMF keypad and frequencies. Each key enables tones to be generated corresponding to each frequency. Figure 88 shows a block diagram of the DTMF circuit. The OSC clock (400 kHz, 800 kHz, 2 MHz, or 4 MHz) is changed into four clock signals through the division circuit (1/2, 1/5, and 1/10). The DTMF circuit uses one of the four clock signals, which is selected by the system clock select register (SSR: $029) depending on the OSC clock frequency. The DTMF circuit has transformed programmable dividers, sine wave counters, and control registers. 1 2 3 A R1 (697 Hz) 4 5 6 B R2 (770 Hz) 7 8 9 C R3 (852 Hz) * 0 # D R4 (941 Hz) C1 (1,209 Hz) C2 (1,336 Hz) C3 (1,477 Hz) C4 (1,633 Hz) The DTMF generation circuit is controlled by the following three registers. Figure 87 DTMF Keypad and Frequencies 98 HD404629R Series Transformation program divider 2 Feedback VT ref Tone generator mode register (TGM) TONER output control Transformation program divider Sine wave counter D/A TONEC 2 Feedback Tone generator control register (TGC) TONEC output control 2 f OSC 400 kHz 800 kHz 2 MHz 4 MHz Data bus Internal data bus Sine wave counter D/A TONER 1/2 1/5 400 kHz Selector System clock selection register (SSR) 1/10 Clock line Signal line Figure 88 Block Diagram of DTMF Circuit 99 HD404629R Series Tone Generator Mode Register (TGM: $019): Four-bit write-only register, which controls output frequencies as shown in figure 89, and is reset to $0 by MCU reset. Tone generator mode register (TGM: $019) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TGM3 TGM2 TGM1 TGM0 Bit name TONER output frequencies TGM1 TGM0 fC1 (1,209 Hz) 0 0 fR1 (697 Hz) 1 fC2 (1,336 Hz) 0 1 fR2 (770 Hz) 1 0 fC3 (1,477 Hz) 1 0 fR3 (852 Hz) 1 1 fC4 (1,633 Hz) 1 1 fR4 (941 Hz) TGM3 TGM2 0 0 0 TONEC output frequencies Figure 89 Tone Generator Mode Register (TGM) Tone Generator Control Register (TGC: $01A): Three-bit write-only register, which controls the start/stop of the DTMF signal output as shown in figure 90, and is reset to $0 by MCU reset. TONER and TONEC output can be independently controlled by bits 3 and 2 (TGC3, TGC2), and the DTMF circuit is controlled by bit 1 (TGC1) of this register. Tone generator control register (TGC: $01A) Bit 3 2 1 0 Initial value 0 0 0 — Read/Write W W W — TGC3 TGC2 TGC1 Not used Bit name TGC3 TONEC output control (column) TGC1 DTMF enable bit 0 No output 0 DTMF disable 1 TONEC output (active) 1 DTMF enable TGC2 TONER output control (row) 0 No output 1 TONER output (active) Figure 90 Tone Generator Control Register (TGC) 100 HD404629R Series System Clock Select Register (SSR: $029): Four-bit write-only register. This register must be set to the value specified in figure 91 depending on the frequency of the oscillator connected to the OSC1 and OSC2 pins. Note that if the combination of the oscillation frequency and the value in this register is different from that specified in figure 91, the DTMF output frequencies will differ from the correct frequencies as listed in figure 89. System clock select register (SSR: $029) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W SSR3 SSR2 SSR1 SSR0 Bit name SSR3 32-kHz oscillation stop SSR1 SSR0 System clock selection 0 Oscillation operates in stop mode 0 0 400 kHz 1 Oscillation stops in stop mode 0 1 800 kHz 1 0 2 MHz 1 1 4 MHz SSR2 32-kHz oscillation division ratio selection 0 fSUB = fX/8 1 fSUB = fX/4 Note: SSR3 is cleared only by a RESET input. SSR3 will not be cleared by a STOPC input during stop mode, and will retain its value. SSR3 will also not be cleared upon entering stop mode. Figure 91 System Clock Select Register (SSR) 101 HD404629R Series DTMF Output: The sine waves of the row-group and column-group are individually converted in the D/A conversion circuit which provides a high-precision ladder resistance. The DTMF output pins (TONER, TONEC) transmit the sine waves of the row-group and column-group, respectively. Figure 92 shows the tone output equivalent circuit. Figure 93 shows the output waveform. One cycle of this wave consists of 32 slots. Therefore, the output waveform is stable with little distortion. Table 30 lists the frequency deviation of the MCU from standard DTMF signals. Table 30 Frequency Deviation of the MCU from Standard DTMF Standard DTMF (Hz) MCU (Hz) Deviation from Standard (%) R1 697 694.44 –0.37 R2 770 769.23 –0.10 R3 852 851.06 –0.11 R4 941 938.97 –0.22 C1 1,209 1,212.12 0.26 C2 1,336 1,333.33 –0.20 C3 1,477 1,481.48 0.30 C4 1,633 1,639.34 0.39 Note: This frequency deviation value does not include the frequency deviation due to the oscillator element. Also note that in this case the ratio of the high level and low level widths in the oscillator waveform due to the oscillator element will be 50%:50%. Switch control VT ref GND TONER TONEC Figure 92 Tone Output Equivalent Circuit 102 HD404629R Series VTref 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GND Time slot Figure 93 Waveform of Tone Output 103 HD404629R Series LCD Controller/Driver The MCU has an LCD controller and driver which drive 4 common signal pins and 52 segment pins. The controller consists of a RAM area in which display data is stored, a display control register (LCR: $01B), and a duty-cycle/clock-control register (LMR: $01C) (figure 94). Four duty cycles and the LCD clock are programmable, and a built-in dual-port RAM ensures that display data can be automatically transmitted to the segment signal pins without program intervention. If a 32-kHz oscillation clock is selected as the LCD clock source, the LCD can even be used in watch mode, in which the system clock stops. VCC Internal LCD power supply switch COM2 COM3 V2 Common signal output circuit V3 LCD control register (LCR) GND COM4 Pin control 4 LCD output register 1 (LOR1) 4 LCD output register 2 (LOR2) LCD output register 3 (LOR3) 3 Display control SEG1 2 SEG4 Display data 52 SEG5 SEG8 Internal data bus COM1 LCD power supply control circuit V1 Segment signal output circuit 2 Dual-port display RAM (52 digits) Duty selection Clock SEG9 SEG20 Selector 2 CL3 CL2 CL1 SEG52 CL0 SEG21 LCD mode register (LMR) Data bus Clock line Note: Pin function switching circuit Signal line Figure 94 Block Diagram of Liquid Crystal Display Control System 104 HD404629R Series LCD Data Area and Segment Data ($050–$083): As shown in figure 95, each bit of the storage area corresponds to one of four duty cycles. If data is written to an area corresponding to a certain duty cycle, it is automatically output to the corresponding segments as display data. RAM address RAM address Bit 3 Bit 2 Bit 1 Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 $050 SEG1 SEG1 SEG1 SEG1 $06A SEG27 SEG27 SEG27 SEG27 $051 SEG2 SEG2 SEG2 SEG2 $06B SEG28 SEG28 SEG28 SEG28 $052 SEG3 SEG3 SEG3 SEG3 $06C SEG29 SEG29 SEG29 SEG29 $053 SEG4 SEG4 SEG4 SEG4 $06D SEG30 SEG30 SEG30 SEG30 $054 SEG5 SEG5 SEG5 SEG5 $06E SEG31 SEG31 SEG31 SEG31 $055 SEG6 SEG6 SEG6 SEG6 $06F SEG32 SEG32 SEG32 SEG32 $056 SEG7 SEG7 SEG7 SEG7 $070 SEG33 SEG33 SEG33 SEG33 $057 SEG8 SEG8 SEG8 SEG8 $071 SEG34 SEG34 SEG34 SEG34 $058 SEG9 SEG9 SEG9 SEG9 $072 SEG35 SEG35 SEG35 SEG35 $059 SEG10 SEG10 SEG10 SEG10 $073 SEG36 SEG36 SEG36 SEG36 $05A SEG11 SEG11 SEG11 SEG11 $074 SEG37 SEG37 SEG37 SEG37 $05B SEG12 SEG12 SEG12 SEG12 $075 SEG38 SEG38 SEG38 SEG38 $05C SEG13 SEG13 SEG13 SEG13 $076 SEG39 SEG39 SEG39 SEG39 $05D SEG14 SEG14 SEG14 SEG14 $077 SEG40 SEG40 SEG40 SEG40 $05E SEG15 SEG15 SEG15 SEG15 $078 SEG41 SEG41 SEG41 SEG41 $05F SEG16 SEG16 SEG16 SEG16 $079 SEG42 SEG42 SEG42 SEG42 $060 SEG17 SEG17 SEG17 SEG17 $07A SEG43 SEG43 SEG43 SEG43 $061 SEG18 SEG18 SEG18 SEG18 $07B SEG44 SEG44 SEG44 SEG44 $062 SEG19 SEG19 SEG19 SEG19 $07C SEG45 SEG45 SEG45 SEG45 $063 SEG20 SEG20 SEG20 SEG20 $07D SEG46 SEG46 SEG46 SEG46 $064 SEG21 SEG21 SEG21 SEG21 $07E SEG47 SEG47 SEG47 SEG47 $065 SEG22 SEG22 SEG22 SEG22 $07F SEG48 SEG48 SEG48 SEG48 $066 SEG23 SEG23 SEG23 SEG23 $080 SEG49 SEG49 SEG49 SEG49 $067 SEG24 SEG24 SEG24 SEG24 $081 SEG50 SEG50 SEG50 SEG50 $068 SEG25 SEG25 SEG25 SEG25 $082 SEG51 SEG51 SEG51 SEG51 $069 SEG26 SEG26 SEG26 SEG26 $083 SEG52 SEG52 SEG52 SEG52 COM4 COM3 COM2 COM1 COM4 COM3 COM2 COM1 Figure 95 Configuration of LCD RAM Area (for Dual-Port RAM) 105 HD404629R Series LCD Control Register (LCR: $01B): Three-bit write-only register which controls LCD blanking, on/off switching of the liquid-crystal display’s power supply division resistor, and display in watch and subactive modes, as shown in figure 96. • Blank/display Blank: Segment signals are turned off, regardless of LCD RAM data setting. Display: LCD RAM data is output as segment signals. • Power switch on/off Off: The power switch is off. On:The power switch is on and V1 is VCC. • Watch/subactive mode display Off: In watch and subactive modes, all common and segment pins are grounded and the liquid-crystal power switch is turned off. On: In watch and subactive modes, LCD RAM data is output as segment signals. LCD display control register (LCR: $01B) Bit 3 2 1 0 Initial value — 0 0 0 Read/Write — W W W Not used LCR2 LCR1 LCR0 Bit name LCR2 Display on/off selection in watch and subactive modes 0 Off 1 On LCR1 Power switch on/off 0 Off 1 On LCR0 Blank/display 0 Blank 1 Display Figure 96 LCD Control Register (LCR) 106 HD404629R Series LCD Duty-Cycle/Clock Control Register (LMR: $01C): Four-bit write-only register which selects the display duty cycle and LCD clock source, as shown in figure 97. The dependence of frame frequency on duty cycle is listed in table 31. LCD duty cycle/clock control register (LMR: $01C) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write W W W W LMR3 LMR2 LMR1 LMR0 Bit name LMR3 LMR2 0 0 0 Input clock source selection Duty cycle selection LMR1 LMR0 CL0 (32.768-kHz × duty/64: when 32.768-kHz oscillation is used) 0 0 1/4 duty 0 1 1/3 duty 1 CL1 (fOSC × duty cycle/1024) 1 0 1/2 duty 1 0 CL2 (fOSC × duty cycle/8192) 1 1 Static 1 1 CL3 (refer to table 31) Figure 97 LCD Duty-Cycle/Clock Control Register (LMR) 107 HD404629R Series Table 31 LCD Frame Frequencies for Different Duty Cycles Frame Frequencies fOSC = 400 kHz fOSC = 800 kHZ fOSC = 2 MHz fOSC = 4 MHz Duty Cycle LMR3 LMR2 Static 0 0 CL0 1 CL1 390.6 Hz 781.3 Hz 1953 Hz 3906 Hz 0 CL2 48.8 Hz 97.7 Hz 244.1 Hz 488.3 Hz 1 CL3* 24.4 Hz 48.8 Hz 122.1 Hz 244.1 Hz 1 512 Hz 64 Hz 1/2 0 1 0 CL0 256 Hz 1 CL1 195.3 Hz 390.6 Hz 976.6 Hz 1953 Hz 0 CL2 24.4 Hz 48.8 Hz 122.1 Hz 244.1 Hz 1 CL3* 12.2 Hz 24.4 Hz 61 Hz 122.1 Hz 32 Hz 1/3 0 1 0 CL0 170.7 Hz 1 CL1 130.2 Hz 260.4 Hz 651 Hz 1302 Hz 0 CL2 16.3 Hz 32.6 Hz 81.4 Hz 162.8 Hz 1 CL3* 8.1 Hz 16.3 Hz 40.7 Hz 81.4 Hz 21.3 Hz 1/4 0 1 0 CL0 128 Hz 1 CL1 97.7 Hz 195.3 Hz 488.3 Hz 976.6 Hz 0 CL2 12.2 Hz 24.4 Hz 61 Hz 122.1 Hz 1 CL3* 6.1 Hz 12.2 Hz 30.5 Hz 61 Hz 16 Hz Note: * The division ratio depends on the value of bit 3 of timer mode register A (TMA). Upper value: When TMA3 = 0, CL3 = f OSC × duty cycle/16384. Lower value: When TMA3 = 1, CL3 = 32.768 kHz × duty cycle/512. 108 HD404629R Series LCD Output Register 1 (LOR1: $01D): Write-only register used to specify ports R30–R33 as pins SEG1– SEG4 by individual pins (figure 98). LCD output register 1 (LOR1: $01D) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write W W W W LOR13 LOR12 LOR11 LOR10 Bit name LOR13 R33/SEG4 mode selection LOR11 R31/SEG2 mode selection 0 R33 0 R31 1 SEG4 1 SEG2 LOR12 LOR10 R32/SEG3 mode selection R30/SEG1 mode selection 0 R32 0 R30 1 SEG3 1 SEG1 Figure 98 LCD Output Register 1 (LOR1) LCD Output Register 2 (LOR2: $01E): Write-only register used to specify ports R40–R43 as pins SEG5– SEG8 by individual pins (figure 99). LCD output register 2 (LOR2: $01E) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name LOR23 W W W W LOR23 LOR22 LOR21 LOR20 R43/SEG8 mode selection LOR21 R41/SEG6 mode selection 0 R43 0 R41 1 SEG8 1 SEG6 LOR22 R42/SEG7 mode selection LOR20 R40/SEG5 mode selection 0 R42 0 R40 1 SEG7 1 SEG5 Figure 99 LCD Output Register 2 (LOR2) 109 HD404629R Series LCD Output Register 3 (LOR3: $01F): Write-only register used to specify ports R5–R7 as pins SEG9– SEG20 in 4-pin units (figure 100). LCD output register 3 (LOR3: $01F) Bit 3 Initial value — 0 0 0 Read/Write — W W W LOR31 LOR30 Bit name LOR32 2 Not used LOR32 1 0 R70/SEG17–R73/SEG20 mode selection LOR30 R50/SEG9–R53/SEG12 mode selection 0 R70-R73 0 R50-R53 1 SEG17–SEG20 1 SEG9–SEG12 LOR31 R60/SEG13–R63/SEG16 mode selection 0 R60-R63 1 SEG13–SEG16 Figure 100 LCD Output Register 3 (LOR3) Large Liquid-Crystal Panel Drive and V LCD : To drive a large-capacity LCD, decrease the resistance of the built-in division resistors by attaching external resistors in parallel, as shown in figure 101. The size of these resistors cannot be simply calculated from the LCD load capacitance because the matrix configuration of the LCD complicates the paths of charge/discharge currents flowing through the capacitors—the resistance will also vary with lighting conditions. This size must be determined by trialand-error, taking into account the power dissipation of the device using the LCD, but a resistance of 1 to 10 kΩ would usually be suitable. (Another effective method is to attach capacitors of 0.1 to 0.3 µF.) Always turn off the power switch (set bit 1 of the LCR to 0) before changing the liquid-crystal drive voltage (VLCD). 110 HD404629R Series VCC (V 1 ) VCC (V 1 ) R R C V2 V2 R R C V3 V3 C R R GND GND VCC VCC VLCD COM1 1 6-digit LCD with sign . V1 SEG1 V2 to V3 SEG52 GND 52 Static drive VCC VCC VLCD COM1 COM2 2 . V1 SEG1 V2 to V3 SEG52 GND 13-digit LCD 52 1/2 duty, 1/2 bias drive VCC VLCD VCC COM1 to COM3 V1 V2 SEG1 to V3 GND SEG52 3 17-digit LCD with sign . 52 1/3 duty, 1/3 bias drive VCC VCC ≥ V LCD ≥ GND VLCD VCC COM1 to COM4 V1 V2 SEG1 to V3 GND SEG52 4 . 26-digit LCD 52 1/4 duty, 1/3 bias drive Figure 101 LCD Connection Examples 111 HD404629R Series ZTATTM Microcomputer with Built-in programmable ROM Programming of Built-in programmable ROM The MCU can stop its function as an MCU in PROM mode for programming the built-in PROM. PROM mode is set up by setting the TEST, M0, and M1 terminals to “Low” level and the RESET terminal to “High” level. Writing and reading specifications of the PROM are the same as those for the commercial EPROM27256. Using a socket adapter for specific use of each product, programming is possible with a general-purpose PROM writer. Since an instruction of the HMCS400 series is 10 bits long, a conversion circuit is incorporated to adapt the general-purpose PROM writer. This circuit splits each instruction into five lower bits and five higher bits to write from or read to two addresses. This enables use of a general-purpose PROM. For instance, to write to a 16kword of built-in PROM with a general-purpose PROM writer, specify 32kbyte address ($0000-$7FFF). Notes: 1. When programming with a PROM writer, set up each ROM size to the address given in table b. If it is programmed erroneously to an address given in Table 33 or later, check of writing of PROM may become impossible. Particularly, caution should be exercised in the case of a plastic package since reprogramming is impossible with it. Set the data in unused addresses to $FF. 2. If the indexes of the PROM writer socket, socket adapter and product are not aligned precisely, the product may break down due to overcurrent. Be sure to check that they are properly set to the writer before starting the writing process. 3. Two levels of program voltages (VPP) are available for the PROM: 12.5 V and 21 V. Our product employs a V PP of 12.5 V. If a voltage of 21 V is applied, permanent breakdown of the product will result. The VPP of 12.5 V is obtained for the PROM writer by setting it according to the Intel 27258 specifications. Writing/verification Programming of the built-in program ROM employs a high speed programming method. With this method, high speed writing is effected without voltage stress to the device or without damaging the reliability of the written data. For precautions for PROM writing procedure, refer to section 2, "Characteristics of ZTATTM Microcomputer's Built-in Programmable ROM and precautions for its Applications." 112 HD404629R Series Table 32 Selection of Mode Mode CE OE VPP O0–O7 Writing “Low” “High” VPP Data input Verification “High” “Low” VPP Data output Prohibition of programming “High” “High” VPP High impedance Table 33 PROM Writer Program Address ROM size Address 8k $0000~$3FFF 12k $0000~$5FFF 16k $0000~$7FFF 113 HD404629R Series Programmable ROM (HD4074629) The HD4074629 is a ZTAT TM microcomputer with built-in PROM that can be programmed in PROM mode. PROM Mode Pin Description Pin No. MCU Mode Pin No. Pin Name FP-100B TFP-100B FP-100A Pin Name I/O Pin Name I/O 24 26 D10 /STOPC I/O A9 I PROM Mode FP-100A Pin Name 1 3 AV CC 2 4 AN0 I 25 27 D11 /INT0 I/O VPP 3 5 AN1 I 26 28 R00/INT1 I/O GND 4 6 AN2 I 27 29 R01/INT2 I/O GND 5 7 AN3 I 28 30 R02/INT3 I/O 6 8 AV SS GND 29 31 R03/INT4 I/O 7 9 TEST I GND 30 32 R10/TOB I/O A5 I 8 10 OSC1 I VCC 31 33 R11/TOC I/O A6 I 9 11 OSC2 O 32 34 R12/TOD I/O A7 I 10 12 RESET I VCC 33 35 R13/EVNB I/O A8 I 11 13 X1 I GND 34 36 R20/EVND I/O A0 I 12 14 X2 O 35 37 R21/SCK I/O A10 I 13 15 GND 36 38 R22/SI I/O A11 I 14 16 D0 I/O CE I 37 39 R23/SO I/O A12 I 15 17 D1 I/O OE I 38 40 R30/SEG1 I/O A13 I 16 18 D2 I/O VCC 39 41 R31/SEG2 I/O A14 I 17 19 D3 I/O VCC 40 42 R32/SEG3 I/O O0 I/O 18 20 D4 I/O 41 43 R33/SEG4 I/O O1 I/O 19 21 D5 I/O 42 44 R40/SEG5 I/O O2 I/O 20 22 D6 I/O 43 45 R41/SEG6 I/O O3 I/O 21 23 D7 I/O 44 46 R42/SEG7 I/O O4 I/O 22 24 D8 I/O 45 47 R43/SEG8 I/O O5 I/O 23 25 D9 I/O 46 48 R50/SEG9 I/O O6 I/O 114 I/O MCU Mode FP-100B TFP-100B Notes on next page. I/O PROM Mode VCC GND HD404629R Series PROM Mode Pin Description (cont) Pin No. MCU Mode PROM Mode Pin No. Pin Name I/O FP-100B TFP-100B FP-100A Pin Name I/O R51/SEG10 I/O O7 I/O 74 76 SEG37 O 50 R52/SEG11 I/O O4 I/O 75 77 SEG38 O 49 51 R53/SEG12 I/O O3 I/O 76 78 SEG39 O 50 52 R60/SEG13 I/O O2 I/O 77 79 SEG40 O 51 53 R61/SEG14 I/O O1 I/O 78 80 SEG41 O 52 54 R62/SEG15 I/O O0 I/O 79 81 SEG42 O 53 55 R63/SEG16 I/O VCC 80 82 SEG43 O 54 56 R70/SEG17 I/O A1 I 81 83 SEG44 O 55 57 R71/SEG18 I/O A2 I 82 84 SEG45 O 56 58 R72/SEG19 I/O A3 I 83 85 SEG46 O 57 59 R73/SEG20 I/O A4 I 84 86 SEG47 O 58 60 SEG21 O 85 87 SEG48 O 59 61 SEG22 O 86 88 SEG49 O 60 62 SEG23 O 87 89 SEG50 O 61 63 SEG24 O 88 90 SEG51 O 62 64 SEG25 O 89 91 SEG52 O 63 65 SEG26 O 90 92 COM1 O 64 66 SEG27 O 91 93 COM2 O 65 67 SEG28 O 92 94 COM3 O 66 68 SEG29 O 93 95 COM4 O 67 69 SEG30 O 94 96 V1 68 70 SEG31 O 95 97 V2 69 71 SEG32 O 96 98 V3 70 72 SEG33 O 97 99 VCC 71 73 SEG34 O 98 100 TONEC O 72 74 SEG35 O 99 1 TONER O 73 75 SEG36 O 100 2 VTref FP-100B TFP-100B FP-100A Pin Name 47 49 48 I/O MCU Mode PROM Mode Pin Name I/O VCC Notes: 1. I/O: Input/output pin, I: Input pin, O: Output pin 2. Each of O0–O4 has two pins; before using, each pair must be connected together. 115 HD404629R Series PROM Mode Pin Functions VPP: Applies the programming voltage (12.5 V ± 0.3 V) to the built-in PROM. CE: Inputs a control signal to enable PROM programming and verification. OE : Inputs a data output control signal for verification. A0–A14: Act as address input pins of the built-in PROM. O0–O7: Act as data bus input pins of the built-in PROM. Each of O0–O4 has two pins; before using these pins, connect each pair together. M 0 , M1, RESET, TEST: Used to set PROM mode. The MCU is set to the PROM mode by pulling M0, M1, and TEST low, and RESET high. Other Pins (FP-100B/FP-100A): Connect pins 1/3 (AVCC), 8/10 (OSC1), 16/18 (D2), 17/19 (D3), 53/55 (R63/SEG16), and 97/99 (V CC ) to VCC, and pins 6/8 (AVSS) and 11/13 (X1) to GND. Leave other pins open. $0000 $0001 . . . $001F $0020 . . . $007F $0080 . . . 1 1 1 1 1 1 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Lower 5 bits Upper 5 bits $0000 Vector address $000F $0010 Zero-page subroutine (64 words) $003F $0040 Pattern (4,096 words) $0FFF $1000 $1FFF $2000 Program (16,384 words) JMPL instruction (jump to RESET, STOPC routine) JMPL instruction (jump to INT 0 routine) JMPL instruction (jump to INT 1 routine) JMPL instruction (jump to timer A routine) JMPL instruction (jump to timer B, INT2 routine) JMPL instruction (jump to timer C, INT3 routine) JMPL instruction (jump to timer D, INT4 routine) JMPL instruction (jump to A/D, serial routine) $3FFF $7FFF Upper three bits are not to be used (fill them with 111) Figure 102 Memory Map in PROM Mode 116 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F HD404629R Series Start Set programming/verification modes V PP = 12.5 ± 0.3 V, V CC = 6.0 ± 0.25 V Address = 0 n=0 n + 1→ n Yes No n < 25? Program t PW =1 ms ± 5% No Address + 1 → Address Verification OK? Yes Program t OPW = 3n ms Last address? No Yes Set read mode VCC = 5.0 ± 0.5 V, V PP = V CC ± 0.6 V No All addresses read? Yes Fail End Figure 103 Flowchart of High-Speed Programming 117 HD404629R Series Programming Electrical Characteristics DC Characteristics (VCC = 6.0 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, T a = 25°C ± 5°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Condition Input high voltage level VIH O0–O7, A0–A14, OE, CE 2.2 — VCC + 0.3 V Input low voltage level VIL O0–O7, A0–A14, OE, CE –0.3 — 0.8 V Output high voltage level VOH O0–O7 2.4 — — V I OH = –200 µA Output low voltage level VOL O0–O7 — — 0.4 V I OL = 1.6 mA Input leakage current I IL O0–O7, A0–A14, OE, CE — — 2 µA Vin = 5.25 V/0.5 V VCC current I CC — — 30 mA VPP current I PP — — 40 mA AC Characteristics (VCC = 6.0 V ± 0.25 V, V PP = 12.5 V ± 0.3 V, Ta = 25°C ± 5°C, unless otherwise specified) Item Symbol Min Typ Max Unit Test Condition Address setup time t AS 2 — — µs See figure 108 OE setup time t OES 2 — — µs Data setup time t DS 2 — — µs Address hold time t AH 0 — — µs Data hold time t DH 2 — — µs Data output disable time t DF — — 130 ns VPP setup time t VPS 2 — — µs Program pulse width t PW 0.95 1.0 1.05 ms CE pulse width during overprogramming t OPW 2.85 — 78.75 ms VCC setup time t VCS 2 — — µs Data output delay time t OE 0 — 500 ns 118 HD404629R Series Input pulse level: 0.8 V to 2.2 V Input rise/fall time: ≤ 20 ns Input timing reference levels: 1.0 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Programming Verification Address t AH t AS Data Data in Stable t DS V PP V CC V PP GND V CC GND Data out Valid t DH t DF t VPS t VCS CE t PW OE t OES t OE t OPW Figure 104 PROM Programming/Verification Timing 119 HD404629R Series Notes on PROM Programming Principles of Programming/Erasure: A memory cell in a ZTAT™ microcomputer is the same as an EPROM cell; it is programmed by applying a high voltage between its control gate and drain to inject hot electrons into its floating gate. These electrons are stable, surrounded by an energy barrier formed by an SiO 2 film. The change in threshold voltage of a memory cell with a charged floating gate makes the corresponding bit appear as 0; a cell whose floating gate is not charged appears as a 1 bit (figure 105). The charge in a memory cell may decrease with time. This decrease is usually due to one of the following causes: • • • Ultraviolet light excites electrons, allowing them to escape. This effect is the basis of the erasure principle. Heat excites trapped electrons, allowing them to escape. High voltages between the control gate and drain may erase electrons. If the oxide film covering a floating gate is defective, the electron erasure rate will be greater. However, electron erasure does not often occur because defective devices are detected and removed at the testing stage. Control gate Control gate SiO2 SiO2 Floating gate Floating gate Drain Source N+ N+ Write (0) Drain Source N+ N+ Erasure (1) Figure 105 Cross-Sections of a PROM Cell PROM Programming: PROM memory cells must be programmed under specific voltage and timing conditions. The higher the programming voltage VPP and the longer the programming pulse t PW is applied, the more electrons are injected into the floating gates. However, if V PP exceeds specifications, the pn junctions may be permanently damaged. Pay particular attention to overshooting in the PROM programmer. In addition, note that negative voltage noise will produce a parasitic transistor effect that may reduce breakdown voltages. The ZTAT™ microcomputer is electrically connected to the PROM programmer by a socket adapter. Therefore, note the following points: • • Check that the socket adapter is firmly mounted on the PROM programmer. Do not touch the socket adapter or the LSI during the programming. Touching them may affect the quality of the contacts, which will cause programming errors. 120 HD404629R Series PROM Reliability after Programming: In general, semiconductor devices retain their reliability, provided that some initial defects can be excluded. These initial defects can be detected and rejected by screening. Baking devices under high-temperature conditions is one method of screening that can rapidly eliminate data-hold defects in memory cells. (Refer to the previous Principles of Programming/Erasure section.) ZTAT™ microcomputer devices are extremely reliable because they have been subjected to such a screening method during the wafer fabrication process, but Hitachi recommends that each device be exposed to 150°C at one atmosphere for at least 48 hours after it is programmed, to ensure its best performance. The recommended screening procedure is shown in figure 106. Note: If programming errors occur continuously during PROM programming, suspend programming and check for problems in the PROM programmer or socket adapter. If programming verification indicates errors in programming or after high-temperature exposure, please inform Hitachi. Programming, verification Exposure to high temperature, without power 150°C ± 10°C, 48 h +8 h * –0 h Program read check VCC = 4.5 V or 5.5 V Note: * Exposure time is measured from when the temperature in the heater reaches 150°C. Figure 106 Recommended Screening Procedure 121 HD404629R Series Addressing Modes RAM Addressing Modes The MCU has three RAM addressing modes, as shown in figure 107 and described below. Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used as a RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions. W register W1 W0 RAM address X register X3 X2 X1 Y register X0 Y3 Y2 Y1 Y0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Register Direct Addressing 1st word of Instruction 2nd word of Instruction Opcode d RAM address 9 d8 d7 d6 d5 d4 d3 d2 d1 d0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Direct Addressing Instruction Opcode 0 RAM address 0 0 1 m3 m2 0 m0 0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Memory Register Addressing Figure 107 RAM Addressing Modes 122 m1 HD404629R Series ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes, as shown in figure 108 and described below. Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits (PC 13–PC0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program can branch to any address in the current page by executing the BR instruction. This instruction replaces the eight low-order bits of the program counter (PC7–PC0) with eight-bit immediate data. If the BR instruction is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next physical page, as shown in figure 105. This means that the execution of the BR instruction on a page boundary will make the program branch to the next page. Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages. Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000– $003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (PC5–PC0), and 0s are placed in the eight highorder bits (PC13–PC6). Table Data Addressing Mode: A program can branch to an address determined by the contents of four-bit immediate data, the accumulator, and the B register by executing the TBR instruction. P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction as shown in figure 109. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and R2 port output registers at the same time. The P instruction has no effect on the program counter. 123 HD404629R Series 1st word of instruction [JMPL] [BRL] [CALL] Opcode p3 Program counter 2nd word of instruction p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Direct Addressing Instruction [BR] Program counter Opcode b7 b6 b5 b4 b3 b2 b1 b0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Current Page Addressing Instruction [CAL] 0 Program counter 0 0 0 d5 Opcode 0 0 0 d4 d3 d2 d1 d0 0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Zero Page Addressing Instruction [TBR] Opcode p3 p2 p1 p0 B register B3 0 Program counter B2 B1 B0 A3 A2 A1 A0 0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Table Data Addressing Figure 108 ROM Addressing Modes 124 Accumulator HD404629R Series Instruction [P] Opcode p3 p2 p1 p0 B register B3 0 B2 B1 Accumulator B0 A3 A2 A1 A0 0 Referenced ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Address Designation ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Accumulator, B register ROM data B3 B2 B1 B0 A3 A 2 A1 A 0 If RO 8 = 1 RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Output registers R1, R2 R23 R22 R21 R20 R13 R12 R11 R10 If RO 9 = 1 Pattern Output Figure 109 P Instruction 125 HD404629R Series 256 (n – 1) + 255 BR AAA 256n AAA BBB 256n + 254 256n + 255 256 (n + 1) NOP BR BR BBB AAA NOP Figure 110 Branching when the Branch Destination is on a Page Boundary 126 HD404629R Series Instruction Set The MCU has 101 instructions, classified into the following 10 groups: • • • • • • • • • • Immediate instructions Register-to-register instructions RAM addressing instructions RAM register instructions Arithmetic instructions Compare instructions RAM bit manipulation instructions ROM addressing instructions Input/output instructions Control instructions The functions of these instructions are listed in tables 34 to 43, and an opcode map is shown in table 44. Table 34 Immediate Instructions Mnemonic Operation Code Load A from immediate LAI i 1 0 0 0 1 1 i3 i2 i1 i0 i→A 1/1 Load B from immediate LBI i 1 0 0 0 0 0 i3 i2 i1 i0 i→B 1/1 Load memory from immediate LMID i,d 0 1 1 0 1 0 i3 i2 i1 i0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 i→M 2/2 1 i → M, Y+1→Y Load memory LMIIY i from immediate, increment Y 0 1 0 0 Function Words/ Status Cycles Operation 1 i3 i2 i1 i0 NZ 1/1 127 HD404629R Series Table 35 Register-Register Instructions Function Words/ Status Cycles Operation Mnemonic Operation Code Load A from B LAB 0 0 0 1 0 0 1 0 0 0 B→A 1/1 Load B from A LBA 0 0 1 1 0 0 1 0 0 0 A→B 1/1 Load A from W LAW* 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W→A 2/2* Load A from Y LAY 0 0 1 0 1 0 1 1 1 1 Y→A 1/1 Load A from SPX LASPX 0 0 0 1 1 0 1 0 0 0 SPX → A 1/1 Load A from SPY LASPY 0 0 0 1 0 1 1 0 0 0 SPY → A 1/1 Load A from MR LAMR m 1 0 0 1 1 1 m3 m2 m1 m0 MR (m) → A 1/1 Exchange MR and A XMRA m 1 0 1 1 1 1 m3 m2 m1 m0 MR (m) ↔ A 1/1 Note: * Although the LAW and LWA instructions require an operand ($000) in the second word, the assembler generates it automatically and thus there is no need to specify it explicitly. 128 HD404629R Series Table 36 RAM Address Instructions Function Words/ Status Cycles Operation Mnemonic Operation Code Load W from immediate LWI i 0 0 1 1 1 1 0 0 i1 i0 i→W 1/1 Load X from immediate LXI i 1 0 0 0 1 0 i3 i2 i1 i0 i→X 1/1 Load Y from immediate LYI i 1 0 0 0 0 1 i3 i2 i1 i0 i→Y 1/1 Load W from A LWA 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 A→W 2/2* Load X from A LXA 0 0 1 1 1 0 1 0 0 0 A→X 1/1 Load Y from A LYA 0 0 1 1 0 1 1 0 0 0 A→Y 1/1 Increment Y IY 0 0 0 1 0 1 1 1 0 0 Y+1→Y NZ 1/1 Decrement Y DY 0 0 1 1 0 1 1 1 1 1 Y–1→Y NB 1/1 Add A to Y AYY 0 0 0 1 0 1 0 1 0 0 Y+A→Y OVF 1/1 Subtract A from Y SYY 0 0 1 1 0 1 0 1 0 0 Y–A→Y NB 1/1 Exchange X and SPX XSPX 0 0 0 0 0 0 0 0 0 1 X ↔ SPX 1/1 Exchange Y and SPY XSPY 0 0 0 0 0 0 0 0 1 0 Y ↔ SPY 1/1 Exchange X and SPX, Y and SPY XSPXY 0 0 0 0 0 0 0 0 1 1 X ↔ SPX, Y ↔ SPY 1/1 Note: * Although the LAW and LWA instructions require an operand ($000) in the second word, the assembler generates it automatically and thus there is no need to specify it explicitly. 129 HD404629R Series Table 37 RAM Register Instructions Mnemonic Operation Code Load A from memory LAM 0 0 1 0 0 1 0 0 0 0 M→A LAMX 0 0 1 0 0 1 0 0 0 1 M → A, X ↔ SPX LAMY 0 0 1 0 0 1 0 0 1 0 M → A, Y ↔ SPY LAMXY 0 0 1 0 0 1 0 0 1 1 M → A, X ↔ SPX, Y ↔ SPY Load A from memory LAMD d 0 1 1 0 0 1 0 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M→A 2/2 Load B from memory LBM 0 0 0 1 0 0 0 0 0 0 M→B 1/1 LBMX 0 0 0 1 0 0 0 0 0 1 M → B, X ↔ SPX LBMY 0 0 0 1 0 0 0 0 1 0 M → B, Y ↔ SPY LBMXY 0 0 0 1 0 0 0 0 1 1 M → B, X ↔ SPX, Y ↔ SPY LMA 0 0 1 0 0 1 0 1 0 0 A→M LMAX 0 0 1 0 0 1 0 1 0 1 A → M, X ↔ SPX LMAY 0 0 1 0 0 1 0 1 1 0 A → M, Y ↔ SPY LMAXY 0 0 1 0 0 1 0 1 1 1 A → M, X ↔ SPX, Y ↔ SPY LMAD d 0 1 1 0 0 1 0 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Load memory from A Load memory from A 130 Function Words/ Status Cycles Operation A→M 1/1 1/1 2/2 HD404629R Series Table 37 RAM Register Instructions (cont) Mnemonic Operation Code Load memory from A, increment Y LMAIY 0 0 0 1 0 1 0 0 0 0 A → M, Y+1→Y LMAIYX 0 0 0 1 0 1 0 0 0 1 A → M, Y + 1 → Y, X ↔ SPX LMADY 0 0 1 1 0 1 0 0 0 0 A → M, Y–1→Y LMADYX 0 0 1 1 0 1 0 0 0 1 A → M, Y – 1 → Y, X ↔ SPX XMA 0 0 1 0 0 0 0 0 0 0 M↔A XMAX 0 0 1 0 0 0 0 0 0 1 M ↔ A, X ↔ SPX XMAY 0 0 1 0 0 0 0 0 1 0 M ↔ A, Y ↔ SPY XMAXY 0 0 1 0 0 0 0 0 1 1 M ↔ A, X ↔ SPX, Y ↔ SPY Exchange memory and A XMAD d 0 1 1 0 0 0 0 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M→A 2/2 Exchange memory and B XMB 0 0 1 1 0 0 0 0 0 0 M↔B 1/1 XMBX 0 0 1 1 0 0 0 0 0 1 M ↔ B, X ↔ SPX XMBY 0 0 1 1 0 0 0 0 1 0 M ↔ B, Y ↔ SPY XMBXY 0 0 1 1 0 0 0 0 1 1 M ↔ B, X ↔ SPX, Y ↔ SPY Load memory from A, decrement Y Exchange memory and A Function Words/ Status Cycles Operation NZ 1/1 NB 1/1 1/1 131 HD404629R Series Table 38 Arithmetic Instructions Operation Mnemonic Operation Code Function Status Words/ Cycles Add immediate to AI i A 1 0 1 0 0 0 i3 i2 i1 i0 A+i→A OVF 1/1 Increment B IB 0 0 0 1 0 0 1 1 0 0 B+1→B NZ 1/1 Decrement B DB 0 0 1 1 0 0 1 1 1 1 B–1→B NB 1/1 Decimal DAA adjust for addition 0 0 1 0 1 0 0 1 1 0 1/1 Decimal adjust for subtraction DAS 0 0 1 0 1 0 1 0 1 0 1/1 Negate A NEGA 0 0 0 1 1 0 0 0 0 0 A+1→A 1/1 Complement B COMB 0 1 0 1 0 0 0 0 0 0 B→B 1/1 Rotate right A with carry ROTR 0 0 1 0 1 0 0 0 0 0 1/1 Rotate left A with carry ROTL 0 0 1 0 1 0 0 0 0 1 1/1 Set carry SEC 0 0 1 1 1 0 1 1 1 1 1 → CA 1/1 Reset carry REC 0 0 1 1 1 0 1 1 0 0 0 → CA 1/1 Test carry TC 0 0 0 1 1 0 1 1 1 1 Add A to memory AM 0 0 0 0 0 0 1 0 0 0 Add A to memory AMD d CA 1/1 M+A→A OVF 1/1 0 1 0 0 0 0 1 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M+A→A OVF 2/2 Add A to memory AMC with carry 0 M + A + CA → A OVF OVF → CA 1/1 Add A to memory AMCD d with carry 0 1 0 0 0 1 1 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M + A + CA → A OVF OVF → CA 2/2 Subtract A from memory with carry SMC 0 M – A – CA → A NB NB → CA 1/1 Subtract A from memory with carry SMCD d 0 1 1 0 0 1 1 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M – A – CA → A NB NB → CA 2/2 OR A and B OR 0 A∪B→A 1/1 132 0 0 1 0 1 0 0 0 1 0 0 0 1 1 0 1 1 0 0 0 1 0 0 0 0 0 0 HD404629R Series Table 38 Arithmetic Instructions (cont) Function Words/ Status Cycles A ∩M→A NZ 1/1 0 1 1 0 0 1 1 1 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 A ∩M→A NZ 2/2 ORM 0 A ∪M→A NZ 1/1 OR memory with A ORMD d 0 1 0 0 0 0 1 1 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 A ∪M→A NZ 2/2 EOR memory with A EORM 0 A ⊕ M →A NZ 1/1 EOR memory with A EORMD d 0 1 0 0 0 1 1 1 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 A ⊕ M →A NZ 2/2 Operation Mnemonic Operation Code AND memory with A ANM 0 AND memory with A ANMD d OR memory with A 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 133 HD404629R Series Table 39 Compare Instructions Function Words/ Status Cycles i≠M NZ 1/1 0 1 0 0 1 0 i3 i2 i1 i0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 i≠M NZ 2/2 ANEM 0 A≠M NZ 1/1 A not equal to memory ANEMD d 0 1 0 0 0 0 0 1 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 A≠M NZ 2/2 B not equal to memory BNEM 0 0 0 1 0 0 0 1 0 0 B≠M NZ 1/1 Y not equal to immediate YNEI i 0 0 0 1 1 1 i3 i2 i1 i0 Y≠i NZ 1/1 Immediate less or equal to memory ILEM i 0 0 0 0 1 1 i3 i2 i1 i0 i≤M NB 1/1 Immediate less or equal to memory ILEMD i, d 0 1 0 0 1 1 i3 i2 i1 i0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 i≤M NB 2/2 A less or equal to memory ALEM 0 A≤M NB 1/1 A less or equal to memory ALEMD d 0 1 0 0 0 1 0 1 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 A≤M NB 2/2 B less or equal to memory BLEM 0 0 1 1 0 0 0 1 0 0 B≤M NB 1/1 A less or equal to immediate ALEI i 1 0 1 0 1 1 i3 i2 i1 i0 A≤i NB 1/1 Operation Mnemonic Operation Code Immediate not equal to memory INEM i 0 Immediate not equal to memory INEMD i, d A not equal to memory 134 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 i3 0 0 i2 1 1 i1 0 0 i0 0 0 HD404629R Series Table 40 RAM Bit Manipulation Instructions Mnemonic Operation Code Set memory bit SEM n 0 n1 n0 i → M (n) 1/1 Set memory bit SEMD n,d 0 1 1 0 0 0 0 1 n1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 i → M (n) 2/2 Reset memory bit REM n 0 n1 n0 0 → M (n) 1/1 Reset memory bit REMD n,d 0 1 1 0 0 0 1 0 n1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 → M (n) 2/2 Test memory bit TM n 0 n1 n0 M (n) 1/1 Test memory bit TM n,d 0 1 1 0 0 0 1 1 n1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M (n) 2/2 0 0 0 1 1 1 0 0 0 0 0 0 Function 0 0 0 0 1 1 1 0 1 Status Words/ Cycles Operation Table 41 ROM Addressing Instructions Mnemonic Operation Code Branch on status 1 BR b 1 b7 b6 b5 b4 b3 b2 b1 b0 1 1/1 Long branch on status 1 BRL u 0 1 0 1 1 1 p3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 2/2 Long jump unconditionally JMPL u 0 1 0 1 0 1 p3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Subroutine jump on status 1 CAL a 0 a5 a4 a3 a2 a1 a0 1 1/2 Long subroutine jump on status 1 CALL u 0 1 0 1 1 0 p3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 2/2 Table branch TBR p 0 0 1 0 1 1 p3 p2 p1 p0 1 1/1 Return from subroutine RTN 0 0 0 0 0 1 0 0 0 0 Return from interrupt RTNI 0 0 0 0 0 1 0 0 0 1 1 1 1 1 Function Words/ Status Cycles Operation 2/2 1/3 1 → IE, ST carry restored 1/3 135 HD404629R Series Table 42 Input/Output Instructions Operation Mnemonic Operation Code Function Set discrete I/O latch SED 0 0 1 1 1 0 0 Set discrete I/O latch direct SEDD m 1 0 1 1 1 0 Reset discrete I/O latch RED 0 0 0 1 1 Reset discrete I/O latch direct REDD m 1 0 0 1 Test discrete I/O latch TD 0 0 1 Test discrete I/O latch direct TDD m 1 0 Load A from R-port register LAR m 1 Load B from R-port register LBR m Load R-port register from A Words/ Status Cycles 1 → D (Y) 1/1 m3 m2 m1 m0 1 → D (m) 1/1 0 0 0 → D (Y) 1/1 1 0 m3 m2 m1 m0 0 → D (m) 1/1 1 1 0 0 1 0 1 0 m3 m2 m1 m0 0 0 1 0 1 m3 m2 m1 m0 R (m) → A 1/1 1 0 0 1 0 0 m3 m2 m1 m0 R (m) → B 1/1 LRA m 1 0 1 1 0 1 m3 m2 m1 m0 A → R (m) 1/1 Load R-port register from B LRB m 1 0 1 1 0 0 m3 m2 m1 m0 B → R (m) 1/1 Pattern generation Pp 0 1 1 0 1 1 p3 p2 p1 p0 136 1 1 0 0 0 0 0 0 0 D (Y) 1/1 D (m) 1/1 1/2 HD404629R Series Table 40 Control Instructions Function Words/ Status Cycles Operation Mnemonic Operation Code No operation NOP 0 0 0 0 0 0 0 0 0 0 1/1 Start serial STS 0 1 0 1 0 0 1 0 0 0 1/1 Standby mode/Watch mode* SBY 0 1 0 1 0 0 1 1 0 0 1/1 Stop mode/ Watch mode STOP 0 1 0 1 0 0 1 1 0 1 1/1 Note: * Only on return from subactive mode. 137 HD404629R Series Table 44 Opcode Map 0 R8 L 0 1 2 3 4 R9 H 0 NOP XSPX XSPY XSPXY ANEM 1 RTN RTNI 5 6 ALEM 2 0 LBM(XY) LMAIY(X) NEGA BNEM 9 C ORM AMC EORM IB AYY LASPY IY RED LASPX XMA(XY) SEM n(2) LAM(XY) LMA(XY) ROTR ROTL D E F TC REM n(2) SMC DAA B TM n(2) ANM DAS LAY TBR p(4) C BLEM LBA DB D LMADY(X) SYY LYA DY E TD SED LXA F XMB(XY) REC SEC LWI i(2) 0 LBI i(4) 1 LYI i(4) 2 LXI i(4) 3 LAI i(4) 4 LBR m(4) 5 LAR m(4) 6 REDD m(4) 7 LAMR m(4) 8 AI i(4) 9 LMIIY i(4) A TDD m(4) B ALEI i(4) C D LRB m(4) E SEDD m(4) F XMRA m(4) LRA m(4) 1-word/2-cycle instruction 138 B YNEI i(4) 8 1 A LAB 7 A 9 ILEM i(4) 4 6 8 AM INEM i(4) 3 5 7 1-word/3-cycle instruction RAM direct address instruction (2-word/2-cycle) 2-word/2-cycle instruction HD404629R Series Table 44 Opcode Map (cont) 1 R8 L 0 1 2 3 4 R9 H 0 LAW ANEMD 1 LWA ALEMD 6 7 8 STS 5 JMPL p(4) 6 CALL p(4) 7 BRL p(4) 8 XMAD LAMD SEMD n(2) LMAD C EORMD ILEMD i(4) 9 B AMCD 2 OR A ORMD 3 COMB 9 AMD INEMD i(4) 4 0 5 SBY REMD n(2) SMCD A LMID i(4) B P p(4) D E F STOP TMD n(2) ANMD C D CAL a(6) E F 0 1 2 3 4 5 6 7 1 BR b(8) 8 9 A B C D E F 1-word/2-cycle instruction 1-word/3-cycle instruction RAM direct address instruction (2-word/2-cycle) 2-word/2-cycle instruction 139 HD404629R Series Absolute Maximum Ratings Item Symbol Value Unit Supply voltage VCC –0.3 to +7.0 V Programming voltage VPP –0.3 to +14.0 V Pin voltage VT –0.3 to (VCC + 0.3) V Total permissible input current ∑Io 100 mA 2 Total permissible output current –∑Io 50 mA 3 Maximum input current Io 4 mA 4, 5 30 mA 4, 6 7, 8 Maximum output current –I o 4 mA Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +125 °C Notes 1 Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. Applies to D 11 (VPP) of the HD4074629. 2. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to ground. 3. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 4. The maximum input current is the maximum current flowing from each I/O pin to ground. 5. Applies to R0–R7. 6. Applies to D 0–D 9. 7. The maximum output current is the maximum current flowing out from V CC to each I/O pin. 8. Applies to D 0–D 9 and R0–R7. 140 HD404629R Series Electrical Characteristics DC Characteristics (HD404628R, HD4046212R, HD404629R: VCC = 2.7 to 6.0 V, GND = 0 V, T a = –20°C to +75°C; HD4074629: VC C = 2.7 to 5.5 V, GND = 0 V, T a = –20°C to +75°C, unless otherwise specified) Item Input high voltage Input low voltage Symbol VIH VIL Pin(s) Min 0.9VCC Typ — Max VCC + 0.3 Unit V Test Condition — VCC – 0.3 — VCC + 0.3 V RESET, SCK, SI, INT0, INT1, INT2, INT3, INT4, STOPC, EVNB, EVND OSC1 –0.3 — 0.1VCC V External clock operation — –0.3 — 0.3 V RESET, SCK, SI, INT0, INT1 INT2, INT3, INT4, STOPC, EVNB, EVND OSC1 Notes Output high voltage VOH SCK, SO, TOB, TOC, TOD VCC – 1.0 — — V External clock operation –I OH = 0.5 mA Output low voltage VOL SCK, SO, TOB, TOC, TOD — — 0.4 V IOL = 0.4 mA I/O leakage current II L — — 1.0 µA Vin = 0 V to V CC 1 Current dissipation in active mode ICC1 RESET, SCK, SI, INT0, INT1, INT2, INT3, INT4, STOPC, EVNB, EVND, OSC1, TOB, TOC, TOD, SO VCC (HD404628R, HD4046212R, HD404629R) VCC (HD4074629) VCC (HD404628R, HD4046212R, HD404629R) VCC (HD4074629) VCC (HD404628R, HD4046212R, HD404629R) VCC (HD4074629) VCC — 2.5 5.0 mA VCC = 5.0 V, fOSC = 4 MHz 2, 4 — 5 9 — 0.3 0.9 mA VCC = 3.0 V, fOSC = 800 kHz 2, 4 — 0.6 1.8 — 1.0 2.0 mA VCC = 5.0 V, fOSC = 4 MHz, LCD on 3, 4 — 1.2 3 — 0.2 0.7 mA VCC = 3.0 V, fOSC = 800 kHz, LCD on 3, 4 ICC2 Current dissipation in standby mode ISBY1 ISBY2 Notes on next page. 141 HD404629R Series DC Characteristics (HD404628R, HD4046212R, HD404629R: VCC = 2.7 to 6.0 V, GND = 0 V, T a = –20°C to +75°C; HD4074629: VC C = 2.7 to 5.5 V, GND = 0 V, T a = –20°C to +75°C, unless otherwise specified) (cont) Item Current dissipation in subactive mode Current dissipation in watch mode Current dissipation in stop mode Symbol ISUB IWTC1 IWTC2 ISTOP Pin(s) VCC VCC (HD404628R, HD4046212R, HD404629R) VCC (HD4074629) VCC (HD404628R, HD4046212R, HD404629R) VCC (HD4074629) VCC (HD404628R, HD4046212R, HD404629R) VCC (HD4074629) VCC Min — Typ 25 Max 70 Unit µA Test Condition HD404628R, HD4046212R, HD404629R: VCC = 3.0 V, LCD on 32-kHz oscillator HD4074629: VCC = 3.0 V, LCD on 32-kHz oscillator VCC = 3.0 V, LCD on 32-kHz oscillator Notes 4 — 70 150 µA — 15 40 µA — 18 40 — 5 10 µA VCC = 3.0 V, LCD off 32-kHz oscillator 4 — 8 15 — 0.5 5 µA VCC = 3.0 V, No 32-kHz oscillator 4 — 1 10 4 4 Stop mode VSTOP 2 — — V No 32-kHz 5 retaining voltage oscillator Notes: 1. Output buffer current is excluded. 2. ICC1 and ICC2 are the source currents when no I/O current is flowing while the MCU is in reset state. Test conditions: MCU: Reset Pins: RESET at VCC (VCC – 0.3 V to VCC) TEST at VCC (VCC – 0.3 V to VCC) 3. ISBY1 and ISBY2 are the source currents when no I/O current is flowing while the MCU timer is operating. Test conditions: MCU: I/O reset Serial interface stopped DTMF stopped Standby mode Pins: RESET at GND (0 V to 0.3 V) TEST at VCC (VCC – 0.3 V to VCC) 4. These are the source currents when no I/O current is flowing. Test conditions: Pins: RESET at GND (0 V to 0.3 V) TEST at VCC (VCC – 0.3 V to VCC) D11 (VPP ) at VCC (VCC – 0.3 V to VCC) for the HD4074629 5. The required voltage for RAM data retention. 142 HD404629R Series I/O Characteristics for Standard Pins (HD404628R, HD4046212R, HD404629R: V CC = 2.7 to 6.0 V, GND = 0 V, Ta = –20°C to +75°C; HD4074629: V CC = 2.7 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Condition Input high voltage VIH D10 , D11 , R0–R7 0.7VCC — VCC + 0.3 V — Input low voltage VIL D10 , D11 , R0–R7 –0.3 — 0.3VCC V — Output high voltage VOH R0–R7 VCC – 1.0 — — V –I OH = 0.5 mA Output low voltage VOL R0–R7 — — 0.4 V IOL = 0.4 mA I/O leakage II L D10 , R0–R7 — — 1 µA Vin = 0 V to V CC 1 D11 — — 1 µA HD404628R, HD4046212R, HD404629R: Vin = 0 V to V CC 1 — — 1 µA HD4074629: Vin = VCC – 0.3 V to VCC 1 — — 20 µA HD4074629: Vin = 0 V to 0.3 V 1 5 30 90 µA VCC = 3.0 V, Vin = 0 V current Pull-up MOS current –I PU R0–R7 Notes Note: 1. Output buffer current is excluded. 143 HD404629R Series I/O Characteristics for High-Current Pins (HD404628R, HD4046212R, HD404629R: V CC = 2.7 to 6.0 V, GND = 0 V, Ta = –20°C to +75°C; HD4074629: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Condition Input high voltage VIH D0–D9 0.7VCC — VCC + 0.3 V — Input low voltage VIL D0–D9 –0.3 — 0.3VCC V — Output high voltage VOH D0–D9 VCC – 1.0 — — V –I OH = 0.5 mA Output low VOL D0–D9 — — 0.4 V IOL = 0.4 mA — — 2.0 V IOL = 15 mA, VCC = 4.5 V to 6.0 V 1 2 voltage I/O leakage current II L D0–D9 — — 1 µA Vin = 0 V to V CC Pull-up MOS current –I PU D0–D9 5 30 90 µA VCC = 3 V, Vin = 0 V Note: Notes 1. The test condition of HD4074629 is VCC = 4.5 V to 5.5 V. 2. Output buffer current is excluded. LCD Circuit Characteristics (HD404628R, HD4046212R, HD404629R: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = –20°C to +75°C; HD4074629: V CC = 2.7 to 5.5 V, GND = 0 V, T a = –20°C to +75°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes Segment driver voltage drop VDS SEG1–SEG52 — — 0.6 V IPD = 3 µA 1 Common driver voltage drop VDC COM1–COM4 — — 0.3 V IPD = 3 µA 1 LCD power supply division resistance RW — (HD404628R, HD4046212R, HD404629R) 50 300 900 kΩ Between V 1 and GND — (HD4074629) 100 300 900 V1 2.7 — VCC LCD voltage VLCD — V — 2 Notes: 1. VDS and VDC are the voltage drops from power supply pins V1, V2, V3, and GND to each segment pin and each common pin, respectively. 2. When VLCD is supplied from an external source, the following relations must be retained: VCC ≥ V1 ≥ V2 ≥ V3 ≥ GND 144 HD404629R Series DTMF Characteristics (HD404628R, HD4046212R, HD404629R: V CC = 2.7 to 6.0 V, GND = 0 V, T a = –20°C to +75°C; HD4074629: V CC = 2.7 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin Min Typ Max Unit Test Condition Notes Tone output voltage (1) VOR TONER 500 660 — mVrms VTref – GND = 2.0 V, R L = 100 kΩ 1 Tone output voltage (2) VOC TONEC 520 690 — mVrms VTref – GND = 2.0 V, R L = 100 kΩ 1 Tone output distortion %DIS — — 3 7 % Short circuit between TONER and TONEC, R L = 100 kΩ 2 Tone output ratio dBCR — — 2.5 — dB Short circuit between TONER and TONEC, R L = 100 kΩ 2 Notes: 1. See figure 106. 2. See figure 107. 3. 400 kHz, 800 kHz, 2 MHz, or 4 MHz can be used as the operating frequency (fOSC). 145 HD404629R Series A/D Converter Characteristics (HD404628R, HD4046212R, HD404629R: V CC = 2.7 to 6.0 V, GND = 0 V, Ta = –20°C to +75°C; HD4074629: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Condition Analog power voltage AV CC AV CC VCC – 0.3 VCC VCC + 0.3 V AV CC ≥ 2.7 V Analog input voltage AV in AN0–AN 3 AV SS — AV CC V — Current between AV CC and AVSS IAD — (HD404628R, HD4046212R, HD404629R) — — 250 µA VCC = AVCC = 5.0 V — (HD4074629) — 50 150 Analog input capacitance CAin AN0–AN 3 — 15 — pF — Resolution — — 8 8 8 Bit — Number of inputs — — 0 — 4 Channel — Absolute accuracy — — — — ± 2.0 LSB Ta = 25°C, VCC = 4.5–5.5 V Conversion time — — 34 — 67 tcyc — Input impedance — AN0–AN 3 1 — — MΩ fOSC = 1 MHz, Vin = 0.0 V 146 Notes HD404629R Series AC Characteristics (HD404628R, HD4046212R, HD404629R: VCC = 2.7 to 6.0 V, GND = 0 V, T a = –20°C to +75°C; HD4074629: VC C = 2.7 to 5.5 V, GND = 0 V, T a = –20°C to +75°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes Clock oscillation fOSC OSC1, OSC2 — 400 — kHz 1/4 division 1 frequency Instruction cycle tcyc — 800 — kHz 1/4 division 1 — 2 — MHz 1/4 division 1 — 4 — MHz 1/4 division; HD404628, HD4046212, HD404629: VCC = 3.0 to 6.0 V 1 X1, X2 — 32.768 — kHz — — — 10 — µs fOSC = 400 kHz — 5 — µs fOSC = 800 kHz — 2 — µs fOSC = 2 MHz — 1 — µs fOSC = 4 MHz; HD404628, HD4046212, HD404629: VCC = 3.0 to 6.0 V — 244.14 — µs 32-kHz oscillator, 1/8 division — 122.07 — µs 32-kHz oscillator, 1/4 division OSC1, OSC2 — — 7.5 ms Ceramic oscillator 2 OSC1, OSC2 (HD404628R, HD4046212R, HD404629R) — — 30 ms Crystal oscillator VCC = 3.0 to 6.0 V 2 X1, X2 — — 3 s Ta = –10°C to +60°C 3 OSC1 1100 — — ns fOSC = 400 kHz 4 550 — — ns fOSC = 800 kHz 4 215 — — ns fOSC = 2 MHz 4 105 — — ns fOSC = 4 MHz 4 1100 — — ns fOSC = 400 kHz 4 550 — — ns fOSC = 800 kHz 4 215 — — ns fOSC = 2 MHz 4 105 — — ns fOSC = 4 MHz 4 — — 150 ns fOSC = 400 kHz 4 — — 75 ns fOSC = 800 kHz 4 — — 35 ns fOSC = 2 MHz 4 — — 20 ns fOSC = 4 MHz 4 time tsubcyc Oscillation tRC stabilization time External clock tCPH — high width External clock tCPL OSC1 low width External clock tCPr rise time OSC1 Notes on next page. 147 HD404629R Series AC Characteristics (HD404628R, HD4046212R, HD404629R: VCC = 2.7 to 6.0 V, GND = 0 V, T a = –20°C to +75°C; HD4074629: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) (cont) Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes External clock tCPf OSC1 — — 150 ns fOSC = 400 kHz 4 — — 75 ns fOSC = 800 kHz 4 — — 35 ns fOSC = 2 MHz 4 — — 20 ns fOSC = 4 MHz 4 fall time INT0–INT4, EVNB , EVND high widths tI H INT0–INT4, EVNB, EVND 2 — — tcyc / tsubcyc — 5 INT0–INT4, EVNB , EVND low widths tI L INT0–INT4, EVNB, EVND 2 — — tcyc / tsubcyc — 5 RESET high width tRSTH RESET 2 — — tcyc — 6 STOPC low width tSTPL STOPC 1 — — tRC — 7 RESET fall time tRSTf RESET — — 20 ms — 6 STOPC rise time tSTPr STOPC — — 20 ms — 7 Input capacitance Cin All pins except D 11 — — 15 pF f = 1 MHz Vin = 0 V, D11 — — 15 pF HD404628R, HD4046212R, HD404629R: f = 1 MHz, Vin = 0 V — — 180 pF HD4074629: f = 1 MHz, Vin = 0 V Notes: 1. Be sure to set system clock selection register (SSR) bits SSR1 and SSR0 to match the system clock oscillator frequency. 2. Applies to voltage ranges V CC = 3.5 to 5.5 V for the HD4074629. 3. There are three oscillator stabilization times. (1) At power on, the time between the point where VCC reaches 2.7 V and the point where oscillation has stabilized. (2) At clearing stop mode, the time between the point where the RESET pin reaches the high level and the point where oscillation has stabilized. (3) At clearing stop mode, the time between the point where the STOPC pin reaches the low level and the point where oscillation has stabilized. At power on or when stop mode is cleared, RESET or STOPC must be input for at least tRC to ensure the oscillation stabilization time. Since the oscillator stabilization time will depend on circuit constants and stray capacitances, determine the oscillator by consulting with the oscillator’s manufacturer. Be sure to set miscellaneous register (MIS) bits MIS1 and MIS0 to match the system clock oscillator stabilization time. 4. Refer to figure 108. 5. Refer to figure 109. The t cyc unit applies when the MCU is in standby or active mode. The t subcyc unit applies when the MCU is in watch or subactive mode. 6. Refer to figure 110. 7. Refer to figure 111. 148 HD404629R Series Serial Interface Timing Characteristics (HD404628R, HD4046212R, HD404629R: V CC = 2.7 to 6.0 V, GND = 0 V, Ta = –20°C to +75°C; HD4074629: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) During Transmit Clock Output Item Symbol Pin Min Typ Max Unit Test Condition Notes Transmit clock cycle time tScyc SCK 1.0 — — tcyc Load shown in figure 113 1 Transmit clock high width tSCKH SCK 0.5 — — tScyc Load shown in figure 113 1 Transmit clock low width tSCKL SCK 0.5 — — tScyc Load shown in figure 113 1 Transmit clock rise time tSCKr SCK — — 200 ns Load shown in figure 113 1 Transmit clock fall time tSCKf SCK — — 200 ns Load shown in figure 113 1 Serial output data delay time tDSO SO — — 500 ns Load shown in figure 113 1 Serial input data setup time tSSI SI 300 — — ns — 1 Serial input data hold time tHSI SI 300 — — ns — 1 Note: 1. Refer to figure 112. During Transmit Clock Input Item Symbol Pin Min Typ Max Unit Test Condition Notes Transmit clock cycle time tScyc SCK 1.0 — — tcyc — 1 Transmit clock high width tSCKH SCK 0.5 — — tScyc — 1 Transmit clock low width tSCKL SCK 0.5 — — tScyc — 1 Transmit clock rise time tSCKr SCK — — 200 ns — 1 Transmit clock fall time tSCKf SCK — — 200 ns — 1 Serial output data delay time tDSO SO — — 500 ns Load shown in figure 113 1 Serial input data setup time tSSI SI 300 — — ns — 1 Serial input data hold time tHSI SI 300 — — ns — 1 Note: 1. Refer to figure 112. 149 HD404629R Series R L = 100 k Ω TONEC R L = 100 k Ω TONER GND Figure 111 Tone Output Load Circuit TONEC R L = 100 k Ω TONER GND Figure 112 Distortion and dBCR Load Circuit OSC1 1/fCP VCC – 0.3 V 0.3 V tCPL tCPH tCPr tCPf Figure 113 External Clock Timing INT0 to INT4, EVNB, EVND 0.9VCC 0.1VCC tIH tIL Figure 114 Interrupt Timing 150 HD404629R Series RESET 0.9VCC tRSTH 0.1VCC tRSTf Figure 115 Reset Timing STOPC 0.9VCC 0.1VCC tSTPL tSTPr Figure 116 STOPC Timing t Scyc t SCKf SCK VCC – 1.0 V (0.9VCC )* 0.4 V (0.1VCC)* t SCKr t SCKL t SCKH t DSO SO VCC – 1.0 V 0.4 V t SSI SI t HSI 0.9V CC 0.1VCC Note: * VCC – 1.0 V and 0.4 V are the threshold voltages for transmit clock output, and 0.9VCC and 0.1VCC are the threshold voltages for transmit clock input. Figure 117 Serial Interface Timing 151 HD404629R Series VCC RL = 2.6 kΩ Test point C= 30 pF R= 12 kΩ 1S2074 H or equivalent Figure 118 Timing Load Circuit 152 HD404629R Series Notes on ROM Out Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size as a 16-kword version (HD404629R). A 16-kword data size is required to change ROM data to mask manufacturing data since the program used is for a 16-kword version. This limitation applies when using an EPROM or a data base. ROM 8-kword version: HD404628R Address $2000–$3FFF ROM 12-kword version: HD4046212R Address $3000–$3FFF $0000 $0000 Vector address Vector address $000F $0010 $000F $0010 Zero-page subroutine (64 words) Zero-page subroutine (64 words) $003F $0040 $003F $0040 Pattern & program (8,192 words) Pattern & program (12,288 words) $2FFF $3000 $1FFF $2000 Not used Not used $3FFF $3FFF Fill this area with 1s 153 HD404629R Series HD404628R/HD4046212R/ HD404629R Option List Please check off the appropriate applications and enter the necessary information. Date of order / / Customer Department Name ROM code name LSI number (Hitachi entry) 1. ROM Size HD404628R 8-kword HD4046212R 12-kword HD404629R 16-kword 2. Optional Functions * With 32-kHz CPU operation, with time-base for clock * Without 32-kHz CPU operation, with time-base for clock Without 32-kHz CPU operation, without time-base for clock Note: * Options marked with an asterisk require a subsystem crystal oscillator (X1, X2). 3. ROM Code Data Type Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMs. 4. System Oscillator (OSC1 and OSC2) Ceramic oscillator f= MHz Crystal oscillator f= MHz External clock f= MHz 5. Stop Mode Used Not used 6. Package FP-100A FP-100B TFP-100B 154 HD404629R Series Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 URL NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to: Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic components Group Dornacher Straße 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. 155