IDT74ALVCH16374 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE LATCH WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT EDGETRIGGERED D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: IDT74ALVCH16374 DESCRIPTION: • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • VCC = 2.5V ± 0.2V µ W typ. static) • CMOS power levels (0.4µ • Rail-to-Rail output swing for increased noise margin • Available in SSOP, TSSOP, and TVSOP packages This 16-bit edge-triggered D-type flip-flop is built using advanced dual metal CMOS technology. The ALVCH16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels at the data (D) inputs. OE can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The highimpedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The ALVCH16374 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The ALVCH16374 has “bus-hold” which retains the inputs’ last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistor. DRIVE FEATURES: • High Output Drivers: ±24mA • Suitable for heavy loads APPLICATIONS: • 3.3V high speed systems • 3.3V and lower voltage computing systems FUNCTIONAL BLOCK DIAGRAM 1 OE 1 C LK 1 2 OE 48 2 CLK 24 25 C1 C1 2 1D 1 47 13 1Q 1 1D 2D 1 36 2Q 1 1D TO 7 OTHER CH ANNELS TO 7 OTHER C HANN ELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE APRIL 1999 1 © 1999 Integrated Device Technology, Inc. DSC-4564/1 IDT74ALVCH16374 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE LATCH WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol Description VTERM(2) Max Unit Terminal Voltage with Respect to GND –0.5 to +4.6 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V °C 1OE 1 48 1CLK TSTG Storage Temperature –65 to +150 1Q1 2 47 1D1 IOUT DC Output Current –50 to +50 mA IIK Continuous Clamp Current, VI < 0 or VI > VCC ±50 mA 1Q2 3 46 1D2 GND 4 45 GND IOK Continuous Clamp Current, VO < 0 –50 mA 1Q3 5 44 1D3 mA 6 43 1D4 Continuous Current through each VCC or GND ±100 1Q4 ICC ISS VCC 7 42 VCC 1Q5 8 41 1D5 1Q6 9 40 1D6 GND 10 39 GND 1Q7 11 38 1D7 1Q8 12 37 1D8 Symbol 2Q1 13 36 2D1 CIN Input Capacitance VIN = 0V 5 7 pF COUT Output Capacitance VOUT = 0V 7 9 pF CI/O I/O Port Capacitance VIN = 0V 7 9 pF NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) Conditions Typ. 2Q2 14 35 2D2 GND 15 34 GND 2Q3 16 33 2D3 2Q4 17 32 2D4 VCC 18 31 VCC 2Q5 19 30 2D5 2Q6 20 29 2D6 xCLK Clock Inputs GND 21 28 GND xQx 3-State Outputs 2Q7 22 27 2D7 xOE 3-State Output Enable Input (Active LOW) 2Q8 23 26 2D8 2OE 24 25 2CLK Max. Unit NOTE: 1. As applicable to the device type. PIN DESCRIPTION Pin Names xDx Description Data Inputs(1) NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os. FUNCTION TABLE (EACH FLIP-FLOP)(1) Inputs SSOP/ TSSOP/ TVSOP TOP VIEW Output xOE xCLK xDx xQx L ↑ H H L ↑ L L L H or L X Q(2) H X X Z NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High-Impedance ↑ = LOW-to-HIGH Transition 2. Output level before the indicated steady-state input conditions were established. 2 IDT74ALVCH16374 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE LATCH WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V IIH Input HIGH Current VCC = 3.6V VI = VCC — — ±5 µA IIL Input LOW Current VCC = 3.6V VI = GND — — ±5 µA IOZH High Impedance Output Current VCC = 3.6V VO = VCC — — ±10 µA IOZL (3-State Output pins) VO = GND — — ±10 VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ∆ICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 0.1 — 40 mV µA Quiescent Power Supply Current Variation One input at VCC - 0.6V, other inputs at VCC or GND — — 750 µA Min. Typ.(2) Max. Unit – 75 — — µA VI = 0.8V 75 — — VI = 1.7V – 45 — — 45 — — — ±500 NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. BUS-HOLD CHARACTERISTICS Symbol IBHH Parameter(1) Test Conditions Bus-Hold Input Sustain Current VCC = 3V Bus-Hold Input Sustain Current VCC = 2.3V Bus-Hold Input Overdrive Current VCC = 3.6V VI = 2V IBHL IBHH IBHL IBHHO VI = 0.7V VI = 0 to 3.6V IBHLO NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3 — µA µA IDT74ALVCH16374 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE LATCH WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH Test Conditions(1) Parameter Output HIGH Voltage Min. Max. Unit VCC – 0.2 — V IOH = – 6mA 2 — IOH = – 12mA 1.7 — 2.2 — VCC = 2.3V to 3.6V IOH = – 0.1mA VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VOL Output LOW Voltage 2.4 — VCC = 3V IOH = – 24mA 2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3V IOL = 24mA — 0.55 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. OPERATING CHARACTERISTICS, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance Outputs enabled CPD Power Dissipation Capacitance Outputs disabled VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Test Conditions Typical Typical Unit CL = 0pF, f = 10Mhz 31 30 pF 16 18 SWITCHING CHARACTERISTICS(1) VCC = 2.5V ± 0.2V Symbol Parameter fMAX VCC = 2.7V VCC = 3.3V ± 0.3V Min. Max. Min. Max. Min. Max. Unit 150 — 150 — 150 — MHz 1 5.3 — 4.9 1 4.2 ns 1 6.2 — 5.9 1 4.8 ns 1 5.3 — 4.7 1.2 4.3 ns tPLH Propagation Delay tPHL xCLK to xQx tPZH Output Enable Time tPZL xOE to xQx tPHZ Output Disable Time tPLZ xOE to xQx tSU Set-up Time, data before CLK↑ 2.1 — 2.2 — 1.9 — ns tH Hold Time, data after CLK↑ 0.6 — 0.5 — 0.5 — ns tW Pulse Duration, CLK HIGH or LOW 3.3 — 3.3 — 3.3 — ns Output Skew(2) — — — — — 500 ps tSK(o) NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2 Skew between any two outputs of the same package and switching in the same direction. 4 IDT74ALVCH16374 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE LATCH WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS VCC(1)= 3.3V±0.3V VCC(1)= 2.7V Symbol VCC(2)= 2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF (1, 2) tPHL V IH VT 0V ALVC Link DISABLE ENABLE CONTROL INPUT GND tPZL D.U.T. OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH 500 Ω RT t PLH CL ALVC Link Test Circuit for All Outputs V OH VT V OL Propagation Delay V OUT Pulse Generator t PHL OPPOSITE PHASE INPUT TRANSITION Open 500 Ω tPLH OUTPUT V LOAD V CC V IN V IH VT 0V SAME PHASE INPUT TRANSITION tPLZ V IH VT 0V V LOAD/2 V LOAD/2 VT V LZ V OL tPHZ VT V OH V HZ 0V 0V ALVC Link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Enable and Disable Times NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. V IH DATA VT INPUT 0V tSU tH V IH TIMING VT INPUT 0V tREM V IH ASYNCHRONOUS VT CONTROL 0V V IH SYNCHRONOUS VT CONTROL tSU 0V tH NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns. SWITCH POSITION Test Switch Open Drain Disable Low Enable Low VLOAD Disable High Enable High GND All Other Tests Open ALVC Link Set-up, Hold, and Release Times V IH INPUT VT 0V tPHL1 tPLH1 V OH OUTPUT 1 tSK (x) LOW-HIGH-LOW PULSE VT V OL tSK (x) tW V OH VT V OL OUTPUT 2 VT HIGH-LOW-HIGH PULSE VT ALVC Link tPLH2 tPHL2 Pulse Width tSK (x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) ALVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 IDT74ALVCH16374 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE LATCH WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX ALVC X Bus-Hold Temp. Range XX Family XX XXX Device Type Package CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 PV PA PF Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package 374 16-Bit Edge-Triggered D-Type Flip-Flop with 3-State Outputs 16 Double-Density, ±24mA H Bus-Hold 74 – 40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 6 for Tech Support: [email protected] (408) 654-6459