IDT IDT74ALVCH162374PAG

IDT74ALVCH162374
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH162374
3.3V CMOS 16-BIT EDGETRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS
AND BUS-HOLD
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
μ W typ. static)
• CMOS power levels (0.4μ
• Rail-to-Rail output swing for increased noise margin
• Available in TSSOP package
This 16-bit edge-triggered D-type flip-flop is built using advanced dual metal
CMOS technology. The ALVCH162374 is particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can
be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of
the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up
at the data (D) inputs. OE can be used to place the eight outputs in either a normal
logic state (high or low logic levels) or a high-impedance state. In the highimpedance state, the outputs neither load nor drive the bus lines significantly.
The high-impedance state and the increased drive provide the capability to
drive bus lines without need for interface or pullup components. OE does not
affect internal operations of the flip-flop. Old data can be retained or new data
can be entered while the outputs are in the high-impedance state.
The ALVCH162374 has series resistors in the device output structure which
will significantly reduce line noise when used with light loads. This driver has
been designed to drive ±12mA at the designated threshold levels.
The ALVCH162374 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs and
eliminates the need for pull-up/down resistor.
DRIVE FEATURES:
• Balanced Output Drivers: ±12mA
• Low switching noise
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1OE
1CLK
1
48
2OE
24
2CLK
25
C1
C1
2
1D1
47
13
1Q1
1D
2D1
36
2Q1
1D
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
MARCH 1999
1
© 1999 Integrated Device Technology, Inc.
DSC-4565/4
IDT74ALVCH162374
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
1OE
1
48
1CLK
1Q1
2
47
1D1
1Q2
3
46
1D2
GND
4
45
GND
1Q3
5
44
1D3
1Q4
6
43
1D4
VCC
7
42
VCC
1Q5
8
41
1D5
1Q6
9
40
1D6
GND
10
39
GND
1Q7
11
38
1D7
1Q8
12
37
1D8
2Q1
13
36
2D1
Symbol
Description
VTERM(2)
Max
Unit
Terminal Voltage with Respect to GND
–0.5 to +4.6
V
VTERM(3)
Terminal Voltage with Respect to GND
–0.5 to VCC+0.5
V
TSTG
Storage Temperature
–65 to +150
°C
–50 to +50
mA
±50
mA
IOUT
DC Output Current
IIK
Continuous Clamp Current,
VI < 0 or VI > VCC
IOK
Continuous Clamp Current, VO < 0
–50
mA
ICC
ISS
Continuous Current through each
VCC or GND
±100
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Parameter(1)
Symbol
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
5
7
pF
COUT
Output Capacitance
VOUT = 0V
7
9
pF
CI/O
I/O Port Capacitance
VIN = 0V
7
9
pF
2Q2
14
35
2D2
GND
15
34
GND
2Q3
16
33
2D3
2Q4
17
32
2D4
VCC
18
31
VCC
2Q5
19
30
2D5
Pin Names
Description
2Q6
20
29
2D6
xDx
Data Inputs(1)
GND
21
28
GND
xCLK
Clock Inputs
xQx
3-State Outputs
2Q7
22
27
2D7
xOE
3-State Output Enable Input (Active LOW)
2Q8
23
26
2D8
2OE
24
25
2CLK
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
FUNCTION TABLE (EACH FLIP-FLOP)(1)
TSSOP
TOP VIEW
Inputs
Outputs
xOE
xCLK
xDx
xQx
L
↑
H
H
L
↑
L
L
L
H or L
X
Qo(2)
H
X
X
Z
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑ = LOW-to-HIGH transition
2. Output level before the indicated steady-state input conditions were established.
2
IDT74ALVCH162374
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C
Symbol
VIH
VIL
Min.
Typ.(1)
Max.
Unit
VCC = 2.3V to 2.7V
1.7
—
—
V
VCC = 2.7V to 3.6V
2
—
—
VCC = 2.3V to 2.7V
—
—
0.7
VCC = 2.7V to 3.6V
—
—
0.8
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Test Conditions
V
IIH
Input HIGH Current
VCC = 3.6V
VI = VCC
—
—
±5
µA
IIL
Input LOW Current
VCC = 3.6V
VI = GND
—
—
±5
µA
IOZH
High Impedance Output Current
VCC = 3.6V
VO = VCC
—
—
±10
µA
IOZL
(3-State Output pins)
VO = GND
—
—
±10
VIK
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
—
–0.7
–1.2
V
VH
ICCL
ICCH
ICCZ
ΔICC
Input Hysteresis
Quiescent Power Supply Current
VCC = 3.3V
VCC = 3.6V
VIN = GND or VCC
—
—
100
0.1
—
40
mV
µA
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
750
µA
Min.
Typ.(2)
Max.
Unit
– 75
—
—
µA
VI = 0.8V
75
—
—
VI = 1.7V
– 45
—
—
VI = 0.7V
45
—
—
—
±500
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol
IBHH
Parameter(1)
Bus-Hold Input Sustain Current
Test Conditions
VCC = 3V
VI = 2V
IBHL
IBHH
Bus-Hold Input Sustain Current
VCC = 2.3V
IBHL
IBHHO
Bus-Hold Input Overdrive Current
VCC = 3.6V
VI = 0 to 3.6V
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3
—
µA
µA
IDT74ALVCH162374
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
VOH
VOL
Test Conditions(1)
Parameter
Output HIGH Voltage
Output LOW Voltage
Min.
Max.
Unit
VCC – 0.2
—
V
IOH = – 4mA
1.9
—
VCC = 2.3V to 3.6V
IOH = – 0.1mA
VCC = 2.3V
IOH = – 6mA
1.7
—
VCC = 2.7V
IOH = – 4mA
2.2
—
IOH = – 8mA
2
—
VCC = 3V
IOH = – 6mA
2.4
—
IOH = – 12mA
2
—
VCC = 2.3V to 3.6V
IOL = 0.1mA
—
0.2
VCC = 2.3V
IOL = 4mA
—
0.4
IOL = 6mA
—
0.55
VCC = 2.7V
IOL = 4mA
—
0.4
IOL = 8mA
—
0.6
IOL = 6mA
—
0.55
IOL = 12mA
—
0.8
VCC = 3V
V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25°C
Symbol
Parameter
CPD
Power Dissipation Capacitance Outputs enabled
CPD
Power Dissipation Capacitance Outputs disabled
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Test Conditions
Typical
Typical
Unit
CL = 0pF, f = 10Mhz
28
31
pF
10
11
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V ± 0.2V
Symbol
Parameter
Min.
fMAX
tPLH
Propagation Delay
tPHL
xCLK to xQx
tPZH
Output Enable Time
VCC = 2.7V
Max.
Min.
150
—
1
5.4
1
VCC = 3.3V ± 0.3V
Max.
Min.
Max.
Unit
150
—
—
5.4
150
—
MHz
1
4.6
ns
6.5
—
6.4
1
5.2
ns
1
5.6
—
5
1.2
4.5
ns
2.1
—
2.2
—
1.9
—
ns
tPZL
xOE to xQx
tPHZ
Output Disable Time
tPLZ
xOE to xQx
tSU
Setup Time, data before CLK↑
tH
Hold Time, data after CLK↑
0.6
—
0.5
—
0.5
—
ns
tW
Pulse Duration, LE HIGH or LOW
3.3
—
3.3
—
3.3
—
ns
Output Skew(2)
—
—
—
—
—
500
ps
tSK(O)
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74ALVCH162374
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol
VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
VCC(2)= 2.5V±0.2V
Unit
VLOAD
6
6
2 x Vcc
V
VIH
2.7
2.7
Vcc
V
VT
1.5
1.5
Vcc / 2
V
VLZ
300
300
150
mV
VHZ
300
300
150
mV
CL
50
50
30
pF
(1, 2)
VIN
tPLH
tPHL
VIH
VT
0V
ALVC Link
Propagation Delay
DISABLE
ENABLE
CONTROL
INPUT
GND
tPZL
VOUT
D.U.T.
OUTPUT
SWITCH
NORMALLY
CLOSED
LOW
tPZH
OUTPUT
SWITCH
NORMALLY
OPEN
HIGH
500Ω
RT
tPHL
OPPOSITE PHASE
INPUT TRANSITION
Open
500Ω
tPLH
OUTPUT
VLOAD
VCC
Pulse
Generator
VIH
VT
0V
VOH
VT
VOL
SAME PHASE
INPUT TRANSITION
CL
ALVC Link
Test Circuit for All Outputs
tPLZ
VLOAD/2
VT
VIH
VT
0V
VLOAD/2
VLZ
VOL
tPHZ
VOH
VHZ
0V
VT
0V
ALVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
DATA
INPUT
SWITCH POSITION
Test
GND
All Other Tests
Open
INPUT
OUTPUT 1
tPLH1
SYNCHRONOUS
CONTROL
VIH
VT
0V
VOH
VT
VOL
tSK (x)
OUTPUT 2
LOW-HIGH-LOW
PULSE
VT
tW
HIGH-LOW-HIGH
PULSE
VT
ALVC Link
tPHL2
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
tH
Set-up, Hold, and Release Times
VOH
VT
VOL
tPLH2
tSU
ALVC Link
tPHL1
tSK (x)
tREM
ASYNCHRONOUS
CONTROL
VLOAD
Disable High
Enable High
tH
TIMING
INPUT
Switch
Open Drain
Disable Low
Enable Low
tSU
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
ALVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74ALVCH162374
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
XX
ALVC X
Bus-Hold
Temp. Range
XX
Family
XX
XXX
Device Type Package
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
PA
PAG
Thin Shrink Small Outline Package
TSSOP - Green
374
16-Bit Edge-Triggered D-Type Flip-Flop with 3-State Outputs
162
Double-Density with Resistors, ±12mA
H
Bus-Hold
74
– 40°C to +85°C
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
6
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