ONSEMI NTD15N06T4

NTD15N06
Power MOSFET
15 Amps, 60 Volts
N−Channel DPAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
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15 AMPERES
60 VOLTS
RDS(on) = 76 m TYP)
Typical Applications
•
•
•
•
Power Supplies
Converters
Power Motor Controls
Bridge Circuits
N−Channel
D
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
60
Vdc
Drain−to−Gate Voltage (RGS = 1.0 M)
VDGR
60
Vdc
Gate−to−Source Voltage
− Continuous
− Non−repetitive (tp10 ms)
VGS
VGS
20
30
Drain Current
− Continuous @ TA = 25°C
− Continuous @ TA = 100°C
− Single Pulse (tp10 s)
ID
ID
15
10
45
Adc
1 2
Apk
48
0.32
2.1
1.5
W
W/°C
W
W
DPAK
CASE 369C
(Surface Mount)
Style 2
−55 to
+175
°C
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, L = 1.0 mH,
IL(pk) = 11 A, VDS = 60 Vdc)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
PD
TJ, Tstg
Vdc
S
4
EAS
4
Drain
3
4
4
Drain
mJ
1
°C/W
RJC
RJA
RJA
3.13
71.4
100
TL
260
°C
2
3
DPAK
CASE 369D
(Straight Lead)
Style 2
15N06
Device Code
Y
= Year
WW
= Work Week
Package
Shipping
DPAK
75 Units/Rail
NTD15N06−1
DPAK
Straight Lead
75 Units/Rail
NTD15N06T4
DPAK
2500/Tape & Reel
NTD15N06
1
1 2 3
Gate Drain Source
ORDERING INFORMATION
Device
September, 2003 − Rev. 1
2
1
3
Drain
Gate
Source
61
1. When surface mounted to an FR4 board using 0.5 sq. in. pad size.
2. When surface mounted to an FR4 board using the minimum recommended
pad size.
 Semiconductor Components Industries, LLC, 2003
MARKING DIAGRAMS
YWW
15N06
Total Power Dissipation @ TJ = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 1)
Total Power Dissipation @ TA = 25°C (Note 2)
IDM
G
YWW
15N06
Rating
Publication Order Number:
NTD15N06/D
NTD15N06
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
60
−
68
54.4
−
−
−
−
−
−
1.0
10
−
−
±100
2.0
−
2.9
6.3
4.0
−
−
76
90
−
−
1.2
1.08
1.62
−
gFS
−
6.7
−
mhos
Ciss
−
325
450
pF
Coss
−
108
150
Crss
−
34
70
td(on)
−
10
15
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 3)
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
Adc
nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−Resistance (Note 3)
(VGS = 10 Vdc, ID = 7.5 Adc)
RDS(on)
Static Drain−to−Source On−Voltage (Note 3)
(VGS = 10 Vdc, ID = 15 Adc)
(VGS = 10 Vdc, ID = 7.5 Adc, TJ = 150°C)
VDS(on)
Forward Transconductance (Note 3) (VDS = 7.0 Vdc, ID = 6.0 Adc)
Vdc
mV/°C
m
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
(VDD = 48 Vdc, ID = 15 Adc,
VGS = 10 Vdc, RG = 9.1 ) (Note 3)
Turn−Off Delay Time
Fall Time
Gate Charge
(VDS = 48 Vdc, ID = 15 Adc,
VGS = 10 Vdc) (Note 3)
ns
tr
−
25
70
td(off)
−
14
50
tf
−
13
50
QT
−
12
20
Q1
−
4.1
−
Q2
−
4.5
−
VSD
−
−
0.96
0.83
1.15
−
Vdc
trr
−
35
−
ns
ta
−
27
−
tb
−
7.4
−
QRR
−
0.050
−
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(IS = 15 Adc, VGS = 0 Vdc) (Note 3)
(IS = 15 Adc, VGS = 0 Vdc, TJ = 150°C)
Reverse Recovery Time
(IS = 15 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s) (Note 3)
Reverse Recovery Stored Charge
3. Pulse Test: Pulse Width ≤ 300 s, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
C
NTD15N06
ID, DRAIN CURRENT (AMPS)
VDS ≥ 10 V
8V
7V
24
6.5 V
6V
16
5.5 V
8
5V
4.5 V
0
1
3
2
4
5
0.12
TJ = 25°C
0.08
TJ = −55°C
0.04
4
5
6
8
7
4
8
12
16
20
24
28
32
0.2
VGS = 15 V
0.16
0.12
TJ = 100°C
0.08
TJ = 25°C
TJ = −55°C
0.04
0
0
4
8
12
16
20
24
28
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
Figure 4. On−Resistance versus Drain Current
32
1000
VGS = 0 V
ID = 7.5 A
VGS = 10 V
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
TJ = −55°C
Figure 2. Transfer Characteristics
TJ = 100°C
1.8
TJ = 100°C
Figure 1. On−Region Characteristics
0.16
2
TJ = 25°C
8
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
VGS = 10 V
0
16
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.2
0
24
0
3
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
32
9V
VGS = 10 V
ID, DRAIN CURRENT (AMPS)
32
1.6
1.4
1.2
1
TJ = 150°C
100
10
TJ = 100°C
0.8
0.6
−50 −25
1
0
25
50
75
100
125
150
175
0
10
20
30
40
50
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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60
NTD15N06
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
900
VDS = 0 V
VGS = 0 V
TJ = 25°C
C, CAPACITANCE (pF)
800
700
Ciss
600
500
400
Crss
Ciss
300
200
Coss
100
Crss
0
10
0
5
VGS
10
5
15
20
25
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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100
12
VDS = 30 V
ID = 15 A
VGS = 10 V
QT
10
VGS
8
Q1
t, TIME (ns)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
NTD15N06
Q2
6
tr
td(off)
10
tf
td(on)
4
2
ID = 15 A
TJ = 25°C
0
1
0
2
8
10
4
6
QG, TOTAL GATE CHARGE (nC)
12
1
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
10
RG, GATE RESISTANCE ()
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
IS, SOURCE CURRENT (AMPS)
16
VGS = 0 V
TJ = 25°C
12
8
4
0
0.6
0.68
0.84
0.76
0.92
1
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 s. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
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NTD15N06
ID, DRAIN CURRENT (AMPS)
100
VGS = 20 V
SINGLE PULSE
TC = 25°C
10 s
10
100 s
1 ms
10 ms
1
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
10
1
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
0.1
100
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
SAFE OPERATING AREA
80
ID = 11 A
60
40
20
0
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
50
75
100
125
175
150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
0.1
P(pk)
0.05
0.02
0.01
t1
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.01
0.00001
0.0001
0.001
0.01
t, TIME (s)
RJC(t) = r(t) RJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RJC(t)
0.1
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
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1
10
NTD15N06
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to ensure proper solder connection
6.20
0.244
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
2.58
0.101
5.80
0.228
3.0
0.118
1.6
0.063
6.172
0.243
SCALE 3:1
mm
inches
DPAK
The power dissipation for a surface mount device is a
PD = 175°C − 25°C = 2.1 Watts
function of the drain pad size. These can vary from the
71.4°C/W
minimum pad size for soldering to a pad size given for
The 71.4°C/W for the DPAK package assumes the use of
maximum power dissipation. Power dissipation for a
0.5 sq. in. source pad on a glass epoxy printed circuit board
surface mount device is determined by TJ(max), the
to achieve a power dissipation of 2.1 W. There are other
maximum rated junction temperature of the die, RJA, the
alternatives to achieving higher power dissipation from the
thermal resistance from the device junction to ambient, and
surface mount packages. One is to increase the area of the
the operating temperature, TA. Using the values provided
drain pad. By increasing the area of the drain pad, the
on the data sheet, PD can be calculated as follows:
power dissipation can be increased. Although one can
TJ(max) − TA
almost double the power dissipation with this method, one
PD =
RJA
will be giving up area on the printed circuit board which
can defeat the purpose of using surface mount technology.
The values for the equation are found in the maximum
For example, a graph of RJA versus drain pad area is shown
ratings table on the data sheet. Substituting these values
in Figure 15.
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device. For a
DPAK device, PD is calculated as follows.
RθJA , THERMAL RESISTANCE, JUNCTION
TO AMBIENT (°C/W)
100
Board Material = 0.0625″
G−10/FR−4, 2 oz Copper
2.1 Watts
80
TA = 25°C
60
3.6 Watts
40
20
0
6.0 Watts
2
4
6
A, AREA (SQUARE INCHES)
8
10
Figure 15. Thermal Resistance versus Drain Pad
Area for the DPAK Package (Typical)
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NTD15N06
SOLDER STENCIL GUIDELINES
pattern of the opening in the stencil for the drain pad is not
critical as long as it allows approximately 50% of the pad to
be covered with paste.
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads.
Solder stencils are used to screen the optimum amount.
These stencils are typically 0.008 inches thick and may be
made of brass or stainless steel. For packages such as the
SC−59, SC−70/SOT−323, SOD−123, SOT−23, SOT−143,
SOT−223, SO−8, SO−14, SO−16, and SMB/SMC diode
packages, the stencil opening should be the same as the pad
size or a 1:1 registration. This is not the case with the DPAK
and D2PAK packages. If one uses a 1:1 opening to screen
solder onto the drain pad, misalignment and/or
“tombstoning” may occur due to an excess of solder. For
these two packages, the opening in the stencil for the paste
should be approximately 50% of the tab area. The opening
for the leads is still a 1:1 registration. Figure 16 shows a
typical stencil for the DPAK and D2PAK packages. The
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ ÇÇ
ÇÇÇ
ÇÇÇ ÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
SOLDER PASTE
OPENINGS
STENCIL
Figure 16. Typical Stencil for DPAK and
D2PAK Packages
SOLDERING PRECAUTIONS
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
* * Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
* * Due to shadowing and the inability to set the wave
height to incorporate other surface mount components, the
D2PAK is not recommended for wave soldering.
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NTD15N06
TYPICAL SOLDER HEATING PROFILE
The line on the graph shows the actual temperature that
might be experienced on the surface of a test board at or
near a central solder joint. The two profiles are based on a
high density and a low density board. The Vitronics
SMD310 convection/infrared reflow soldering system was
used to generate this profile. The type of solder used was
62/36/2 Tin Lead Silver with a melting point between
177−189°C. When this type of furnace is used for solder
reflow work, the circuit boards and solder joints tend to
heat first. The components on the board are then heated by
conduction. The circuit board, because it has a large surface
area, absorbs the thermal energy more efficiently, then
distributes this energy to the components. Because of this
effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joint.
For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones,
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 17 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems but it is a good starting point. Factors that
can affect the profile include the type of soldering system in
use, density and types of components on the board, type of
solder used, and the type of board or substrate material
being used. This profile shows temperature versus time.
STEP 1
PREHEAT
ZONE 1
“RAMP”
200°C
STEP 2
STEP 3
VENT
HEATING
“SOAK” ZONES 2 & 5
“RAMP”
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
160°C
STEP 5
STEP 6
STEP 7
HEATING
VENT
COOLING
ZONES 4 & 7
205° TO 219°C
“SPIKE”
PEAK AT
170°C
SOLDER
JOINT
150°C
150°C
100°C
140°C
100°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
5°C
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 17. Typical Solder Heating Profile
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NTD15N06
PACKAGE DIMENSIONS
DPAK
CASE 369C−01
ISSUE O
−T−
C
B
V
SEATING
PLANE
E
R
4
Z
A
S
1
2
DIM
A
B
C
D
E
F
G
H
J
K
L
R
S
U
V
Z
3
U
K
F
J
L
H
D
2 PL
G
0.13 (0.005)
M
T
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.090 BSC
0.180 0.215
0.025 0.040
0.020
−−−
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
4.58 BSC
0.87
1.01
0.46
0.58
2.60
2.89
2.29 BSC
4.57
5.45
0.63
1.01
0.51
−−−
0.89
1.27
3.93
−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
DPAK
CASE 369D−01
ISSUE O
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
H
D
G
3 PL
0.13 (0.005)
M
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
T
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NTD15N06/D