ETC PI74ALVCH16841A

PI74ALVCH16841
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20-Bit Bus-Interface D-Type Latch
with 3-State Outputs
Product Features
Product Description
• PI74ALVCH16841 is designed for low voltage operation
Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced using the Company’s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
• VCC = 2.3V to 3.6V
• Hysteresis on all inputs
• Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
• Bus Hold retains last active bus state during 3-State,
eliminating the need for external pullup resistors
• Industrial operation at –40°C to +85°C
• Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 300 mil wide plastic SSOP (V)
The PI74ALVCH16841, a 20-bit bus-interface D-type latch designed
for 2.3V to 3.6V VCC operation.
The PI74ALVCH16841 features 3-state outputs designed specifically
for driving highly capacitive or relatively low-impedance loads.
It is particularly suitable for implementing buffer registers,
unidirectional bus drivers, and working registers.
The PI74ALVCH16841 can be used as two 10-bit latches or one
20-bit latch (transparent D-type). The device has non-inverting
Data (D) inputs and provides true data at its outputs. While the
Latch Enable (1LE or 2LE) input is HIGH, the Q outputs of the
corresponding 10-bit latch follow the D inputs. When LE is taken
LOW, the Q outputs are latched at the levels set up at the D inputs.
A buffered Output Enable (1OE or 2OE) input can be used to place
the outputs of the corresponding 10-bit latch in either a normal logic
state (high or low logic levels) or a high-impedance state. In that
state, outputs neither load nor drive the bus lines significantly.
Logic Block Diagram
1OE
1LE
The Output Enable (OE) input does not affect the internal operation
of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
1
56
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
C1
2
1D1
55
1Q1
1D
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
TO NINE OTHER CHANNELS
2OE
2LE
28
29
C1
15
2D1
42
2Q1
1D
TO NINE OTHER CHANNELS
1
PS8182A
11/06/00
PI74ALVCH16841
20-Bit
Bus
Interface
D-Type Latch
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Truth Table(1) ( Each 10-Bit Latch)
Product Pin Description
Inputs
Outputs
Pin Name
De s cription
OE
Output Enable Input (Active LOW)
OE
LE
D
Q
LE
Latch Enable
L
H
H
H
D
Data Input
L
H
L
L
Q
Data Output
L
L
X
QO
GND
Ground
H
X
X
Z
VCC
Power
Note:
1. H = High Signal Level
L = Low Signal Level
Z = High Impedance
X = Irrelevant
Product Pin Configuration
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2Q10
2OE
56
1
55
2
54
3
53
4
52
5
51
6
50
7
49
8
48
9
47
10
56-Pin
46
11
12 A, V 45
44
13
43
14
42
15
41
16
40
17
39
18
38
19
37
20
36
21
35
22
34
23
33
24
32
25
26
31
27
30
28
29
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9
2D10
2LE
2
PS8182A
11/06/00
PI74ALVCH16841
20-Bit
Bus
Interface
D-Type Latch
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ........................................................... –65°C to +150°C
Ambient Temperature with Power Applied .......................... –40°C to +85°C
Input Voltage Range, VIN ....................................................... –0.5V to VCC +0.5V
Output Voltage Range, VOUT ................................................ –0.5V to VCC +0.5V
DC Input Voltage ....................................................................–0.5V to +5.0V
DC Output Current ............................................................................. 100mA
Power Dissipation ..................................................................................1.0W
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect reliability.
Recommended Operating Conditions(1)
Parame te rs
De s cription
VCC
Supply Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VIN
Input Voltage
0
VCC
VOUT
Output Voltage
0
VCC
IOH
IOL
TA
High- level Output Current
Low- level Output Current
Te s t Conditions
M in.
Typ.
2.3
VCC = 2.3V to 2.7V
1.7
VCC = 2.7V to 3.6V
2.0
M ax.
3.6
VCC = 2.3V to 2.7V
0.7
VCC = 2.7V to 3.6V
0.8
VCC = 2.3V
–12
VCC = 2.7V
–12
VCC = 3.0V
–24
VCC = 2.3V
12
VCC = 2.7V
12
VCC = 3.0V
24
Operating Free- Air Temperature
- 40
Units
85
V
mA
°C
Note:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
3
PS8182A
11/06/00
PI74ALVCH16841
20-Bit
Bus
Interface
D-Type Latch
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DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ± 10%)
Parame te rs
VCC(1)
Te s t Conditions
IOH = - 100 µA
IOH = - 6 MA
VOH
IOH = - 12 mA
IOH = - 24 MA
VOL
IOL = 12 MA
IOL = 24 mA
II
VIH = 1.7V
2.3V
2.0
VIH = 1.7V
2.3V
1.7
VIH = 2.0V
2.7V
2.2
VIH = 2.0V
3.0V
2.4
VIH = 2.0V
3.0V
2.0
M ax. Units
V
Min. to Max.
0.2
VIL = 0.7V
2.3V
0.4
VIL = 0.7V
2.3V
0.7
VIL = 0.8V
2.7V
0.4
VIL = 0.8V
3.0V
0.55
3.6V
±5
VI = VCC or GND
VI = 0.7V
2.3V
VI = 1.7V
II (Hold)(3)
Typ.(2)
Min. to Max. VCC - 0.2
IOL = 100 µA
IOL = 6 mA
M in.
VI = 0.8V
3.0V
VI = 2.0V
45
–45
75
µA
–75
VI = 0 to 3.6V
3.6V
±500
IOZ(4)
VO = VCC or GND
3.6V
±10
ICC
VI = VCC or GND
3.6V
40
∆ICC
One input at VCC - 0.6V, Other inputs at VCC or GND
3V to 3.6V
750
IO = 0
CI Control Inputs VI = VCC or GND
3.3V
3.5
Data Input
VO = VCC or GND
3.3V
6
CO Outputs
VO = VCC or GND
3.3V
7
pF
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient and maximum loading.
3. Bus Hold maximum dynamic current required to switch the input from one state to another.
4. For I/O ports, the IOZ includes the input leakage current.
4
PS8182A
11/06/00
PI74ALVCH16841
20-Bit
Bus
Interface
D-Type Latch
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Timing Requirements over Operating Range
Parame te rs
VCC = 2.5 V ± 0.2V
De s cription
M in.
tW Pulse Duration LE high
tSU Setup time
tH Hold time
Dt/Dv(1)
M ax.
VCC = 2.7V
M in.
VCC = 3.3V ± 0.3V
M ax.
M in.
3.3
3.3
3.3
Data before LE­
0.9
0.7
1.1
Data after LE­
1.2
1.5
1.1
Input Transition Rise or Fall
0
10
0
10
0
M ax.
Units
ns
10
ns/V
Note:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
Switching Characteristics Over Operating Range(1)
Parame te rs
tPD
VCC = 2.5V ± 0.2V
From
To
(INPUT) (OUTPUT) M in.(2)
M ax.
D
LE
tEN
OE
tDIS
OE
Q
VCC = 2.7V
M in.(2)
VCC = 3.3 V ± 0.3V
M ax.
M in.(2)
M ax.
1.0
5.0
4.7
1.2
3.9
1.0
5.6
5.1
1.0
4.3
1.0
6.2
6.0
1.0
4.9
1.1
5.3
4.3
1.3
4.1
Units
ns
Notes:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
Operating Characteristics, TA = 25ºC
Parame te r
CPD Power Dissipation
Capacitance
O utputs Enabled
O utputs Disabled
VCC = 2.5V ± 0.2V
Te s t Conditions
VCC = 3.3V ± 0.3V
Typical
CL = 50pF,
f = 10 MHz
12
20
1
3
Units
pF
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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PS8182A
11/06/00