PI74ALVCH16373 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 16-Bit Transparent D-Type Latch with 3-STATE Outputs Product Features Product Description • • • • Pericom Semiconductor’s PI74ALVCH series of logic circuits are produced in the Company’s advanced 0.5 micron CMOS technology, achieving industry leading speed. • • • • PI74ALVCH16373 is designed for low voltage operation VCC = 2.3V to 3.6V Hysteresis on all inputs Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25°C Typical VOHV (Output VOH Undershoot) < 2.0V at VCC = 3.3V, TA = 25°C Bus Hold retains last active bus state during 3-STATE, eliminating the need for external pullup resistors Industrial operation at –40°C to +85°C Packages available: – 48-pin 240 mil wide plastic TSSOP (A) – 48-pin 300 mil wide plastic SSOP (V) This 16-bit transparent D-type latch is designed for 2.3V to 3.6V VCC operation. The PI74ALVCH16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the Latch Enable (LE) input is HIGH, the Q outputs follow the (D) inputs. When LE is taken LOW, the Q outputs are latched at the levels set up at the D inputs. A buffered Output Enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state in which the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high impedance state. Logic Block Diagram 1OE 1LE 1 To ensure the high impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 48 C1 2 1D1 47 Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. 1Q1 1D To Seven Other Channels 2OE 2LE 24 25 C1 13 2D1 36 2Q1 1D To Seven Other Channels 1 PS8093B 10/09/00 PI74ALVCH16373 16-Bit Transparent D-Type Latch with 3-STATE Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Truth Table(1) Product Pin Description Pin Name OE LE Dx Qx GND VCC Description Output Enable Input (Active LOW) Latch Enable (Active HIGH) Data Inputs 3-State Outputs Ground Power Inputs Outputs OE LE D Q L H H H L H L L L L X Q0 H X X Z Notes: 1. H = High Signal Level L = Low Signal Level X = Irrelevant Z = High Impedance Product Pin Configuration 1OE 1 48 1LE 1Q1 2 47 1D1 1Q2 3 46 1D2 GND 4 45 GND 1Q3 5 44 1D3 1Q4 6 43 1D4 VCC 7 42 VCC 1Q5 8 41 1D5 1Q6 9 40 1D6 GND 10 39 GND 1Q7 11 38 1D7 48-Pin V,A 1Q8 12 37 1D8 2Q1 13 36 2D1 2Q2 14 35 2D2 GND 15 34 GND 2Q3 16 33 2D3 2Q4 17 32 2D4 VCC 18 31 VCC 2Q5 19 30 2D5 2Q6 20 29 2D6 GND 21 28 GND 2Q7 22 27 2D7 2Q8 23 26 2D8 2OE 24 25 2LE 2 PS8093B 10/09/00 PI74ALVCH16373 16-Bit Transparent D-Type Latch with 3-STATE Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ............................................................ –65°C to +150°C Ambient Temperature with Power Applied .......................... –40°C to +85°C Input Voltage Range, VIN .................................................... –0.5V to VCC +0.5V Output Voltage Range, VOUT ............................................. –0.5V to VCC +0.5V DC Input Voltage ................................................................... –0.5V to +5.0V DC Output Current .............................................................................. 100 mA Power Dissipation ................................................................................... 1.0W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ±10%) Te s t Conditions (1) De s cription VCC Supply Voltage VIH(3) Input HIGH Voltage VIL(3) Input LOW Voltage VIN(3) Input Voltage 0 VCC VOUT(3) Output Voltage 0 VCC VOH VOL IOH(3) Output HIGH Voltage Output LOW Voltage Output HIGH Current M in. Typ.(2) Parame te rs 2.3 VCC = 2.3V to 2.7V 1.7 VCC = 2.7V to 3.6V 2.0 M ax. 3.6 VCC = 2.3V to 2.7V 0.7 VCC = 2.7V to 3.6V 0.8 IOH = - 100µA, VCC = Min. to Max. VCC - 0.2 VIH = 1.7V, IOH = - 6mA, VCC = 2.3V 2.0 VIH = 1.7V, IOH = - 12mA, VCC = 2.3V 1.7 VIH = 2.0V, IOH = - 12mA, VCC = 2.7V 2.2 VIH = 2.0V, IOH = - 12mA, VCC = 3.0V 2.4 VIH = 2.0V, IOH = - 24mA, VCC = 3.0V 2.0 Units V IOL = 100µA, VIL = Min. to Max. 0.2 VIL = 0.7V, IOL = 6mA, VCC = 2.3V 0.4 VIL = 0.7V, IOL = 12mA, VCC = 2.3V 0.7 VIL = 0.8V, IOL = 12mA, VCC = 2.7V 0.4 VIL = 0.8V, IOL = 24mA, VCC = 3.0V 0.55 VCC = 2.3V - 12 VCC = 2.7V - 12 VCC = 3.0V - 24 mA IOL(3) Output LOW Current VCC = 2.3V 12 VCC = 2.7V 12 VCC = 3.0V 24 3 PS8093B 10/09/00 PI74ALVCH16373 16-Bit Transparent D-Type Latch with 3-STATE Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics-Continued (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ±10%) Te s t Conditions (1) Parame te rs De s cription IIN IIN (HOLD) Input Current Typ.(2) M in. VIN = VCC or GND, VCC = 3.6V Input Hold Current M ax. ±5 VIN = 0.7V, VCC = 2.3V 45 VIN = 1.7V, VCC = 2.3V - 45 VIN = 0.8V, VCC = 3.0V 75 VIN = 2.0V, VCC = 3.0V - 75 VIN = 0 to 3.6V, VCC = 3.6V ±500 IOZ Output Current (3- STATE Outputs) VOUT = VCC or GND, VCC = 3.6V ±10 ICC Supply Current VCC = 3.6V, IOUT = 0µA, VIN = GND or VCC 40 ∆ICC Supply Current per Input @ TTL HIGH VCC = 3.0V to 3.6V One Input at VCC - 0.6V Other Inputs at VCC or GND 750 Control Inputs CI CO Units µA 3 VIN = VCC or GND, VCC = 3.3V Data Inputs Outputs 6 VO = VCC or GND, VCC = 3.3V pF 7 Notes: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient and maximum loading. 3. Unused Control Inputs must be held HIGH or LOW to prevent them from floating. Timing Requirements over Operating Range Parame te rs De s cription VCC = 2.5V ±0.2V M in. M ax. VCC = 2.7V M in. M ax. VCC = 3.3V ±0.3V M in. tW Pulse Duration LE HIGH or LOW 3.3 3.3 3.3 tSU Setup Time Data Before LE↓ 1.0 1. 0 1.1 tH Hold Time Data After LE↓ 1.5 1.7 1.4 ∆t/∆v(1) Input Transition Rise or Fall 0 10 0 10 0 Units M a x. ns 10 ns/V Note: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. 4 PS8093B 10/09/00 PI74ALVCH16373 16-Bit Transparent D-Type Latch with 3-STATE Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Characteristics over Operating Range(1) Parame te rs From (INPUT) To (OUTPUT) VCC = 2.5V ±0.2V M in.(2) M ax. 1.0 VCC = 2.7V VCC = 3.3V ±0.3V M ax. M in.(2) M ax. 4.5 4.3 1.1 3.6 1. 0 5.9 4.6 1. 0 3.9 M in. tPD D tPD LE tEN OE 1. 0 6.0 5.7 1. 0 4.7 tDIS OE 1. 9 5.1 4.5 1.4 4.1 Units Q ns Notes: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. Operating Characteristics, TA = 25ºC Parame te r Te s t Conditions VCC = 2.5V ±0.2V VCC = 3.3V ±0.3V Units Typ. CPD Power Dissipation Capacitance Outputs Enabled 19 22 4 5 CL = 50pF, f = 10 MHz Outputs Disabled pF Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 5 PS8093B 10/09/00