STB60NE06L-16 N-CHANNEL 60V - 0.014 Ω - 60A D2PAK STripFET II POWER MOSFET TYPE STB60NE06L-16 ■ ■ ■ ■ ■ ■ ■ VDSS R DS(on) ID 60 V <0.016 Ω 60 A TYPICAL RDS(on) = 0.014 Ω AVALANCHE RUGGED TECHNOLOGY LOW GATE CHARGE HIGH CURRENT CAPABILITY 175 oC OPERATING TEMPERATURE LOW THRESHOLD DRIVE SURFACE-MOUNTING D2PAK (TO-263) POWER PACKAGE IN TUBE (NO SUFFIX) OR IN TAPE & REEL (SUFFIX “T4”) DESCRIPTION This Power MOSFET is the latest development of STMicroelectronis unique ”Single Feature Size ” strip-based process. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. 3 1 D2 PAK TO-263 (Suffix “T4”) INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ HIGH CURRENT, HIGH SWITCHING SPEED ■ SOLENOID AND RELAY DRIVERS ■ DC-DC & DC-AC CONVERTERS ■ AUTOMOTIVE ENVIRONMENT ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Unit 60 V 60 V ± 15 V ID Drain Current (continuous) at TC = 25°C 60 A ID Drain Current (continuous) at TC = 100°C 42 A Drain Current (pulsed) 240 A Total Dissipation at TC = 25°C IDM (•) P tot 150 W Derating Factor 1 W/°C dv/dt (1) Peak Diode Recovery voltage slope 11 V/ns E AS (2) Single Pulse Avalanche Energy 400 mJ -55 to 175 °C Tstg Tj Storage Temperature Operating Junction Temperature (•) Pulse width limit ed by safe operating area. March 2002 . Value (1) ISD ≤60A, di/dt ≤300A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX (2) Starting Tj = 25 o C, ID = 60A, VDD = 35V 1/9 STB60NE06L-16 THERMAL DATA Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Maximum Lead Temperature For Soldering Purpose Max Max °C/W °C/W °C 1 62.5 300 ELECTRICAL CHARACTERISTICS (Tcase = 25 °C unless otherwise specified) OFF Symbol Parameter Test Conditions Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 IDSS Zero Gate Voltage Drain Current (V GS = 0) VDS = Max Rating VDS = Max Rating TC = 125°C IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 15V V(BR)DSS Min. Typ. Max. 60 Unit V 1 10 µA µA ±100 nA ON (*) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS RDS(on) Static Drain-source On Resistance VGS = 5 V VGS = 10 V ID = 250 µA Min. Typ. Max. Unit 1 1.6 2.5 V 0.014 0.012 0.016 0.014 Ω Ω Typ. Max. Unit ID = 30 A ID = 30 A DYNAMIC Symbol 2/9 Parameter Test Conditions Min. g fs (*) Forward Transconductance VDS>ID(on)xR DS(on)max ID=30 A 30 S C iss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25V f = 1 MHz VGS = 0 4150 590 150 pF pF pF STB60NE06L-16 ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Time Rise Time VDD = 30 V ID = 30 A VGS = 4.5 V RG = 4.7 Ω (Resistive Load, Figure 3) 50 155 Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD= 40V ID= 60A VGS= 5V 55 15 30 70 nC nC nC Typ. Max. Unit ns ns SWITCHING OFF Symbol tr(Voff) tf tc Parameter Off-Voltage Rise Time Fall Time Cross-over Time Test Conditions Min. Vclamp = 48 V ID = 20 A VGS = 5 V RG = 4.7Ω (Inductive Load, Figure 5) 45 220 280 ns ns ns SOURCE DRAIN DIODE Symbol Parameter ISD ISDM (•) Source-drain Current Source-drain Current (pulsed) VSD (*) Forward On Voltage ISD = 60 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 60 A di/dt = 100A/µs Tj = 150°C VDD = 30 V (see test circuit, Figure 5) trr Qrr IRRM Test Conditions Min. Typ. VGS = 0 85 300 7 Max. Unit 60 240 A A 1.3 V ns nC A (*)Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (•)Pulse width limited by safe operating area. Safe Operating Area Thermal Impedance 3/9 STB60NE06L-16 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/9 STB60NE06L-16 Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized Breakdown Voltage Temperature . . 5/9 STB60NE06L-16 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/9 STB60NE06L-16 D2PAK MECHANICAL DATA DIM. MIN. mm. TYP. MAX. MIN. inch. TYP. TYP. A 4.4 4.6 0.173 0.181 A1 2.49 2.69 0.098 0.106 A2 B 0.03 0.7 0.23 0.93 0.001 0.028 0.009 0.037 B2 C 1.14 0.45 1.7 0.6 0.045 0.018 0.067 0.024 C2 1.21 1.36 0.048 0.054 D 8.95 9.35 0.352 0.368 D1 E 10 10.4 0.394 E1 G 8.5 4.88 5.28 8 0.315 0.409 0.334 0.192 0.208 L 15 15.85 0.591 0.624 L2 1.27 1.4 0.050 0.055 L3 M 1.4 2.4 1.75 3.2 0.055 0.094 0.069 0.126 R V2 0° 8° 0° 0.4 0.016 8° 7/9 STB60NE06L-16 D2PAK FOOTPRINT TUBE SHIPMENT (no suffix)* TAPE AND REEL SHIPMENT (suffix ”T4”)* REEL MECHANICAL DATA DIM. mm MIN. A DIM. mm MAX. MIN. MAX. A0 10.5 10.7 0.413 0.421 B0 15.7 15.9 0.618 0.626 D 1.5 1.6 0.059 0.063 D1 1.59 1.61 0.062 0.063 E 1.65 1.85 0.065 0.073 F 11.4 11.6 0.449 0.456 K0 4.8 5.0 0.189 0.197 P0 3.9 4.1 0.153 0.161 P1 11.9 12.1 0.468 0.476 P2 1.9 2.1 0075 0.082 R 50 1.574 T 0.25 0.35 .0.0098 0.0137 W 23.7 24.3 0.933 0.956 * on sales type 8/9 inch MIN. MIN. 330 B 1.5 C 12.8 D 20.2 G 24.4 N 100 T TAPE MECHANICAL DATA inch MAX. MAX. 12.992 0.059 13.2 0.504 0.520 0.795 26.4 0.960 1.039 3.937 30.4 1.197 BASE QTY BULK QTY 1000 1000 STB60NE06L-16 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics 2002 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. 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