Main Features • Programmable DMUX Ratio: • • • • • • • • • • • • • • – 1:4 Data Rate Max = 1 Gsps – PD (8b/10b) < 4.3/4.7 W (ECL 50 Ω Output) – 1:8 Data Rate Max = 2 Gsps – PD (8b/10b) < 6/6.9 W (ECL 50 Ω Output) – 1:16 With 1 TS8388B or 1 TS83102G0 and 2 DMUX Parallel Output Mode 8/10-bit ECL Differential Input Data Data Ready or Data Ready 2 Input Clock Input Clock Sampling Delay Adjust Single-ended Output Data: – Adjustable Common Mode and Swing – Logic Threshold Reference Output – ECL, PECL, TTL Asynchronous Reset Synchronous Reset ADC and DMUX Multi-channel Applications: – Stand-alone Delay Adjust Cell for ADCs Sampling Instant Alignment Differential Data Ready Output Built-in Self Test (BIST) Dual Power Supply VEE = -5 V, VCC = 5 V Radiation Tolerance Oriented Design (More Than 100 Krad (Si) Expected) Thermally Enhanced CQFP196 Cavity Up Package 1:4/1:8 8/10-bit 2 Gsps DMUX TS81102G0FS Target Specification Screening • Temperature Range: – C Grade: 0°C < Tc; Tj < 90°C – V Grade: -40°C < Tc; Tj < 110°C – M Grade: -55°C < Tc; Tj < 125°C Summary • Standard Screening Level for “C”, “V” and “M” Grades • ESA SCC 9000 Space Screening Flow for “M” Grade (on Request) Note: For more information please contact [email protected] For commercial and industrial temperature ranges the DMUX is also available in a TBGA240 package (P/N: TS81102G0CTP and TS81102G0VTP). Description The TS81102G0 is a monolithic 10-bit high-speed (up to 2 Gsps) demultiplexer. The DMUX is designed to run with all kinds of ADCs and more specifically, it fits perfectly with Atmel’s high-speed ADC 8-bit 1 Gsps TS8388B and ADC 10-bit 2 Gsps TS83102G0B. The TS81102G0 uses an innovative architecture, including a sampling delay adjust and tunable output levels. This DMUX allows users to process the highspeed output data stream down to standard signal processors speed (standard FPGAs). 5344AS–BDC–09/03 Note: This is a summary document. A complete document is not available at this time. For more information, please contact your local Atmel sales office. 1 Package Description Table 1. Pin Description Symbol Pin Number Description VCC 5, 127 Positive 5 V power supply VEE 1, 10, 16, 22, 28, 34, 40, 46, 58, 73, 92, 112, 123, 141, 155, 172, 189, 196 Negative -5 V power supply VPLUSD 53, 61, 64, 69, 78, 83, 87, 95, 98, 101, 102, 106, 109, 115, 122, 126, 130, 133, 136, 144, 145, 148, 152, 160, 163, 167, 177, 181, 184, 193 Output buffer power supply GND 2, 7, 13, 19, 25, 31, 37, 43, 49, 50, 99, 100, 118, 128, 146, 147 Ground DMUXDelAdjCtrl 194 In-phase DMUX clock delay cell control signal DMUXDelAdjCtrlB 195 Inverted phase DMUX clock delay cell control signal ADCDelAdjCtrl 47 In-phase stand-alone delay cell control signal ADCDelAdjCtrlB 48 Inverted phase stand-alone delay cell control signal SwiAdj 121 Swing adjust function control signal DIODE 6 Die junction temperature monitoring signal ClkIn 21 In-phase input clock signal ClkInB 20 Inverted phase input clock signal I[0…9] 9, 12, 15, 18, 24, 27, 30, 33, 36, 39 In-phase input data I[0…9]B 8, 11, 14, 17, 23, 26, 29, 32, 35, 38 Inverted phase input data SyncReset 4 In-phase synchronous reset SyncResetB 3 Inverted phase synchronous reset ADCDelAdjIn 44 In-phase input of the stand-alone delay cell ADCDelAdjInB 45 Inverted phase input of the stand-alone delay cell Power Supplies Analog Input Signals ECL Input Signals 2 TS81102G0FS 5344AS–BDC–09/03 TS81102G0FS Table 1. Pin Description (Continued) Output Data A[0…9] B[0…9] C[0…9] D[0…9] E[0…9] F[0…9] G[0…9] H[0…9] 179, 180, 182, 183, 185, 186, 187, 188, 190, 191 56, 57, 59, 60, 62, 63, 65, 66, 67, 68 165, 166, 168, 169, 170, 171, 173, 174, 175, 176 71, 72, 74, 75, 76, 77, 79, 80, 81, 82 150, 151, 153, 154, 156, 157, 158, 159, 161, 162 85, 86, 88, 89, 90, 91, 93, 94, 96, 97 131, 132, 134, 135, 137, 138, 139, 140, 142, 143 104, 105, 107, 108, 110, 111, 113, 114, 116, 117 Output data RefA to RefH 178, 55, 164, 70, 149, 84, 129, 103 Reference outputs (tied to the common mode voltage of each port) DR 125 In-phase Data Ready Signal (centered in the output data, frequency = output data frequency/2) DRB 124 Inverted phase Data Ready Signal (centered in the output data, frequency = output data frequency /2) 192 Asynchronous reset (active high) ClkInType 51 Input clock type: DR mode = Logic 1 DR/2 mode = Logic 0 RatioSel 120 DMUX ratio selection: 1:4 mode = Logic 1 1:8 mode = Logic 0 NbBit 52 Number of bits selection 10 bits = Logic 1 8 bits = Logic 0 BIST 54 Built-in self-test mode (active low) ADCDelAdjOUT 41 In-phase output of the stand-alone delay cell ADCDelAdjOUTB 42 Inverted phase output of the stand-alone delay cell TTL Input Signals AsyncReset Other Output Signals 3 5344AS–BDC–09/03 Figure 1. Pinout Top View Top View 4 TS81102G0FS 5344AS–BDC–09/03 TS81102G0FS Figure 2. CQFP 196 Package Top View Lands for Capacitor (Chip size 0603) Chamfer 0.5 ±0.25 Chamfer 0.76 ±0.25 (x3) Pin 1 Index 38.80 mm ±0.18 mm 33.91 mm ±0.10 mm 18.54 mm 0.635 mm pitch 0.230 mm + 0.050/-0.038 lead width (196x) 18.54 mm 33.91 mm ±0.10 mm 38.80 mm ±0.18 mm Note: Package: black AI203 ceramic Leads: Kovar, Ni and Au plating Lid: Kovar, Ni and Au plating Heatspreader on bottom: CuW with Ni and Au plating 5 5344AS–BDC–09/03 1 nF 2.200 mm 0.900 mm 0.900 mm 16.340 mm 0.900 mm 16.780 mm 16.610 mm 2.760 mm Figure 3. CQFP 196 On-package Capacitor Location 1 nF 2.760 mm 1 nF 2.200 mm 2.200 mm 2.760 mm 16.010 mm Note: 6 1 nF 2.760 mm 2.200 mm 0.900 mm The on-package decoupling capacitors are an option only. Their use will be confirmed after full characterization. TS81102G0FS 5344AS–BDC–09/03 TS81102G0FS Figure 4. Detailed Cross Section of DEMUX in CQFP196 Package Capacitor 0.8 mm thick (soldered on top) 127 µm Thick Lead (Ref) (230 µm Width) Lid 0.38 Thickness + 0.05 Solder 18.54 mm2 Lid, 16.51 mm2 Inner (0.381) 0.010 mm (0.10 x 3 + 0.20) 0.510 mm 0.200 mm ±0.150 mm 0.51 mm (0.50) CuW Heatspreader 2.620 mm Die: 0.380 1.90 ±0.20 mm (0.35 x 2) (0.20) 7.25˚ 2 22.86 mm 4˚ Overall Height 3.47 mm Ref/3.90 mm Max. 9.27 (Combo 18.54 SQ) 0.817 Seating Plane 19.4 mm Ref (38.8/2 mm tip-to-tip) All Dimensions in mm Lid 0.38 Thickness + 0.05 Solder 18.54 mm2 Lid, 16.51 mm2 Inner 127 µm Thick Lead (Ref) (230 µm Width) (0.381) 0.010 mm (0.10 x 3 + 0.20) CuW Heatspreader 0.510 mm 0.200 mm ±0.150 mm 0.51 mm (0.50) 22.86 mm2 2.620 mm Die: 0.380 1.90 ±0.20 mm (0.35 x 2) (0.20) 7.25˚ 4˚ Overall Height 3.05 mm Ref/3.40 mm Max. 9.27 (Combo 18.54 SQ) 0.817 Seating Plane 19.4 mm Ref (38.8/2 mm tip-to-tip) All Dimensions in mm Note: The on-package decoupling capacitors are an option only. Their use will be confirmed after full characterization of the packaged device. 7 5344AS–BDC–09/03 Figure 5. Thermal Characteristics Estimated Thermal Model For 196 CQFP-CuW DEMUX (Typical Values) Silicon Junction Silicon Die 7 x 7=49 mm2 heating zone = 3.5 x 3.5 mm2 = 0.95 W/cm/˚C 0.26˚C/Watt Silver Glass 0.31˚C/Watt = 0.2 W/cm/˚C Lid top 1.44˚C/Watt Al2O3 = 0.17 W/cm/˚C 0.3˚C/Watt Lid : Kovar = 0.17 W/cm/˚C 0.07˚C/Watt CuW Base = 1.8 W/cm/˚C CuW Base 2.3˚C/Watt CuW base Al2O3 0.6˚C/Watt Al2O3 3.0˚C/Watt 0.07˚C/Watt Thermal Interface (Customer) Bottom of Package 47.7 ˚C/Watt Kovar Leads 127 µm x 230 µm = 0.17 W/cm/˚C Bottom of Leads Board at Bottom of Package Board at Bottom of Leads Thermal Resistance Junction to bottom of case = 0.26 + 0.31 + 1.44 + 0.07 + 0.07 = 2.15˚C/Watt (customer thermal interface excluded) 8 TS81102G0FS 5344AS–BDC–09/03 TS81102G0FS Ordering Information Table 2. Ordering Information Part Number Package Temperature Range Screening TS81102G0CFS CQFP 196 “C” grade 0°C < Tc; Tj < 90°C Standard TS81102G0VFS CQFP 196 “V” grade -40°C < Tc; Tj < 110°C Standard TS81102G0MFS CQFP 196 “M” grade -55°C < Tc; Tj < 125°C Standard TS81102G0MFS9Nxy CQFP 196 “M” grade -55°C < Tc; Tj < 125°C ESA/SCC9000 screening Non ESA/SCC qualified x = B or C for respectively level B or C of ESA/SCC9000 y = 1, 2 or 3 for respectively Lot Acceptance Test 1, 2 or 3 Comments Please contact Marketing 9 5344AS–BDC–09/03 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. © Atmel Corporation 2003. All rights reserved. Atmel ® and combinations thereof are the registered trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others. Printed on recycled paper. 5344AS–BDC–09/03 0M