Features • Programmable DMUX Ratio: • • • • • • • • • • • • • • – 1:4: Data Rate Max = 1 Gsps – PD (8b/10b) < 4.3/4.7 W (ECL 50Ω output) – 1:8: Data Rate Max = 2 Gsps – PD (8b/10b) < 6/6.9 W (ECL 50Ω output) – 1:16 with 1 TS8388B or 1 TS83102G0B and 2 DMUX Parallel Output Mode 8-/10-bit ECL Differential Input Data DataReady or DataReady/2 Input Clock Input Clock Sampling Delay Adjust Single-ended Output Data: – Adjustable Common Mode and Swing – Logic Threshold Reference Output – (ECL, PECL, TTL) Asynchronous Reset Synchronous Reset ADC + DMUX Multi-channel Applications: – Stand-alone Delay Adjust Cell for ADCs Sampling Instant Alignment Differential Data Ready Output Built-in Self Test (BIST) Dual Power Supply VEE = -5V, VCC = +5V Radiation Tolerance Oriented Design (More than 100 Krad (Si) Expected) TBGA 240 (Cavity Down) Package DMUX 8-/10-bit 2 GHz 1:4/8 TS81102G0 Description The TS81102G0 is a monolithic 10-bit high-speed (up to 2 GHz) demultiplexor, designed to run with all kinds of ADCs and more specifically with Atmel’s high-speed ADC 8-bit 1 Gsps TS8388B and ADC 10-bit 2 Gsps TS83102G0B. The TS81102G0 uses an innovative architecture, including a sampling delay adjust and tunable output levels. It allows users to process the high-speed output data stream down to processor speed and uses the very high-speed bipolar technology (25 GHz NPN cut-off frequency). Rev. 2105C–BDC–11/03 1 Block Diagram Figure 1. Block Diagram FS/8 ADCDelAdjIn ADCDelAdjCtrl RatioSel SyncReset AsyncReset ClkIn (to be confirmed) RatioSel NbBit ClkInType DEMUXDelAdjCtrl Clock Path I[0..7/9] BIST SwiAdj VplusDOut VCC GND VEE DIODE Data Path delay delay NAP B2 mux BIST 8/10 mux Phase control 8/10 RstGen ClkPar even master latch odd master latch odd slave latch Counter (8 stage shift register) 8 Counter Status Latch Sel Even/Odd [1..8/10] 8 even slave latch FS/8 Port Selection Clock 8 8 Data Output Clock 1 Even Ports Odd Ports DataReady generation DR/DR ADCDelAdjOut A[0..7/9] RefA C[0..7/9] RefC E[0..7/9] RefE G[0..7/9] RefG B[0..7/9] RefB D[0..7/9] RefD F[0..7/9] RefF H[0..7/9] RefH 3 8/10 2 Reset TS81102G0 2105C–BDC–11/03 TS81102G0 Internal Timing Diagram This diagram corresponds to an established operation of the DMUX with Synchronous Reset. Figure 2. Internal Timing Diagram 500 ps min Data In N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N+10 N+11 N+12 N+13 N+14 N+15 N+16 N+17 N+18 N+19 N+20 N+21 N+22 N+23 N+24 N+25 N+26 N+27 N+28 N+29 N+30 N+31 DR In = Fs DR/2 In = Fs/2 = ClkPar Master Even Latch Master Odd Latch Slave Even Latch Slave Odd Latch N N+2 N+4 N+3 N+1 N N+5 N+2 N+1 N+6 N+7 N+4 N+3 N+8 N+9 N+6 N+5 N+10 N+11 N+8 N+7 N+12 N+13 N+10 N+9 N+14 N+15 N+12 N+11 N+16 N+17 N+14 N+13 N+18 N+19 N+16 N+15 N+20 N+21 N+18 N+17 N+22 N+23 N+20 N+19 N+24 N+25 N+22 N+21 N+26 N+27 N+24 N+23 N+28 N+29 N+26 N+25 N+30 N+31 N+28 N+27 N+30 N+29 Synchronous reset = Fs/8 Internal reset pulse Port Select A Port Select B Port Select C Port Select D Port Select E Port Select F Port Select G Port Select H Latch Select A Latch Select B Latch Select C Latch Select D Latch Select E Latch Select F Latch Select G Latch Select H N N+8 N+1 N+16 N+9 N+2 N+17 N+10 N+3 N+27 N+20 N+13 N+6 N+26 N+19 N+12 N+5 N+25 N+18 N+11 N+4 N+24 N+21 N+14 N+22 N+7 N+15 N+23 N to N+7 N+8 to N+15 N+16 to N+23 A to H Port Out A to H LatchOut DROut 3 2105C–BDC–11/03 Functional Description The TS81102G0 is a demultiplexer based on an advanced high-speed bipolar technology featuring a cutoff frequency of 25 GHz. Its role is to reduce the data rate so that the data can be processed at the DMUX output. The TS81102G0 provides 2 programmable ratios: 1:4 and 1:8. The maximum data rate is 1 Gsps for the 1:4 ratio and 2 Gsps for the 1:8 ratio. The TS81102G0 is able to process 8 or 10-bit data flows. The input clock can be an ECL differential signal or single-ended DC coupled signal. Moreover it can be a DataReady or DataReady/2 clock. The input digital data must be an ECL differential signal. The output signals (Data Ready, digital data and reference voltage) are adjustable with VplusD independent power supply. Typical output modes are ECL, PECL or TTL. The Data Ready output is a differential signal. The digital output data and reference voltages are single-ended signals. The TS81102G0 is started by an Asynchronous Reset. A Synchronous Reset enables the user to re-synchronize the output port selection and to minimize loss of data that could occur within the DMUX. A delay adjust cell is available to ensure a good phase between the DMUX’ input clock and input data. Another delay adjust cell is available to control the ADCss sampling instant alignment, in case of the ADCs interleaving. A 10-bit generator is implemented in the TS81102G0, the Built-In Self Test (BIST). This test sequence is very useful for testing the DMUX at first use. A fine tuning of the output swing is also available. The TS81102G0 can be used with the following Atmel ADCs: 4 • TS8388B(F/FS/GL), 8-bit 1 Gsps ADC • TS83102G0B, 10-bit 2 Gsps ADC TS81102G0 2105C–BDC–11/03 TS81102G0 Main Function Description Programmable DMUX Ratio The conversion ratio is programmable: 1:4 or 1:8. Figure 3. Programmable DMUX Ratio Input Words: Output Words: 1,2,3,4,5,6,7,8,... PortA PortB 1 5 2 6 PortC 3 7 8 1:4 PortD 4 PortE not used PortF not used PortG not used PortH not used Input Words: Output Words: 1,2,3,4,5,6,7,8,... PortA PortB 1 2 9 ... 10 PortC 3 11 PortD 4 12 PortE 5 13 PortF 6 14 PortG 7 15 PortH 8 16 1:8 Parallel Output Mode ... Figure 4. Parallel Mode ClkIn DR PortA N PortB N+1 PortC N+2 PortD N+3 PortE N+4 PortF N+5 PortG N+6 PortH N+7 Input Clock Sampling Delay Adjust (DEMUXDELADJCTRL) The input clock phase can be adjusted with an adjustable delay (from 250 to 750 ps). This is to ensure a proper phase between the clock and input data of the DMUX. 5 2105C–BDC–11/03 Asynchronous Reset (ASYNCRESET) Figure 5. Asynchronous Reset CLKIN AsyncReset Port A selected Port B selected Port C selected Port D selected Port E selected Port F selected Port G selected Port H selected The Asynchronous Reset is a master reset of the port selection, which works on TTL levels. It is active on the high level. During an asynchronous reset, the clock must be in a known state. It is used to start the DMUX. When it is active, it paralyzes the outputs (the output clock and output data remain at the same level as before the asynchronous reset). When it comes back to its low level, the DMUX starts: the outputs are active and the first processed data is on port A. Synchronous Reset (SYNCRESET) Figure 6. Synchronous Reset FS DR/2 SyncReset = FS/8 Internal reset pulse Port A selected Port B selected Port C selected Port D selected Port E selected Port F selected Port G selected Port H selected The DMUX can be synchronously reset to a programmable state depending on the conversion ratio. The clock must not be stopped during reset. The synchronization signal is a clock (SyncRest) whose frequency is FS/8*n where n is an integer (n = 1,2,3,…) in 1:8 mode and FS/4*n in 1:4 mode. The front edge of this clock is synchronized with Clkln inside the DMUX, and generates a 200 ps reset pulse. This reset pulse occurs during a fixed level of Clkln. If the DMUX was synchronized with Syncreset previous to a possible loss of synchronization, then the output data is immediately correct, no modification can be seen at the output of the DMUX, and no data is lost (“Internal Timing Diagram” on page 3). If the DMUX was not synchronized with SyncReset previous to a possible loss of synchronization, then the output data and data ready of the DMUX are changed. The output data is correct after a number of input clocks corresponding to the pipeline delay (“Timing Diagrams with Synchronous Reset” on page 19). 6 TS81102G0 2105C–BDC–11/03 TS81102G0 Counter Programmable State When the counter is reset, its initial states depends on the conversion ratio: Pipeline Delay The maximum pipeline delay depends on the conversion ratio: • 1:8: counting on 8 bits, • 1:4: counting on 4 bits. • 1:8: pipeline delay = 7 • 1:4: pipeline delay = 3 8-/10-bit, with NAP Mode for the 2 Unused Bit The DMUX is a 10-bit parallel device. The last two bits (bits 8 and 9) may not be used, and the corresponding functions are set to nap mode to reduce power consumption. ECL Differential Input Data Input data are ECL compatible (Voh = -0.8V, Vol = -1.8V). The minimum swing required is 100 mV differential. All inputs have a 100Ω differential termination resistor. The middle point of these resistors is connected to ground through a 10 pF capacitor. Figure 7. ECL Differential Input Data Gnd ClkIn ClkInb 50Ω 50Ω 10 pF 50Ω Differential Output Data The output clock for the ADC is generated through a 50Ω loaded long tailed. The 50Ω resistor is connected to the ground pad via a diode. The levels are (on the 100Ω differential termination resistor): Vol = -1.4V, Voh = -1.0V. Figure 8. 50Ω Differential Output Data ADCDelAdjOut 50Ω 50Ω Gnd ADCDelAdjOutb 7 2105C–BDC–11/03 Single-ended Output Data To reduce the pin number and power consumption of the DMUX, the eight output ports are single-ended. To reach the high frequency output (up to 250 MHz) with a reasonable power consumption, the swing must be limited to a maximum of ±500 mV. The common mode is adjustable from -1.3V to +2V, with Vplus DOut pins. To ensure better noise immunity, a reference level (common mode) is available (one level by output port). The output buffers are of ECL type (open emitters – not resistive adapted impedances). They are designed for a 15 mA average output current, and may be used with a 50Ω termination impedance. Figure 9. Single-ended Output Data VPlusDOut PadOut Vee Following are three application examples for these buffers: ECL/PECL/TTL. Please note that it is possible to have any other odd output format as far as current (36 mA max) and voltage (Vplus Dout – VEE ≤ 8.3V) limits are not overridden. The maximum frequency in TTL output mode depends on the load to be driven. Table 1. Examples of Application of Buffers Parameter ECL PECL TTL Unit VplusDout 0 3.3 3.3 V Vtt -2 1.3 0 V Swing ±0.5 ±0.5 ±1 V Reference -1.3 2 1.5 V Voh -0.8 2.5 2.5 V Vol -1.8 1.5 0.5 V Load 50 50 ≥75 Ω Average Output Current 14 14 15 mA Output Data rate max. 250 250 250 Msps This corresponds to the “Adjustable Logic Single” in the pinout description. The “Adjustable Single” buffers for reference voltage are the same buffers, but the information available at the output of these buffers is more like analog than logic. Note: 8 The Max Output Data Rate is given for a typical 50Ω/2 pF load. TS81102G0 2105C–BDC–11/03 TS81102G0 Differential Data Ready Output The front edge of the DataReady output occurs when data is available on the corresponding port. The frequency of this clock depends on the conversion ratio (1:8 or 1:4), with a duty cycle of 50%. The definition is the same as for single-ended output data, but the buffers are differential. This corresponds to the “Adjustable Logic Differential” in the pinout description. Built-in Self Test (BIST) A pseudo-random 10-bit generator is implemented in the DMUX. It generates a 10-bit signal in the output of the DMUX, with a period of 512 input clocks. The probability of occurrence of codes is uniformly spread over the 1024 possible codes: 0 or 1/1024. Note that the 256 codes of bits 1 to 8 occur at least once. They start with a BIST command, in phase with the FS/8 clock on Port A. The logic output obtained on the A to H ports depends on the conversion ratio. The driving clock of BIST is Clkln. The ClklnType must be set to ‘1’ (DataReady ADC clock) to have a different 10-bit code on each output. The complete BIST sequence is available on request. Specifications Absolute Maximum Ratings Table 2. Absolute Maximum Ratings Parameter Symbol Positive supply voltage Comments Value Unit VCC GND to 6 V Positive output buffer supply voltage VPLUSD GND to 4 V Negative supply voltage VEE GND to -6 V Analog input voltages ADCDelAdjCtrl, ADCDelAdjCtrlb or DMUXDelAdjCtrl, DMUXDelAdjCtrlb or SwiAdj Voltage range for each pad -1 to +1 V Differential voltage range -1 to +1 ECL 50Ω input voltage Clkln or Clklnb or I[0…9] or I[0…9]b or SyncReset or SyncResetb or ADCDelAdjln or ADCDelAdjlnb Voltage range for each pad Maximum difference between ECL 50Ω input voltages Clkln – Clklnb or I[0…9] - I[0…9]b or SyncReset – Syncresetb or ADCDelAdjln ADCDelAdjlnb -2.2 to +0.6 V Minimum differential swing 0.1 V Maximum differential swing 2 9 2105C–BDC–11/03 Table 2. Absolute Maximum Ratings (Continued) Parameter Symbol Comments Value Unit Data output current A[0…9] to H[0…9] or RefA to RefH or DR or DRb Maximum current 36 mA TTL input voltage Clkln Type RatioSel NbBit AsyncReset BIST GND to VCC V Maximum input voltage on diode for temperature measurement DIODE 700 mV Maximum input current on diode DIODE 8 mA Maximum junction temperature Tj 135 °C Storage temperature Tstg -65 to 150 °C Note: Absolute maximum ratings are limiting values, to be applied individually, while other parameters are within specified operating conditions. Long exposure to maximum rating may affect device reliability. The use of a thermal heat sink is mandatory. See “Thermal and Moisture Characteristics” on page 26. Recommended Operating Conditions Table 3. Recommended Operating Conditions Recommended Value Parameter Symbol Positive supply voltage VCC Positive output buffer supply voltage VPLUSD Positive output buffer supply voltage Min Typ Max Unit 4.45 5 5.25 V ECL output compatibility – 0 – V VPLUSD PECL output compatibility – 3.3 – V Positive output buffer supply voltage VPLUSD TTL output compatibility – 3.3 – V Negative supply voltage VEE -5.25 -5 -4.75 V Operating temperature range TJ 10 Comments Commercial grade: “C” Industrial grade: “V” 0 < Tc; Tj < 90 -40 < Tc; Tj < 110 °C TS81102G0 2105C–BDC–11/03 TS81102G0 Electrical Operating Characteristics Tj (typical) = 70°C. Full Temperature Range: -40°C < Tc; Tj < 110°C. (Guaranteed temperature range are depending on part number) Table 4. Electrical Specifications Parameter Symbol Test Level Value Min Typ Max Unit 5 – 0 3.3 3.3 5.25 – 0.25 3.465 3.465 V – V V V -5 -4.75 V Note Power Requirements Positive supply voltage VCC VPLUSDOUT ECL PECL TTL VCC – VPLUSD VPLUSD VPLUSD 1 4.75 – -0.25 3.135 3.135 VEE 1 -5.25 Negative supply voltage VEE (1) Supply Currents ECL (50Ω) and PECL (50Ω) VCC (for every configuration) 1:8, 8 bits 1:8, 10 bits 1:4, 8 bits 1:4, 10 bits TTL (75Ω) VCC (for every configuration) 1:8, 8 bits 1:8, 10 bits 1:4, 8 bits 1:4, 10 bits ICC IPLUSD IEE IPLUSD IEE IPLUSD IEE IPLUSD IEE ICC IPLUSD IEE IPLUSD IEE IPLUSD IEE IPLUSD IEE 1 – 540 – 640 – 270 – 320 – 31 1180 719 1140 790 590 592 720 634 – 1820 – 2240 – 910 – 1120 – mA mA mA mA mA mA mA mA mA 1 – 760 – 900 – 380 – 450 – 31 1610 872 1770 980 810 670 880 729 – 2440 – 3010 – 1220 – 1510 – mA mA mA mA mA mA mA mA mA (1) Nominal power dissipation ECL (50Ω) 1:8, 8 bits 1:8, 10 bits 1:4, 8 bits 1:4, 10 bits PD PD PD PD 1 5.2 5.9 3.9 4.2 5.6 6.4 4.1 4.5 6 6.9 4.3 4.7 W W W W 11 2105C–BDC–11/03 Table 4. Electrical Specifications (Continued) Parameter Symbol PECL (50Ω) 1:8, 8 bits 1:8, 10 bits 1:4, 8 bits 1:4, 10 bits PD PD PD PD TTL (75Ω) 1:8, 8 bits 1:8, 10 bits 1:4, 8 bits 1:4, 10 bits PD PD PD PD Test Level Value Min Typ Max Unit 1 5.8 6.6 4.2 4.6 6.2 7.1 4.4 4.8 6.6 7.6 4.6 5.1 W W W W 1 6.8 7.8 4.7 5.2 7.3 8.4 4.9 5.5 7.7 9 5.1 5.8 W W W W – – – – – – – -0.5 0 0.5 – – – – – – V V V mA – – – – – – – -0.5 0 0.5 – – – – – – V V V mA Note Delay Adjust Control DMUXDelAdjCtrl differential voltage 250 ps 500 ps 750 ps Input current ADCDelAdjCtrl differential voltage 250 ps 500 ps 750 ps Input current DDAC IDDAC ADAC IADAC Digital Outputs ECL Output (assuming VPLUSD = 0V, SWIADJ = 0V, 50Ω termination resistor on board) Logic “0” voltage Logic “1” voltage Reference voltage VOL VOH VREF 1 – – – -2.12 -1.16 -1.40 – – – V V V PECL Output (assuming VPLUSD = 3.3V, SWIADJ = 0V, 50Ω termination resistor on board) Logic “0” voltage Logic “1” voltage Reference voltage VOL VOH VREF 1 – – – 1.27 2.44 1.83 – – – V V V TTL Output (assuming VPLUSD = 3.3V, SWIADJ = 0V, 75Ω termination resistor on board) Logic “0” voltage Logic “1” voltage Reference voltage VOL VOH VREF 1 – – – 0.9 2.31 1.2 – – – V V V – – – -1.3 – mV/°C Output level drift with temperature (data and DR outputs) 12 TS81102G0 2105C–BDC–11/03 TS81102G0 Table 4. Electrical Specifications (Continued) Parameter Output level drift with temperature (reference outputs) Value Symbol Test Level Min Typ Max Unit – 1 – -0.9 – mV/°C VIL VIH 1 – -1.1 – – -1.4 – V V Note Digital Inputs ECL Input Voltages Logic “0” voltage Logic “1” voltage TTL Input Voltages – – 0.8 Logic “0” voltage VIL 1 VIH 2.0 – – Logic “1” voltage Note: 1. The supply current IPLUSD and the power dissipation depend on the state of the output buffers: - the minimum values correspond to all the output buffers at low level, - the maximum values correspond to all the output buffers at high level, - the typical values correspond to an equal sharing-out of the output buffers between high and low levels. Switching Performance and Characteristics V V 50% clock duty cycle (CLKIN, CLKINB). Tj (typical) = 70°C. Full temperature range: -40°C < Tc; Tj < 110°C. (Guaranteed temperature ranges depend on the part number) See Timing Diagrams Figure 10 on page 16 to Figure 19 on page 21. Table 5. Switching Performances Symbol Test Level FMAX Clock pulse width (high) Clock pulse width (low) Parameter Value Min Typ Max Unit – 2 1 – – 2.2 1.1 GHz TC1 – 100 – – ps TC2 – 100 – – ps TCPD TCPD – – – 981 1084 – – ps ps Note Input Clock Maximum clock frequency 1:8 ratio 1:4 ratio Clock Path pipeline delay DR input clock DR/2 input clock Clock rise/fall time TRCKIN TFCKIN – – 100 – ps Asynchronous Reset pulse width PWAR – 1000 – – ps Setup time from Asynchronous to Clkln TSAR – – 1500 – ps Rise/fall time for (10% – 90%) TRAR TFAR – 1000 – – ps (1) (2) Asynchronous Reset 13 2105C–BDC–11/03 Table 5. Switching Performances (Continued) Symbol Test Level Setup time from SyncReset to Clkln DR input clock DR/2 input clock TSSR – Hold time from Clkln to SyncReset DR input clock DR/2 input clock THSR Parameter Value Min Typ Max Unit Note – – -580 -477 – – ps ps (3) – – 780 677 – – ps ps (5) Synchronous Reset Rise/fall for (10% – 90%) – (4) (6) TSRR/TFSR – 100 – – ps Setup time from I[0…9] to Clkln DR input clock DR/2 input clock TSCKIN – – – -794 -691 – – ps ps (7) Hold time from Clkln to I[0…9] DR input clock DR/2 input clock THCKIN – – 994 891 – – ps ps (9) Input Data Rise/fall for (10% – 90%) – (8) (10) TRDI/TFDI – 100 – – ps Data output delay DR input clock DR/2 input clock TOD – – – 1820 1717 – – ps ps (11) Data pipeline delay DR input clock, 1:4 ratio DR input clock, 1:8 ratio DR/2 input clock, 1:4 ratio DR/2 input clock, 1:8 ratio TPD – – – – – 3 7 3/2 7/2 – – – – Number of input clock (13) TROD/tfod – – 497/484 – ps (14) Data ready Falling edge DR input clock DR/2 input clock TDRF – – – 1856 1753 – – ps ps (15) Data ready Rising edge DR input clock DR/2 input clock TDRR – – 1828 1725 – – ps ps (17) Asynchr; Reset to DataReady delay TARDR – – 1918 – ps (19) Synchr. Reset to DataReady delay TSRDR – – 1037 – ps (20) Rise/fall for (10% – 90%) TRDR/TFDR – – 450 – ps (21) Rising edge uncertainty JITTER – – 62 – ps THBIST – – – – ps Output Data Rise/fall for (10% – 90%) (12) Data Ready – (16) (18) Built-In Self Test Hold time from Clkln to BIST 14 (22) TS81102G0 2105C–BDC–11/03 TS81102G0 Table 5. Switching Performances (Continued) Value Parameter Symbol Test Level Setup time from Bist to Clkln TSBIST – – 1000 – ps Rise/fall time for (10% – 90%) TRBIST/ TFBIST – 1000 – – ps Input frequency FMADA – 2 – 2.2 GHz Input pulse width (high) TC1ADA – 90 – – ps Input pulse width (low) TC2ADA – 90 – – ps Input rise/fall time TRIADA/ TFIADA – 100 100 150 150 – – ps Output rise/fall time TROADA/ TFOADA – – – 145 104 – – ps TADA – – – 784 896 – – ps TADAT – – 2.5 – ps/°C Min Typ Max Unit Note ADC Delay Adjust Data output delay (typical delay adjust setting) Output delay drift with temperature (23) (24) (25) Output delay uncertainly JITADA – – 30 – ps Notes: 1. TCPD is tuned with DMUXDelAdjCtrl: TCPD = 981 ± 250 ps. 2. TCPD is tuned with DMUXDelAdjCtrl: TCPD = 1084 ± 250 ps. 3. TSSR depends on DMUXDelAdjCtrl: TSSR = -580 ± 250 ps. TSSR < 0 because of Clock Path internal delay. 4. TSSR depends on DMUXDelAdjCtrl: TSSR = -477 ± 250 ps. TSSR < 0 because of Clock Path internal delay. 5. THSR depends on DMUXDelAdjCtrl: THSR = 780 ± 250 ps. 6. THSR depends on DMUXDelAdjCtrl: THSR = 677 ± 250 ps. 7. TSCKIN depends on DMUXDelAdjCtrl: TSCKIN = -794 ± 250 ps. TSCKIN < 0 because of Clock Path internal delay. 8. TSCKIN depends on DMUXDelAdjCtrl: TSCKIN = -691 ± 250 ps. TSCKIN < 0 because of Clock Path internal delay. 9. THCKIN depends on DMUXDelAdjCtrl: THCKIN = 994 ± 250 ps. 10. THCKIN depends on DMUXDelAdjCtrl: THCKIN = 891 ± 250 ps. 11. TOD depends on DMUXDelAdjCtrl: TOD = 1820 ± 250 ps. TOD is given for ECL 50Ω/2 pFoutput load. 12. TOD depends on DMUXDelAdjCtrl: TOD = 1717 ± 250 ps. TOD is given for ECL 50Ω/2 pFoutput load. 13. TPD is the number of Clkln clock cycle from selection of Port A to selection of Port H in 1:8 conversion mode, and from selection of Port A to selection of Port D in 1:4 conversion mode. It is the maximum number of Clkln clock cycle, or pipeline delay, that a data has to stay in the DMUX before being sorted out. This maximum delay occurs for the data sent to Port A. For instance, the data sent to Port H goes directly from the input to the Port H, and its pipeline is 0. But even for this data, there is an additional delay due to physical propagation time in the DMUX. 14. TROD and TFOD are given for ECL 50Ω/2 pF output load. In TTL mode, the TROD and TFOD are twice the ones for ECL. (For other termination topology, apply proper derating value 50 ps/pF in ECL, 100 ps/pF in TTL mode.) 15. TDRF depends on DMUXDelAdjCtrl: TDRF = 1856 ± 250 ps. It is given for ECL 50Ω/2 pF output load. 16. TDRF depends on DMUXDelAdjCtrl: TDRF = 1753 ± 250 ps. It is given for ECL 50Ω/2 pF output load. 17. TDRR depends on DMUXDelAdjCtrl: TDRR = 1858 ± 250 ps. It is given for ECL 50Ω/2 pF output load. 18. TDRR depends on DMUXDelAdjCtrl: TDRR = 1725 ± 250 ps. It is given for ECL 50Ω/2 pF output load. 19. TARDR is given for ECL 50Ω/2 pF output load. 20. TSRDR is given for ECL 50Ω/2 pF output load. It is minimum value since RstSync clock is synchronized with Clkln clock. 21. TRDR and TFDR are given for ECL 50Ω/2 pF output load. 22. THBIST depends on the configuration of the DMUX. There must be enough Clkln clock cycles to have all the 512 codes, (see different Timing Diagrams). 23. With transmission line (ZO = 50Ω) and output load R = 50Ω; C = 2 pF. 24. Without output load. 25. With transmission line (ZO = 50Ω) and output load R = 50Ω; C = 2 pF. 15 2105C–BDC–11/03 Input Clock Timings Figure 10. Input Clock TC2 TC2 TFCKIN TFCKIN TC1 TC1 TRCKIN TRCKIN Clkln TSCKIN Data [0..9] d1 d2 TSCKIN THCKIN d3 d4 d5 d1 Clkln Type = 1 DataReady Mode (DR) d2 THCKIN d3 d4 d5 Clkln Type = 0 DataReady/2 Mode (DR/2) ADC Delay Adjust Timing Diagram Figure 11. ADC Delay Adjust Timing Diagram TC2ADA TFIADA TC1ADA TRIADA ADCDelAdjIn TADA TFOADA TROADA ADCDelAdjOut 16 TS81102G0 2105C–BDC–11/03 TS81102G0 Timing Diagrams with Asynchronous Reset With a nominal tuning of DMUXDelAdj at a frequency of 2 GHz, d1 and d2 data is lost because of the internal clock’s path propagation delay TCPD. TCPD is tuned with DMUXDelAdjCtrl pins to obtain good setup and hold times between Clkln and the data. Figure 12. Start with Asynchronous Rest, 1:8 Ratio, DR Mode TRAR TFAR PWAR ASyncReset TPD Clkn TCPD Internal Port Selection (not available out of the DEMUX) A I[0..9] B d1 d2 d3 C d4 D d5 E d6 F d7 G d8 H d9 A d10 B C D d11 d12 d13 E d14 F d15 TOD G d16 H d17 TOD d10 A[0..9] B[0..9] d3 d11 C[0..9] d4 d12 D[0..9] d5 d13 E[0..9] d6 d14 F[0..9] d7 d15 G[0..9] d8 d16 TROD/TFOD H[0..9] d9 TARDR d17 TRDR TDRF TDRR TFDR DR With a nominal tuning of DMUXDelAdj at 2 GHz, d1 and d2 data is lost because of the internal clock’s path propagation delay TCPD. TCPD is tuned with DMUXDelAdjCtrl pins to obtain good setup and hold times between Clkln and the input data. This timing diagram does not change with the opposite phase of Clkln. Figure 13. Start with Asynchronous Rest, 1:8 Ratio, DR/2 Mode TRAR TFAR PWAR ASyncReset TPD Clkn TCPD Internal Port Selection (not available out of the DEMUX) A I[0..9] TCPD B d1 d2 d3 C d4 D d5 E d6 F d7 G d8 H d9 A d10 B C D d11 d12 d13 TOD E d14 F d15 G d16 H d17 TOD d10 A[0..9] B[0..9] d3 d11 C[0..9] d4 d12 D[0..9] d5 d13 E[0..9] d6 d14 F[0..9] d7 d15 G[0..9] d8 d16 TROD/TFOD H[0..9] d9 TARDR TDRR TDRF TRDR d17 TFDR DR 17 2105C–BDC–11/03 With a nominal tuning of DMUXDelAdj, at 1 GHz (1:4 mode) d1 data is lost because of the internal clock’s path propagation delay TCPD. TCPD is tuned with DMUXDelAdjCtrl pins and is used to obtain good setup and hold times between Clkln and the input data. Figure 14. Start with Asynchronous Reset, 1:4 Ratio, DR Mode TRAR TFAR PWAR ASyncReset TPD Clkn TCPD Internal Port Selection (not available out of the DEMUX) A I[0..9] d1 B d2 C D d3 A d4 B d5 C d6 D d7 d8 TOD TOD d5 A[0..9] B[0..9] d2 d6 C[0..9] d3 d7 d4 d8 D[0..9] TARDR TDRF TDRR TDRR TROD/TFOD DR TRDR TFDR With a nominal tuning of DMUXDelAdj, at 1 GHz (1:4 mode) d1 data is lost because of the internal clock’s path propagation delay TCPD. TCPD is tuned with DMUXDelAdjCtrl pins and is used to obtain good setup and hold times between Clkln and the input data. This timing diagram does not change with the opposite phase of Clkln. Figure 15. Start with Asynchronous Reset, 1:4 Ratio, DR/2 Mode TRAR TFAR PWAR ASyncReset TPD Clkn TCPD Internal Port Selection (not available out of the DEMUX) TCPD A d1 I[0..9] C B d2 D d3 d4 A B d5 d6 C d7 d8 TOD TOD d5 A[0..9] B[0..9] d2 d6 C[0..9] d3 d7 d4 d8 D[0..9] TARDR TDRR TDRF TROD/TFOD DR TRDR 18 TFDR TS81102G0 2105C–BDC–11/03 TS81102G0 Timing Diagrams with Synchronous Reset Following is an example of the Synchronous Reset’s utility in case of de-synchronization of the DMUX output port selection. The de-synchronization event happens after the selection of Port D. DMUXDelAdjCtrl value is nominal. TSSR < 0 because of Clkln’s internal propagation delay TCPD. After selection of Port C, instead of selecting Port D, the de-synchronization makes the port selection to restart on Port A. Since Port H was not selected, the data is not output to the ports but the last data (d1 to d8) is latched until the next selection of Port H. d9 to d16 are lost. The synchronous Reset ensures a re-synchronization of the port selection. Figure 16. Synchronous Reset, 1:8 Ratio, DR Mode THSR THSR THSR SyncReset TSSR TSSR TSSR Clkn I[0..9] d0 d1 Internal Port Selection A (not available out of the DEMUX) A[0..9] B d2 d3 d4 d5 d6 d7 TCPD d8 C D E F G H TOD A d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 TCPD B C A B C D E A B C D E F G H TOD A B C d1 d17 B[0..9] d2 d18 C[0..9] d3 d19 d4 d20 d5 d21 d6 d22 d7 d23 D[0..9] E[0..9] F[0..9] G[0..9] H[0..9] TDRR TDRF d8 TSRDR D d24 TDRR TDRF DR Period of uncertainty due to desynchronization Example of the Synchronous Reset’s utility in case of de-synchronization of the DMUX output port selection. The de-synchronization event happens after the selection of Port D. DMUXDelAdjCtrl value is nominal. TSSR < 0 because of Clkln’s internal propagation delay TCPD. After selection of Port C, instead of selecting Port D, the de-synchronization makes the port selection to restart on Port A. Since Port H was not selected, the data is not output to the ports but the last data (d1 to d4) is latched until the next selection of Port H. d5 to d8 are lost. The synchronous Reset ensures a re-synchronization of the port selection. 19 2105C–BDC–11/03 Figure 17. Synchronous Reset, 1:4 Ratio, DR Mode THSR SyncReset TSSR Clkn TCPD I[0..9] d1 d2 Internal Port Selection (not available out of the DEMUX) d3 B C d4 d5 D A d6 d7 B C d8 d9 D d10 A B d11 d12 C D d13 d14 A B d16 d15 C D TOD A[0..9] d1 d9 B[0..9] d2 d10 C[0..9] d3 d11 D[0..9] d4 d12 TDRF TDRR DR Period of uncertainty due to desynchronization Example of Synchronous Reset’s utility in case of de-synchronization of the DMUX output port selection. The de-synchronization event happens after the selection of Port D. DMUXDelAdjCtrl value is nominal. TSSR < 0 because of Clkln’s internal propagation delay TCPD. After selection of Port C, instead of selecting Port D, the de-synchronization makes the port selection to restart on Port A. Since Port H was not selected, the data is not output to the ports but the last data (d1 to d8) is latched until the next selection of Port H. d9 to d16 are lost. The synchronous Reset ensures a re-synchronization of the port selection. Figure 18. Synchronous Reset, 1:8 ratio, DR/2 Mode THSR THSR THSR SyncReset I[0..9] TSRR TSSR Clkn d0 Internal Port Selection (not available out of the DEMUX) A d1 B d2 C d3 D d4 d5 E TOD F d6 d7 TCPD G H d8 A d9 B d10 d11 d12 d13 C A B C TSRR d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 TCPD D E A B C D E F G H A B C D TOD A[0..9] d1 d17 B[0..9] d2 d18 C[0..9] d3 d19 D[0..9] d4 d20 E[0..9] d5 d21 F[0..9] d6 d22 G[0..9] d7 d23 H[0..9] TDRF d8 TSDRR d24 TDRR TDRF DR Period of uncertainty due to desynchronization Example of Synchronous Reset’s utility in case of de-synchronization of the DMUX output port selection. The de-synchronization event happens after the selection of Port D. DMUXDelAdjCtrl value is nominal. TSSR < 0 because of Clkln’s internal propagation delay TCPD. After selection of Port C, instead of selecting Port D, the de-synchronization makes the port selection to restart on Port A. Since Port H was not selected, the data is not output to the ports but the last data (d1 to d4) is latched until the next selection of Port H. d5 to d8 are lost. The synchronous Reset ensures a re-synchronization of the port selection. 20 TS81102G0 2105C–BDC–11/03 TS81102G0 Figure 19. Synchronous Reset, 1:4 ratio, DR/2 Mode THSR SyncReset TSSR Clkn I[0..9] d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d12 d11 d13 d14 d15 d16 TCPD Internal Port Selection (not available out of the DEMUX) B C D A B C A A B C D A B C D TOD A[0..9] d1 B[0..9] d2 C[0..9] d3 D[0..9] d4 d9 d10 d11 d12 TDRF TDRR DR Period of uncertainty due to desynchronization Note: In case of low clock frequency and start with asynchronous reset, only the first data is lost and the first data to be processed is the second one. This data is output from the DMUX through port B. 21 2105C–BDC–11/03 Explanation of Test Levels Table 6. Explanation of Test Levels Num 1 100% production tested at +25°C.(1) 2 100% production tested at +25°C, and sample tested at specified temperatures.(1) 3 Sample tested only at specified temperatures. 4 Parameter is guaranteed by design and characterization testing (thermal steady-state conditions at specified temperature). 5 Parameter is a typical value only. Notes: 22 Characteristics 1. The level 1 and 2 tests are performed at 50 MHz. 2. Only MIN and MAX values are guaranteed (typical values are issuing from characterization results). TS81102G0 2105C–BDC–11/03 TS81102G0 Package Description Pin Description Table 7. TS81102G0 Pin Description Type Name Levels Comments Digital Inputs I[0…9] Differential ECL Data input. On-chip 100Ω differential termination resistor. Clkln Differential ECL Clock input (Data Ready ADC). On-chip 100Ω differential termination resistor. A[0…9] → H[0…9] Adjustable Logic Single Data ready for port A to H. Common mode is adjusted with VplusDOut. Swing is adjusted with SwiAdj. 50Ω termination possible. DR Adjustable Logic Differential Data ready for channel A to H. Common mode is adjusted with VplusDOut. Swing is adjusted with SwiAdj. 50Ω termination possible. RefA → RefH Adjustable Single Reference voltage for output channels A to H. Common mode is adjustable with VplusDOut. 50Ω termination possible. ClklnType TTL DataReady or Dataready/2: logic 1: Data Ready. RatioSel TTL DMUX ratio; logic 1: 1:4 Bist TTL Reset and Switch of built-in Self Test (BIST): logic 0: BIST active. SwiAdj 0V ± 0.5V Swing fine adjustment of output buffers. Diode Analog Diode for chip temperature measurement. NbBit TTL Number of bit 8 or 10: logic 1: 10-bit. AsyncReset TTL Asynchronous reset: logic 1: reset on. SyncReset Differential ECL Synchronous reset: active on rising edge. DMUXDelAdjCtrl Differential analog input of ±0.5V around 0V common mode Control of the delay line of DataReady input: differential input = -0.5V: delay = 250 ps differential input = 0V: delay = 500 ps differential input = 0.5V: delay = 750 ps ADCDelAdjCtrl Differential analog input of ±0.5V around 0V common mode Control of the delay line for ADC: differential input = - 0.5V: delay = 250 ps differential input = 0V: delay = 500 ps differential input = 0.5V: delay = 750 ps ADCDelAdjln Differential ECL Stand-alone delay adjust input for ADC. Differential termination of 100Ω inside the buffer. ADCDelAdjOut 50Ω differential output Stand-alone delay adjust output for ADC. GND Ground 0V Common ground. VEE Power -5V Digital negative power supply. VPlusDOut Adjustable power from 0V to +3.3V Common mode adjustment of output buffers. VCC Power +5V Digital positive power supply. Outputs Control Signals Synchronization Power Supplies 23 2105C–BDC–11/03 TBGA 240 Package – Pinout Row A A A A A A A A A A A A A A A A A A A B B B B B B B B B B B B B B B B B B B C C C C C C C C C C C C C C C C C C C D D D 24 Col 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 3 Name NC E3 E5 E7 E9 C0 C2 C4 C6 C8 REFA A1 A3 A5 A7 A9 DEMUXDELADJCTRL RSTSYNCB NC E1 E2 E4 E6 E8 REFC C1 C3 C5 C7 C9 A0 A2 A4 A6 A8 ASYNCRESET DEMUXDELADJCTRLB RSTSYNC REFE E0 VEE VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VPLUSDOUT VPLUSDOUT GND GND GND DIODE G8 G9 VEE Row D D D D D D D D D D D D D D D D E E E E E E E E F F F F F F F F G G G G G G G G H H H H H H H H J J J J J J J J K K K K Col 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 Name VEE VEE VPLUSDOUT VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT GND VCC VCC GND I0B I0 G6 G7 VPLUSDOUT VEE VEE VEE I1B I1 G4 G5 GND GND GND GND I2B I2 G2 G3 VEE VEE VEE VEE I3B I3 G0 G1 GND GND GND GND CLKINB CLKIN DR REFG VPLUSDOUT VCC VEE VEE I4B I4 SWIADJ DRB VEE VEE Row K K K K L L L L L L L L M M M M M M M M N N N N N N N N P P P P P P P P R R R R R R R R T T T T T T T T T T T T T T T T Col 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name VEE GND I5B I5 H9 RATIOSEL VPLUSDOUT VPLUSDOUT VEE VEE I6B I6 H7 H8 GND GND GND GND I7B I7 H5 H6 VPLUSDOUT VPLUSDOUT VEE VEE I8B I8 H3 H4 GND GND GND GND I9B I9 H1 H2 VPLUSDOUT VPLUSDOUT VEE GND ADCDELADJOUT ADCDELADJOUTB REFH H0 VEE VEE VEE VPLUSDOUT VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VPLUSDOUT GND VEE Row T T T U U U U U U U U U U U U U U U U U U U V V V V V V V V V V V V V V V V V V V W W W W W W W W W W W W W W W W W W W Col 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Name VEE ADCDELADJIN ADCDELADJINB F8 F9 VEE VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VPLUSDOUT VPLUSDOUT GND GND GND GND F7 F6 F4 F2 F0 D9 D7 D5 D3 D1 REFD B8 B6 B4 B2 B0 BIST CLKINTYPE ADCDELADJCTRL NC F5 F3 F1 REFF D8 D6 D4 D2 D0 B9 B7 B5 B3 B1 REFB NBBIT ADCDELADJCTRLB NC TS81102G0 2105C–BDC–11/03 TS81102G0 Figure 20. TBGA 240 Package: Bottom View 19 RstSync 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 RstSyncb Demuxdeladjctrcl A9 A7 A5 A3 A1 REFA C8 C6 C4 C2 C0 E9 E7 E5 E3 A8 A6 A4 A2 A0 C9 C7 C5 C3 C1 REFC E8 E6 E4 E2 E1 B Demuxdeladjctrclb Asyncreset 1 A DIODE GND GND GND VPLUSD VPLUSD VPLUSD VEE VPLUSD VEE VPLUSD VEE VPLUSD VPLUSD VPLUSD VPLUSD VEE E0 REFE C I0 I0b GND VCC VCC GND VPLUSD VEE VPLUSD VEE VPLUSD VEE VPLUSD VPLUSD VEE VEE VEE G9 G8 D I1 I1b VEE VEE VEE VPLUSD G7 G6 E I2 I2b GND GND GND GND G5 G4 F I3 I3b VEE VEE VEE VEE G3 G2 G CLK CLKb GND GND GND GND G1 G0 H I4 I4b VEE VEE VCC VPLUSD REFG DR J I5 I5b GND VEE VEE VEE DRb SWIadj K I6 I6b VEE VEE VPLUSD VPLUSD RATIOSEL H9 L I7 I7b GND GND GND GND H8 H7 M I8 I8b VEE VEE VPLUSD VPLUSD H6 H5 N I9 I9b GND GND GND GND H4 H3 P ADCdelayadjoutB ADCdelayadjout GND VEE VPLUSD VPLUSD H2 H1 R ADCdelayadjinB ADCdelayadjin VEE VEE GND VPLUSD VPLUSD VEE VPLUSD VEE VPLUSD VEE VPLUSD VPLUSD VEE VEE VEE H0 REFH T GND GND VPLUSD VPLUSD VPLUSD VEE VPLUSD VEE VPLUSD VEE VPLUSD VPLUSD VPLUSD VPLUSD VEE F9 F8 U BIST B0 B2 B4 B6 B8 REFD D1 D3 D5 D7 D9 F0 F2 F4 F6 F7 V NbBIT REFB B1 B3 B5 B7 B9 D0 D2 D4 D6 D8 REFF F1 F3 F5 GND GND ADCDELADJCTRL CLKINTYPE ADCDELADJCTRLb W 25 2105C–BDC–11/03 Outline Dimensions Figure 21. Package Dimension – 240 Tape Ball Grid Array 11 0.10 D 10 -A- Corner 19 17 15 13 11 9 7 5 3 1 -B- Ref. A A1 D D1 E E1 b c M N aaa ccc e g P 18 16 14 12 10 8 6 4 2 A B C D E F G H J K L M N P R T U V W e E E1 e 45 degree 0.5 mm chamfer (4 PLCS) Detail B D1 Top View Bottom View Dimensional References Min. Nom. 1.30 1.50 0.50 0.60 24.80 25.00 22.86 (BSC.) 24.80 25.00 22.86 (BSC.) 0.60 0.75 0.90 0.80 19.00 240.00 1.27 TYP. 0.35 0.15 Max. 1.70 0.70 25.20 25.20 0.90 1.00 0.15 0.25 - Notes: 1. All dimensions are in millimeters. 2. "e" represents the basic solder ball grid pitch. 3. "M" represents the basic solder ball matrix size, and symbol "N" is the maximum allowable number of balls after depopulating. g Detail A 4 "b" is measured at the maximum solder ball diameter parallel to primary datum - C 5 Dimension "aaa" is measured parallel to primary datum - C - g Side View 0.30 M C A M B M 0.30 M C b 4 Detail B 6 Primary datum - C - and seatin plane are defined by the spherical crowns of the solder balls. 7. Package surface shall be black oxide. 8. Cavity depth various with die thickness. 9. Substrate material base is copper. 10 Bilateral tolerance zone is applied to each side of package body. 11 45 deg. 0.5 mm chamfer corner and white dot for pin 1 identification. A1 C A P ccc C -C- 6 Detail A aaa C 5 Thermal and Moisture Characteristics Thermal Resistance from Junction to Case: RTHJC 26 The Rth from junction to case for the TBGA package is estimated at 1.05°C/W that can be broken down as follows: • Silicon: 0.1°C/W • Die attach epoxy: 0.5°C/W (thickness # 50 µm) • Copper block (back side of the package): 0.1°C/W • Black Ink: 0.251°C/W. TS81102G0 2105C–BDC–11/03 TS81102G0 Thermal Resistance from Junction to Ambient: RTHJA A pin-fin type heat sink of a size 40 mm x 40 mm x 8 mm can be used to reduce thermal resistance. This heat sink should not be glued to the top of the package as Atmel cannot guarantee the attachment to the board in such a configuration. The heat sink could be clipped or screwed on the board. With such a heat sink, the Rthj-a is about 6°C/W (if we take 10°C/W for Rth from the junction to air through the package and heat sink in parallel with 15°C/W from the junction to the board through the package body, through balls and through board copper). Without the heat sink, the Rth junction to air for a package reported on-board can be estimated at 13 to 20°C/W (depending on the board used). The worst value 20°C/W is given for a 1-layer board (13°C for a 4-layer board). Thermal Resistance from Junction to Bottom of Balls The thermal resistance from the junction to the bottom of the balls of the package corresponds to the total thermal resistance to be considered from the silicon’s die junction to the interface with a board. This thermal resistance is estimated to be 4.8°C/W max. The following diagram points out how the previous thermal resistances were calculated for this packaged device. Figure 22. Thermal Resistance from Junction to Bottom of Balls DEMUX − Axpproximative Model for 240 TBGA Assumptions: Square die 7.0 x 7.0 = 49 mm², 75 µm thick Epoxy/Ag glue, 0.40 mm copper thickness under die, Sn60Pb40 columns diameter 0.76 mm, 23 x 23 mm TBGA Typical values (values are in °C/Watt) Case were all Bottom of Balls are connected to infinite heatsink (values are in °C/Watt) Silicon Junction Silicon Junction Silicon Die 49 mm² 0.10 0.10 0.60 0.60 λ = 0.95Watt/°C Epoxy/Ag glue λ = 0.025Watt/°C Copper base (Top half of thickness) λ = 25Watt/°C Copper base 0.05 1.70 0.05 0.05 1.70 0.25 1.87 Reduction 0.25 Reduction Silicon Junction 1.43 Tape + glue over balls 2.45 λ = 0.02Watt/°C Black ink 0.25 0.40 0.31 Balls PbSn Silicon Junction 3.55 2.47 1.74 2.47 1.99 λ = 0.40Watt/°C Top of package 2 internal 2 external rows rows (104 balls) (136 balls) Thermal Resistance Junction to case typical = 0.10 + 0.60 + 0.05 + 0.05 + 0.25 = 1.05°C/W Infinite heatsink at bottom of balls Infinite heatsink Infinite heatsink at bottom of balls at bottom of balls Thermal Resistance Junction to bottom of balls = 4.8°C/W Max Thermal Resistance Junction to case Max = 1.40°C/W 27 2105C–BDC–11/03 Temperature Diode Characteristic The theoretical characteristic of the diode according to the temperature when I = 3 mA is depicted below. Figure 23. Temperature Diode Characteristic Vdiode DiodeT 1.0 I = 3 mA dV/dT = 1.32 mV/°C (V) 900m 800m 700m -70.0 -20.0 30.0 80.0 130.0 Temperature (°C) Moisture Characteristic This device is sensitive to moisture (MSL3 according to the JEDEC standard). The shelf life in a sealed bag is 12 months at < 40°C and < 90% relative humidity (RH). After this bag is opened, devices that might be subjected to infrared reflow, vapor-phase reflow, or equivalent processing (peak package body temperature 220°C) must be: • mounted within 168 hours at factory conditions of ≤ 30°C/60% RH, or • stored at ≤ 20% RH. The devices require baking before mounting, if the humidity indicator is > 20% when read at 23°C ±5°C. If baking is required, the devices may be baked for: 28 • 192 hours at 40°C + 5°C/-0°C and < 5% RH for low temperature device containers, or • 24 hours at 125°C ± 5°C for high-temperature device containers. TS81102G0 2105C–BDC–11/03 TS81102G0 Detailled Cross Section The following diagram depicts a detailed cross section of the DMUX TBGA package. Figure 24. TBGA 240: 1/2 Cross Section Copper Heatspreader Block overcoat Adhesive Die Attach Epoxy/Ag Solder Mask Metal 2 side Polyimide Tape Silicon Die Block Epoxy resin encapsulant Gold wires Copper traces and Solder Balls Pads on metal 1 side Sn/Pb/Ag 62/36/2 Eutectic Solder Balls Solder Mask Metal 1 side In the DMUX package shown above, the die’s rear side is attached to the copper heat spreader, so the copper heat spreader is at -5V. It is necessary to use a heat sink tied to the copper heat speader. Moreover, there is only a little layer of painting over the copper heat spreader which does not isolate it. It is therefore recommended to either isolate the heat sink from the other components of the board or to electrically isolate the copper heat spreader from the heat sink. In the latter case, one should use adequate low Rth electrical isolation. 29 2105C–BDC–11/03 Applying the TS81102G0 DMUX The TSEV81102G0 DMUX evaluation board is designed to be connected with the TSEV8388G and TSEV83102G0 ADC evaluation boards. Figure 25. TSEV81102G0 DMUX Evaluation Boards VplusD = 0V → 3.3V CLOCK BUFFER s-e or diff. (2 GHz) Vee = -5V FS Vcc = +5V (125 MHz) 8x8b/10b single A[0..9] → H[0..9] DEMUX Analog Input ADC (1 GHz) 8b/10b diff. Data Bus RefA → RefH (250 MHz) 1b diff. I[0..9] (1 - 2 GHz) 1b diff. ASIC (DC) 8 ref Clkln DR Clkln Data Ready delay ECL + ref 8bits 1 GHz TS8388B 10bits 2 GHz TS83102G0 VplusD = ground Rload = 50Ω Vtt = -2V Voh = -0.8V Vol = -1.8V ECL Rload = 50Ω Vih = -1.0V Vil = -1.4V Delay adjust control Number of bits (8/10) Synchronous or Asynchronous Reset TS81102G0 TTL + ref VplusD = 3.3V Rload ≥ 75Ω Vtt = ground Voh = 2.5V Vol = 0.5V PECL + ref VplusD = 3.3V Rload = 50Ω Vtt = 1.3V Voh = 2.5V Vol = 1.5V Please refer to the "ADC and DMUX Application Note" for more information. 30 TS81102G0 2105C–BDC–11/03 TS81102G0 ADC to DMUX Connections The DMUX inputs configuration has been optimized to be connected to the TS8388B ADC. The die in the TBGA package is up. For the ADC, different types of packages can be used such as CBGA with die up or the CQFP68 down. The DMUX device being completely symmetrical, both ADC packages can be connected to the TBGA package of the DMUX crisscrossing the lines (see Table 8). Table 8. ADC to DMUX Connections ADC Digital Outputs CQFP68 Package DMUX Data Inputs TBGA Package ADC Digital Outputs CBGA Package DMUX Data Inputs TBGA Package D0 I7 D0 I0 D1 I6 D1 I1 D2 I5 D2 I2 D3 I4 D3 I3 D4 I3 D4 I4 D5 I2 D5 I5 D6 I1 D6 I6 D7 I0 D7 I7 – 18 not connected – 18 not connected – 19 not connected – 19 not connected Note: The connection between the ADC evaluation board and the DMUX evaluation board requires a 4-pin shift to make the D0 pin match either the I7 or I0 pin of the DMUX evaluation board. 31 2105C–BDC–11/03 TSEV81102G0TP: Device Evaluation Board General Description The TSEV81102G0TP DMUX Evaluation Board (EB) is designed to simplify the characterization and the evaluation of the TS81102G0 device (2 Gsps DMUX). The DMUX EB enables testing of all the DMUX functions: Synchronous and Asynchronous reset functions, selection of the DMUX ratio (1:4 or 1:8), selection of the number of bits (8 or 10), output data common mode and swing adjustment, die junction temperature measurements over military temperature range, etc. The DMUX EB has been designed to enable easy connection to Atme’s ADC Evaluation Boards (such as TSEV8388BGL or TSEV83102G0BGL) for an extended functionality evaluation (ADC and DMUX multi-channel applications). The DMUX EB comes fully assembled and tested, with a TS81102G0 device implemented on the board and a heat sink assembled on the device. 32 TS81102G0 2105C–BDC–11/03 TS81102G0 Ordering Information Table 9. Ordering Information Part Number Package JTS81102G0-1V1A Die TS81102G0CTP TBGA 240 "C" grade 0°C < Tc; Tj < 90°C Standard TS81102G0VTP TBGA 240 "V" grade -40°C < Tc; Tj < 110°C Standard TSEV81102G0TPZR3 TBGA 240 Ambient Prototype Datasheet Status Description Temperature Range Ambient Screening Comments Visual inspection Evaluation board (delivered with heatsink) Table 10. Datasheet Status Datasheet Status Validity Objective specification This datasheet contains target and goal specifications for discussion with customer and application validation. Before design phase Target specification This datasheet contains target or goal specifications for product development. Valid during the design phase Preliminary specification α-site This datasheet contains preliminary data. Additional data may be published later; could include simulation results. Valid before characterization phase Preliminary specification β-site This datasheet contains also characterization results. Valid before the industrialization phase Product specification This datasheet contains final product specification. Valid for production purposes Limiting Values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application Information Where application information is given, it is advisory and does not form part of the specification. Life Support Applications These products are not designed for use in life-support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Atmel for any damages resulting from such improper use or sale. 33 2105C–BDC–11/03 Addendum This section has been added to the description of the device for better understanding of the synchronous reset operation. It puts particular stress on the setup and hold times defined in the switching characteristics table (Table 5), linked with the device performances when used at full speed (2 Gsps). Synchronous Reset Operation It first describes the operation of the synchronous reset in case the DMUX is used in DR mode and then when used in the DR/2 mode. As a reminder, the synchronous reset has to be a signal frequency of Fs/8N in 1:8 ratio or Fs/4N in 1:4 ratio, where N is an integer. The effect of the synchronous reset is to ensure that at each new port selection cycle, the first port to be selected is port A. The synchronous reset ensures the internal cyclic synchronization of the device during operation. It is also highly recommended in the case of multichannel applications using 2 synchronized DMUXs. SETUP and HOLD Timings The setup and hold times for the reset are defined as follows: • SETUP from SynchReset to Clkin: Required delay between the rising edge of the reset and the rising edge of the clock to ensure that the reset will be taken into account at the next clock edge. If the reset rising edge occurs at less than this setup time, it will be taken into account only at the second next rising edge of the clock. A margin of ± 100ps has to be added to this setup time to compensate for the delays from the drivers and lines. • HOLD from Clkin and SynchReset: Minimum duration of the reset signal at a high level to be taken into account by the DMUX. This means that the reset signal has to satisfy 2 requirements: a frequency of Fs/8N or Fs/4N (N is an integer) depending on the ratio and a duty cycle such that it is high during at least the hold time. Operation in DR Mode In DR mode, the DMUX input clock can run at up to 2 GHz in 1:8 ratio or 1 GHz in 1:4 ratio. Both cases are described in the following timing diagrams. Figure 26. Synchronous Reset Operation in DR Mode, 1:4 ratio, 1GHz (Full Speed) – Principle of Operation Fs Sync_RESET 34 TS81102G0 2105C–BDC–11/03 TS81102G0 Figure 27. Synchronous Reset Operation in DR Mode, 1:4 ratio, 1GHz (Full Speed) – TIMINGS Fs Time Zones Allowed for the reset Sync_RESET Note: The clock edge to which the reset applies is the one identified by the arrow. If the reset rising edge had occurred in the second allowed window, the reset would have been effective on the third clock rising edge (not represented, on the right of the edge represented with the arrow). Figure 28. Synchronous Reset Operation in DR Mode, 1:8 ratio, 2 GHz (Full-speed) – Principle of Operation Fs Sync_RESET Figure 29. Synchronous Reset Operation in DR Mode, 1:8 ratio, 2 GHz (Full-speed) – Timings Fs Times Zones Allowed for the reset Sync_RESET Note: The clock edge to which the reset applies is the one identified by the arrow. If the reset rising edge had occurred in the second allowed window, the reset would have been effective on the fourth clock rising edge (last clock rising edge, on the right of the edge represented with the arrow). This case is the most critical one with only a 300 ps window for the reset. 35 2105C–BDC–11/03 Operation in DR/2 Mode In DR/2 mode, the DMUX input clock can run at up to 1 GHz in 1:8 ratio or 500 MHz in 1:4 ratio, since the DR/2 clock from the ADC is half the sampling frequency. Both cases are described in the following timing diagrams. Figure 30. Synchronous Reset Operation in DR/2 Mode, 1:4 ratio, 500MHz (Full Speed) – Principle of Operation Fs/2 Sync_RESET Figure 31. Synchronous Reset Operation in DR/2 Mode, 1:4 ratio, 500 MHz (Full-speed) – Timings Fs/2 Times Zones Allowed for the reset Sync_RESET Note: The clock edge to which the reset applies is the one identified by the arrow. If the reset rising edge had occurred in the first allowed window (on the left), the reset would have been effective on the first represented clock rising edge (first clock rising edge of the schematic, on the left of the edge represented with the arrow). Figure 32. Synchronous Reset Operation in DR/2 Mode, 1:8 ratio, 1GHz (Full Speed) – Principle of Operation Fs/2 Sync_RESET 36 TS81102G0 2105C–BDC–11/03 TS81102G0 Figure 33. Synchronous Reset Operation in DR/2 Mode, 1:8 ratio, 1GHz (Full-speed) – Timings Fs/2 Times Zones Allowed for the reset Sync_RESET Note: The clock edge to which the reset applies is the one identified by the arrow. If the reset rising edge had occurred in the second allowed window, the reset would have been effective on the fourth clock rising edge (not represented, on the right of the edge represented with the arrow). 37 2105C–BDC–11/03 Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131, USA TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 2325 Orchard Parkway San Jose, CA 95131, USA TEL 1(408) 441-0311 FAX 1(408) 436-4314 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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