UCC2751 UCC3751 Single Line Ring Generator Controller FEATURES DESCRIPTION • Novel Topology for Low-Cost, Efficient The UCC3751 controller is designed for driving a power stage that generGeneration of Ring Voltage ates low frequency, high voltage sinusoidal signals for telephone ringing applications. The controller and the power stage are most suitable for sin• Provides DC Offset and “Talk Battery” gle line applications where low cost, high efficiency and minimum parts Voltage for Off-Hook Conditions count are critical. In addition to providing the sinusoidal ringing signal, the • Selectable 20, 25 and 50 Hz Ring controller and the power stage are designed to provide the required DC Frequency voltage across the output when the phone goes off-hook. The DC voltage is also added as the offset to the ringing signal. This feature eliminates the • Secondary (AC) Current Limiting need to have a separate talk battery voltage power supply as well as relays Allows Removal of AC Voltage under and drivers to switch between the ringing voltage and the talk battery. Off-Hook Conditions • Primary Current Limiting to turn Power The UCC3751 directly drives primary side switches used to implement a push-pull resonant converter topology and transformer coupled sampling Stage off under Fault Conditions switches located on the secondary of the converter. For normal ring signal • Operates from a Single 12V Supply generation, the primary switching frequency and secondary sampling frequency are precisely offset from each other by the ringing frequency to produce a high voltage low frequency alias signal at the output. The off-hook condition is detected by sensing the AC current and when AC limit is exceeded, the sampling frequency is set to be equal to the primary switching frequency to produce a DC output. The drive signal frequencies are derived from a high frequency (3579545 Hz) crystal. The primary switching frequency is 89.488 kHz and the sampling frequency is 20, 25 or 50 Hz less depending on the status of frequency select pins FS0 and FS1. The circuits described in this datasheet are covered under US Patent #5,663,878 and other patents pending. TYPICAL APPLICATIONS CIRCUIT D1 RSENSE LIN T1 DC SIGNAL CDC VIN V1 12V AC SIGNAL CR2 LR CF SAMPLING CIRCUIT LR N:1 Q1 Q2 12V CBYP1 CR1 VOUT 9 12 2 6 4 VS12 DRVS RINGEN OHD VDD 11 DRV1 5 DCLIM 13 DRV2 UCC3751 CBYP2 ENABLE 10 DELAY 1 XTAL2 GND PGND FS0 FS1 XTAL1 3 14 7 8 16 15 3.579545MHz APRIL 1999 - REVISED AUGUST 2000 - SLUS267B Powered by ICminer.com Electronic-Library Service CopyRight 2003 UDG-98047 UCC2751 UCC3751 CONNECTION DIAGRAM ABSOLUTE MAXIMUM RATINGS Input Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V Analog Inputs (OHD, DCLIM, XTAL1, XTAL2) Maximum Forced Voltage. . . . . . . . . . . . . . . . . . . . –0.3 to 5V Logic Inputs Maximum Forced Voltage . . . . . . . . . . . . . . . . . . –0.3 to 7.5V Reference Output Current (VDD) . . . . . . . . . . . Internally Limited Output Current (DRV1, DRV2, DRVS) Pulsed . . . . . . . . . . 1.5A Operating Junction Temperature . . . . . . . . . . –55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C DIL-16, SOIC-16 (TOP VIEW) N or D Packages DELAY 1 16 XTAL1 RINGEN 2 15 XTAL2 GND 3 14 PGND VDD 4 13 DRV2 DCLIM 5 12 DRVS OHD 6 11 DRV1 FS0 7 10 ENABLE FS1 8 9 VS12 Note: Unless otherwise indicated, voltages are referenced to ground and currents are positive into, negative out of, the specific terminals. Pulsed is defined as a less than 10% duty cycle with a maximum duration of 500 S. BLOCK DIAGRAM ENABLE 10 XTAL2 15 XTAL1 16 MODULO 20 COUNTER MODULO 2 COUNTER 11 DRV1 13 DRV2 12 DRVS 14 PGND 3 GND 9 VS12 4 VDD ONE-SHOT DCLIM 5 PROGRAMMABLE COUNTER CLR 300mV CLK DELAY 1 OHD 6 2 BIT A/D ONE-SHOT 300mV 1/FOSC RINGEN 2 FS1 8 MODULO 1,800 COUNTER MODULO 3,560 COUNTER FS0 2/FOSC MODULO 40 COUNTER ONE-SHOT 5 VOLT REFERENCE 7 MODULO 4,480 COUNTER 4.5V UDG-98020 2 Powered by ICminer.com Electronic-Library Service CopyRight 2003 UCC2751 UCC3751 Table I. Frequency selectability decoding. FS1 FS0 MODE 0 0 1 1 OHD = 0.5 0 1 0 1 1 1 1 3 2 Sine Wave Frequency (Hz) 20 25 50 0 0 RINGEN OHD FS1 FS0 FDRVS 1 1 1 0 X 0 0 0 X 1 0 0 1 X X 0 1 0 X X 89.469kHz 89.464kHz 89.439kHz 89.489kHz 89.489kHz FDRV– FDRVS 20Hz 25Hz 50Hz 0.0Hz 0.0Hz ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications hold for TA = 0°C to 70°C for the UCC3751 and –40°C to +85°C for the UCC2751, TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS V12 Supply Current Section Supply Current ENABLE = 0V 1.0 3.0 mA ENABLE = 5V 1.0 3.0 mA Internal Reference with External Bypass Section Output Voltage (VDD) Load Regulation 4.85 0mA ≤IVDD ≤2mA Line Regulation 10V < VS12 < 13V, IVDD = 1mA Short Circuit Current VDD = 0 5 5 5.15 V 5 20 mV 3 20 mV 10 mA Output Drivers Section (DRV1, DRV2) Pull Up Resistance ILOAD = 10mA to 20mA 6 15 Pull Down Resistance ILOAD = 10mA to 20mA 6 15 Rise Time CLOAD = 1nF 50 100 nS Fall Time CLOAD = 1nF 50 100 nS Pull Up Resistance ILOAD = 10mA to 20mA 4 10 Pull Down Resistance ILOAD = 10mA to 20mA 4 10 Output Drivers Section (DRVS) Sample Pulse-Width Mode 1 and 2, (Note 1) 280 320 nS Rise Time CLOAD = 1nF 240 50 100 nS Fall Time CLOAD = 1nF 50 100 nS 250 300 350 mV –900 –100 250 300 350 mV –900 –100 nA Current Limit Section OHD Threshold OHD Input Current VOHD = 0V DCLIM Threshold DCLIM Input Current VDCLIM = 0V nA Frequency Section (Note 1) Primary Switching Frequency All cases 3.579545 MHz Crystal 89489 Hz Sampling Switching Frequency FS0 = 0, FS1 = 0, Mode 1, (Note 1) 89469 Hz FS0 = 1, FS1 = 0, Mode 1 89464 Hz FS0 = 0, FS1 = 1, Mode 1 89439 Hz 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 UCC2751 UCC3751 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications hold for TA = 0°C to 70°C for the UCC3751 and –40°C to +85°C for the UCC2751, TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Off-Hook Sampling Delay (Note 2) td0 VDELAY < 0.9V 0 20 nS td1 1.1V < VDELAY < 1.9V 252 280 308 nS td2 2.1V < VDELAY < 2.9V 504 560 616 nS td3 3.1V < VDELAY < 3.9V 756 840 924 nS td4 4.1V < VDELAY 1008 1120 1232 nS Note 1. Frequency setting is as shown in the Frequency Selectability Decoding Table. Sine Wave Frequency = Primary – Sampling Frequency. Note 2. The delay function will delay the sample pulse from the rising edge of DRV2 to allow adjustment of the DC level provided during Mode 2. PIN DESCRIPTIONS DCLIM: Primary current sense input. Signal proportional to the primary switch current. All outputs are turned off when a threshold of 300mV is exceeded on this pin. This current limit works on a cycle-by-cycle basis. frequencies (20,25 and 50 Hz). See Note 1 in the spec table. DELAY: A resistive divider from VDD to GND is programmed and fed into DELAY pin. The voltage at this pin sets the phase difference between the sampling pulses and primary pulses under off-hook condition. By programming the delay, desired level of DC voltage can be attained at the ringer output when the OHD threshold is exceeded. OHD: Secondary current sense input. Voltage proportional to output current DC level is fed into this pin and compared to an internal threshold of 300mV. If the threshold is exceeded, the sampling scheme is changed to eliminate the AC component in the output voltage as required by the off-hook condition. GND: Reference point for all the internal voltages and common return for the device. PGND: Return point for the output drivers. Connect to GND at a single point in the circuit. DRV1, DRV2: Low impedance driver outputs for the primary switches. RINGEN: Logic input used to determine when the ring signal is needed. When this signal is high and OHD low, normal ring signal is available at the output of the ring generator. DRVS: Low impedance driver output for the sampling switch(es). The pulse width of this output is 280ns. Typically, a pulse transformer is used to couple the short sampling pulses at DRVS to the floating sampling switch(es). VDD: Internal regulated 5V supply. This voltage is used to power all the internal precision circuits of the IC. This pin needs to be bypassed to GND with ceramic capacitor. ENABLE: Logic input which turns off the outputs when low. VS12: External 12V power supply for the IC. Powers VDD and provides voltage for the output drivers. FS0, FS1: Frequency select pins for determining the difference frequency between primary and secondary pulses under normal operation. These pins can be hardwired to GND or VDD to get one of the available output XTAL1, XTAL2: Pins for connecting precision Crystal to attain the accurate output frequencies. An external square-wave pulse can also be applied to XTAL2 if XTAL1 is tied to VDD/2. 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 UCC2751 UCC3751 APPLICATION INFORMATION Power Stage Operation transformer. Typical pulsewidth of the sampling signal is 280ns. As a result of sampling, the resultant output signal matches the secondary voltage in amplitude and has a low output frequency desired for ring generation. The power stage used for the UCC3751 application has two distinct switching circuits which together produce the required low frequency signal on the output. The primary side switching circuit consists of a current fed push-pull resonant circuit that generates the high frequency sinusoidal waveform across the transformer winding. The operation of this type of circuit is extensively covered in Unitrode Application notes U-141 and U-148. Resonant components CR1, CR2, LR, N should be chosen so that the primary and secondary resonances are well matched. Also, for the UCC3751 operation, switching frequency is fixed by crystal selection. So, the resonant components must be selected to yield a resonant frequency close enough to the switching frequency to get a low distortion sine-wave. Practically, since it is impossible to get an exact match between the two frequencies, the switching frequency should always be higher than the resonant frequency to ensure low distortion and take advantage of ZVT operation. Switches Q1 and Q2 are pulsed at 50% duty cycle at the switching frequency (89.489 kHz) determined by a crystal (3.579545 MHz) connected to the UCC3751. The input voltage for the resonant stage (typically 12V) determines the voltage stress of Q1 and Q2. Transformer turns ratio is determined by the output voltage requirements. On the secondary side, the high frequency waveform is sampled at a predetermined frequency (e.g. 89.469 kHz) which differs from the primary switching frequency by the desired output frequency (e.g. 20 Hz). The sampling is accomplished using a bi-directional switching circuit as shown in Figure 2 and Figure 3. Figure 2 shows the sampling mechanism consisting of two back-to-back FET switches allowing current flow in both directions. The sampling can also be done with a single active switch and a full-bridge rectifier as shown in Fig. 3. The DRVS pin of the UCC3751 provides the drive signal for the sampling switch(es) and this signal is coupled through a pulse The secondary winding of the power transformer also has a tap (or a separate winding) to generate a loosely regulated DC voltage. This DC voltage can be used to offset the ring generator output. The UCC3751 is also configured such that the AC output can go to zero under certain conditions. Table 2 provides the logic levels for different operating modes of UCC3751. Operation in mode 2 is achieved by altering the sampling frequency to match the switching frequency and sampling the secondary AC voltage at zero crossings. As a result, the resultant total output voltage between VOUT and GND is the semi-regulated DC voltage achieved through the tapped secondary. This feature allows the circuit to operate under off-hook and idle conditions when only the DC portion of the voltage is required. The activation of this mode occurs when the OHD voltage exceeds a set threshold or RINGEN is low. The incorporation of this mode eliminates any need for external relays or switching circuits as well as eliminating the need for an additional power supply for powering the phone. The DC voltage level can be fine tuned by adjusting the voltage on the DELAY pin of the UCC3751. This pin sets the sampling delay time during the off-hook mode and allows a DC voltage to be developed between V1 and VOUT during this mode. Fig. 1 illustrates the operation of this mode. When the DELAY is set between 0 and 1V, the sampling is done in phase with the primary switching instances (at points A), leading to an average voltage of 0V between V1 and VOUT for a sinusoidal secondary signal. If DELAY is set to another level, the sampling instance shifts (e.g. to point B) leading to an effective voltage VB being developed between V1 and VOUT. The actual VOUT is the sum of VB and the DC offset voltage derived from the additional (or tapped) winding (V1). Table II. Operating mode selection. Condition Continuous Ringing Idle (On Hook, No Ringing) Low Low OHD RINGEN High Low Off-Hook Cadenced Ringing High Low X (Low/High) High/Low 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Sampling Output Mode Frequency Offset from Primary (Mode 1) Synchronized to Primary Frequency with Phase Controlled by DELAY (Mode 2) Mode 2 Mode 1/Mode 2 UCC2751 UCC3751 TRANSFORMER SECONDARY VOLTAGE VB B A B A B 0 0 VDRV2 Figure 1. Effects of sampling delay during off-hook operation. TO TRANSFORMER TO TRANSFORMER DRVS DRVS TO OUTPUT TO OUTPUT Figure 2. Sampling circuit with two FETs. Figure 3. Sampling circuit with single FET and full-bridge rectifier. UNITRODE CORPORATION 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. (603) 424-2410 • FAX (603) 424-3460 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. 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