UCC2752 UCC3752 Resonant Ring Generator Controller FEATURES PRELIMINARY DESCRIPTION • Novel Topology for Low-Cost, Efficient The UCC3752 controller is designed for driving a power stage that generGeneration of Ring Voltage ates low frequency, high voltage sinusoidal signals for telephone ringing applications. The controller and the power stage are most suitable for up to • Suitable for Multi-Line Operation 5 line applications where low cost, high efficiency and minimum parts count • Selectable 20, 25 and 50 Hz Ring are critical. A semi-regulated DC voltage is added as an offset to the ringFrequency ing signal. The ring generator operation is non-isolated and open loop. • Secondary (AC) Current Limiting Generates an Off-Hook Detect Signal • Primary Current Limiting to Turn Power Stage Off Under Fault Conditions • Operates from a Single 12V Supply The UCC3752 directly drives primary side switches used to implement a push-pull resonant converter topology and transformer coupled sampling switches located on the secondary of the converter. For normal ring signal generation, the primary switching frequency and secondary sampling frequency are precisely offset from each other by the ringing frequency to produce a high voltage low frequency alias signal at the output. The off-hook condition is detected by sensing the AC current and when AC limit is exceeded, a flag is generated on the OFFHOOK pin. The drive signal frequencies are derived from a high frequency (3579545 Hz) crystal. The primary switching frequency is 89.489 kHz and the sampling frequency is 20, 25 or 50 Hz less depending on the status of frequency select pins FS0 and FS1. The circuits described in this datasheet are covered under US Patent #5,663,878 and other patents pending. TYPICAL APPLICATION D1 RSENSE LIN T1 DC SIGNAL CDC VIN V1 12V LR AC SIGNAL CR2 SAMPLING CIRCUIT LR CBYP1 CR1 Q2 VOUT 12V N:1 Q1 CF 9 12 2 6 4 VS12 DRVS N/C OHD VDD 11 DRV1 5 DCLIM 13 UCC3752 DRV2 CBYP2 ENABLE 10 OFFHOOK 1 XTAL2 15 GND PGND FS0 FS1 XTAL1 3 14 7 8 16 3.579545MHz UDG-98058 SLUS269 - JULY 1999 UCC2752 UCC3752 CONNECTION DIAGRAMS ABSOLUTE MAXIMUM RATINGS Input Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2V Analog Inputs (OHD, DCLIM, XTAL1, XTAL2) Maximum Forced Voltage. . . . . . . . . . . . . . . . . . . . –0.3 to 5V Logic Inputs Maximum Forced Voltage . . . . . . . . . . . . . . . . . . –0.3 to 7.5V Reference Output Current (VDD) . . . . . . . . . . . Internally Limited Output Current (DRV1, DRV2, DRVS) Pulsed . . . . . . . . . . 1.5A Operating Junction Temperature . . . . . . . . . . –40°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C (TOP VIEW) DIL-16, SOIC-16 N or D Packages OFFHOOK 1 16 XTAL1 N/C 2 15 XTAL2 GND 3 14 PGND VDD 4 13 DRV2 DCLIM 5 12 DRVS OHD 6 11 DRV1 FS0 7 10 ENABLE FS1 8 9 VS12 Note: Unless otherwise indicated, voltages are referenced to ground and currents are positive into, negative out of, the specific terminals. Pulsed is defined as a less than 10% duty cycle with a maximum duration of 500 S. Table I. Frequency selectability decoding. FS1 FS0 MODE 0 0 1 1 0 1 0 1 1 1 1 3 FS1 0 0 1 FS0 0 1 0 FDRVS 89.469kHz 89.464kHz 89.439kHz Sine Wave Frequency (Hz) 20 25 50 0 FDRV – FDRVS 20Hz 25Hz 50Hz ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications hold for TA = 0°C to 70°C for the UCC3752 and –40°C to +85°C for the UCC2752, TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS V12 Supply Current Section Supply Current ENABLE = 0V 0.5 3 mA ENABLE = 5V 0.5 3 mA 5 5.15 Internal Reference with External Bypass Section Output Voltage (VDD) 4.85 Load Regulation 0mA ≤IVDD ≤2mA Line Regulation 10V < VS12 < 13V, IVDD = 1mA Short Circuit Current VDD = 0 5 V 5 mV 3 mV 10 mA Output Drivers Section (DRV1, DRV2) Pull Up Resistance ILOAD = 10mA to 20mA 6 15 Pull Down Resistance ILOAD = 10mA to 20mA 6 15 Rise Time CLOAD = 1nF 50 100 nS Fall Time CLOAD = 1nF 50 100 nS Pull Up Resistance ILOAD = 10mA to 20mA 4 10 Pull Down Resistance ILOAD = 10mA to 20mA 4 10 Output Drivers Section (DRVS) Sample Pulse-Width Mode 1 (Table 1) 280 Rise Time CLOAD = 1nF 50 100 nS Fall Time CLOAD = 1nF 50 100 nS 2 nS UCC2752 UCC3752 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications hold for TA = 0°C to 70°C for the UCC3752 and –40°C to +85°C for the UCC2752, TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Current Limit Section DCLIM Threshold 300 mV VDCLIM = 0V –100 nA 300 mV OHD Input Current VOHD = 0V –100 nA DCLIM Input Current OffHook Detect Section OHD Threshold Offhook VOH IOFFHOOK = 1mA 4.0 V Offhook VOL IOFFHOOK = –1mA 1.0 V Offhook Pull-Up Impedance ILOAD = 0mA to 1mA 400 Offhook Pull-Down Impedance ILOAD = 0mA to 1mA 250 Frequency Section (Table 1) Primary Switching Frequency All cases 3.579545 MHz Crystal 89489 Hz Sampling Switching Frequency FS0 = 0, FS1 = 0, Mode 1, (Table 1) 89469 Hz FS0 = 1, FS1 = 0, Mode 1 89464 Hz FS0 = 0, FS1 = 1, Mode 1 89439 Hz PIN DESCRIPTIONS DCLIM: Primary current sense input. Signal proportional to the primary switch current. All outputs are turned off when a threshold of 300mV is exceeded on this pin. This current-limit works on a cycle-by-cycle basis. GND: Reference point for all the internal voltages and common return for the device. OFFHOOK: Output indicating the off-hook condition. This signal can be used by an external circuit to switch to a line from the ring generator output to the DC voltage. DRV1, DRV2: Low impedance driver outputs for the primary switches. DRV1 and DRV2 are complimentary and have 50% duty cycle. OHD: Off-Hook Detect. Voltage proportional to output current DC level is fed into this pin and compared to an internal threshold of 300mV. If the threshold is exceeded, the OFFHOOK output goes high. DRVS: Low impedance driver output for the sampling switch(es). The pulse width of this output is 280ns. Typically, a pulse transformer is used to couple the short sampling pulses at DRVS to the floating sampling switch(es). PGND: Return point for the output drivers. Connect to GND at a single point in the circuit. VDD: Internal regulated 5V supply. This voltage is used to power all the internal precision circuits of the IC. This pin needs to be bypassed to GND with ceramic capacitor. ENABLE: Logic input which turns off the outputs when low. FS0, FS1: Frequency select pins for determining the difference frequency between primary and secondary pulses under normal operation. These pins can be hardwired to GND or VDD to get one of the available output frequencies (20,25 and 50 Hz). See Table 1 in the spec table. VS12: External 12V power supply for the IC. Powers VDD and provides voltage for the output drivers. XTAL1, XTAL2: Pins for connecting precision Crystal to attain the accurate output frequencies. An external square-wave pulse can also be applied to XTAL2 if XTAL1 is tied to VDD/2. 3 UCC2752 UCC3752 BLOCK DIAGRAM N/C S 2 Q 300mV DCLIM 5 ENABLE 10 XTAL1 XTAL2 OHD MODULO 20 COUNTER 16 DRV1 13 DRV2 12 DRVS 14 PGND 3 GND 9 VS12 4 VDD MODULO 2 COUNTER 15 6 300mV OFFHOOK 11 1-SHOT R 1 MODULO 1,800 COUNTER MODULO 40 COUNTER ONE-SHOT 2/FOSC 1/FOSC MODULO 3,560 COUNTER FS1 ONE-SHOT 5 VOLT REFERENCE 8 MODULO 4,480 COUNTER FS0 7 4.5V UDG-98023 APPLICATION INFORMATION stress of Q1 and Q2. Transformer turns ratio is determined by the output voltage requirements. On the secondary side, the high frequency waveform is sampled at a predetermined frequency (e.g. 89.469 kHz) which differs from the primary switching frequency by the desired output frequency (e.g. 20 Hz). The sampling is accomplished using a bi-directional switching circuit as shown in Figure 1 and Figure 2. Figure 1 shows the sampling mechanism consisting of two back-to-back FET switches allowing current flow in both directions. The sampling can also be done with a single active switch and a full-bridge rectifier as shown in Fig. 2. The DRVS pin of the UCC3752 provides the drive signal for the sampling switch(es) and this signal is coupled through a pulse transformer. Typical pulsewidth of the sampling signal is 280nS. As a result of sampling, the resultant output signal matches the secondary voltage in amplitude and has a low output frequency desired for ring generation. Power Stage Operation The power stage used for the UCC3752 application has two distinct switching circuits which together produce the required low frequency signal on the output. The primary side switching circuit consists of a current fed push-pull resonant circuit that generates the high frequency sinusoidal waveform across the transformer winding. The operation of this type of circuit is extensively covered in Unitrode Application notes U-141 and U-148. Resonant components CR1, CR2, LR, N should be chosen so that the primary and secondary resonances are well matched. Also, for the UCC3752 operation, switching frequency is fixed by crystal selection. So, the resonant components must be selected to yield a resonant frequency close enough to the switching frequency to get a low distortion sine-wave. Practically, since it is impossible to get an exact match between the two frequencies, the switching frequency should always be higher than the resonant frequency to ensure low distortion and take advantage of ZVT operation. Switches Q1 and Q2 are pulsed at 50% duty cycle at the switching frequency (89.489 kHz) determined by a crystal (3.579545 MHz) connected to the UCC3752. The input voltage for the resonant stage (typically 12V) determines the voltage The secondary winding of the power transformer also has a tap (or a separate winding) to generate a loosely regulated DC voltage. This DC voltage can be used to offset the ring generator output. It an also be used as a power supply for supplying talk battery voltage in some applications. 4 UCC2752 UCC3752 APPLICATION INFORMATION (cont.) TO TRANSFORMER TO TRANSFORMER DRVS DRVS TO OUTPUT TO OUTPUT Figure 1. Sampling circuit with two FETs. Figure 2. Sampling circuit with single FET and full-bridge rectifier. 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