[AK2364]
AK2364
Two-way Radio Filterless FM Detector LSI
1. Features
The AK2364 includes 2nd-Mixer, AGC+BPF, PLL FM detector, noise squelch, and RSSI circuit.
This device can eliminate D to G type ceramic filters, quadrature discriminator, and other external
components.
• Low operating voltage: VDD = 2.6 to 5.5 V
• Wide operating temperature: Ta = -40 to 85 °C
• Hi sensitivity: -104dBm at 12dB SINAD
• Built-in 2nd Mixer
• Local frequency: 45.9MHz, 50.4MHz, 57.6MHz (Triple of 15.3, 16.8 and 19.2MHz)
• Built-in programmable AGC+BPF circuits corresponding to D to G type ceramic filters
• Built-in PLL FM detector
• RSSI function
• Built-in noise squelch circuits
• Low consumption current: 7mA
• Compact plastic packaging, 28-pin QFNJ （4.0 x 4.0 x 0.75mm, 0.4mm pitch）
MS1431-E-01
2012/10
-1-
[AK2364]
2. Contents
1. Features...............................................................................................................................1
2. Contents .............................................................................................................................. 2
3. Block Diagram ..................................................................................................................... 3
4. Circuit Configuration ............................................................................................................ 4
5. Pin/Function......................................................................................................................... 5
6. Absolute Maximum Ratings ................................................................................................. 7
7. Recommended Operating Conditions .................................................................................. 7
8. Digital DC Characteristics .................................................................................................... 7
9. Digital AC Timing ................................................................................................................. 8
10. System Reset .................................................................................................................. 10
11. Power Consumption......................................................................................................... 11
12. Analog Characteristics ..................................................................................................... 12
13. Serial Interface Configuration .......................................................................................... 16
14. Calibration Procedure ...................................................................................................... 19
15. Recommended External Application Circuits ................................................................... 21
16. Packaging ........................................................................................................................ 25
17. Important Notice .............................................................................................................. 26
MS1431-E-01
2012/10
-2-
[AK2364]
3. Block Diagram
NC
IF_INPUT
BPF0
AGC0
MIX
MIXIP
BPF1
AGC1
BPF2
NC
NC
NC
PDOUT
DISCOUT
Limiter
LPF
AUDIOOUT
DISCRI
NAMPI
AGCCNT
Noise AMP
NAMPO
Control
Logic
NRECTO
Noise
Rectifier
LDO
VIREF
RSSI
DETO
Comparator
LOIN
LOCAP
RSTN
SCLK SDATA CSN
VREFA
BIAS VSS2
AGNDIN
AGNDOUT
RSSIOUT
LO_INPUT
MS1431-E-01
2012/10
-3-
DVDD DVSS
AVSS
AVDD
[AK2364]
4. Circuit Configuration
Block
MIX
Description
DISCRI
2nd-mixer to convert the input signal down to 450Hz.
The circuit composed of AGC and BPF, where the desired signal is amplified and
spurious components included in the signal from the 2nd-mixer are eliminated.
The circuit to divide the signal from LOIN pin and supply BPF with CLK.
The circuit to amplify the signal filtered at the AGC+BPF stage and generate rectangular
wave.
The demodulator circuit with PLL FM detector, where the audio signal is recovered.
LPF
The Low-pass filter to eliminate the noise generated at the DISCRI stage.
Noise AMP
The amplifier to compose the Band-pass filter for noise squelch.
Noise Rectifier
The rectification circuit to detect the noise level.
Comparator
The circuit to compare the noise level with reference voltage level.
The circuit to indicate the Received Signal Strength Indicator(RSSI) by generate a DC
voltage corresponding to the input level from LIMITER.
The circuit to generate internal reference voltage.
AGC+BPF
Divider
LIMTER
RSSI
VIREF
LDO
Control Logic
The circuit to supply 2.7V power for some circuits.
The control register controls the status of internal condition by serial data that consists of
1 instruction bit, 6 address bits and 8 data bits.
Note: When you use AK2364 in AVDD=2.6 to 3.6V operation, VREFA pin is connected to AVDD pin
for power supplying.
MS1431-E-01
2012/10
-4-
[AK2364]
5. Pin/Function
Signal
Package
Pin No
Name
Type
Conditions
at power
down
Function
1
MIXIP
AI
Z
IF positive signal input pin
2
AVSS
PWR
-
Analog ground pin
3
VREFA
AI
H
Output pin to connect capacitor for LDO
4
AVDD
PWR
-
Analog VDD power supply pin
5
NC
AIO
Z
NC pin
6
NC
AIO
Z
NC pin
7
NC
AIO
Z
NC pin
8
NC
AIO
Z
9
RSSIOUT
AO
Z
10
PDOUT
AO
Z
NC pin
Output pin to connect capacitor for Received Signal Strength
Indicator(RSSI)
Pin1 for DISCRIMINATOR Low-pass filter
11
DISCOUT
AO
Z
PIN2 for DISCRIMINATOR Low-pass filter
12
AUDIOOUT
AO
Z
Demodulated audio signal output pin
13
NAMPI
AI
Z
Input pin for noise squelch amplifier
14
NAMPO
AO
Z
Output pin for noise squelch amplifier
15
NRECTO
AI
Z
Output pin for the rectification circuit
16
BIAS
AO
Z
17
AGNDOUT
AO
Z
18
AGNDIN
AI
Z
19
VSS2
PWR
-
20
RSTN
DI
Z
Output pin to connect bias resistor for reference voltage
Analog ground output pin.
Connect the capacitor to stabilize the analog ground level.
Analog ground input pin.
Connect the capacitor to stabilize the analog ground level.
VSS power supply pin.
Normally supply 0V to this pin.
Hardware reset pin
21
CSN
DI
Z
Chip select input pin for serial data
22
SCLK
DI
Z
Clock input pin for serial data
23
SDATA
DB
-
Input and output pin for serial data
24
DETO
DO
Z
Signal detect output pin
25
DVDD
PWR
-
Digital VDD power supply pin.
26
DVSS
PWR
-
Digital ground pin
27
LOCAP
AI
Z
Local signal input pin
LOIN
AI
Z
28
Local signal input pin
Note:
A: Analog, D: Digital, PWR: Power, I: Input, O: Output, B: Bidirectional, Z: High-Z, L: Low
When you use AK2364 in AVDD=2.6 to 3.6V operation, VREFA pin is connected to AVDD pin for
power supplying. Please set LDO (Low Drop Out) power off setting.
When VREFA pin is supplied by external power supply, absolute maximum ratings and recommended
operating conditions are based on AVDD level.
MS1431-E-01
2012/10
-5-
[AK2364]
VSS2
AGNDIN
AGNDOUT
BIAS
NRECTO
21
RSTN
CSN
• Pin Assignment
20
19
18
17
16
15
NA MP I
DE TO
24
12
AU DIO O UT
DV DD
25
11
D ISC OU T
D VS S
26
10
P DO UT
LO CA P
27
9
R SS IO UT
LO IN
28
8
NC
1
2
3
4
5
6
7
NC
13
NC
23
NC
S DATA
AVDD
NA MP O
VREFA
14
AVSS
22
MIXIP
SCL K
MS1431-E-01
2012/10
-6-
[AK2364]
6. Absolute Maximum Ratings
Parameter
Symbol
AVDD
DVDD
VSS
VIN analog
VIN digital
Power Supply Voltage
Ground Level
Input Voltage
Input Current
IIN
(Except power supply pin)
Storage Temperature
Tstg
Note : All voltages are relative to the VSS pin.
Min.
-0.3
-0.3
0
-0.3
-0.3
Max.
6.5
6.5
0
AVDD+0.3
DVDD+0.3
Units
V
V
V
V
V
-10
+10
mA
-55
130
°C
Caution : Exceeding these maximum ratings can result in damage to the device.
Normal operation cannot be guaranteed under this extreme.
7. Recommended Operating Conditions
Parameter
Operating Temperature
Power Supply Voltage
Analog Reference Voltage
Symbol
Ta
AVDD
DVDD
AGND
Condition
DVDD ≤ AVDD
LDO in use
LDO not in use
Output Load Resistance
RL
AUDIOOUT, DISCOUNT,
NAMPO
Output Load Capacitance
CL
AUDIOOUT,
NAMPO
Min.
-40
2.6
2.6
Typ.
3.0
3.0
1.35
1/2VDD
Max.
85
5.5
5.5
30
Units
°C
V
V
V
V
kΩ
DISCOUNT,
15
pF
Max.
Units
Note : All voltages are relative to the VSS pin.
8. Digital DC Characteristics
Parameter
Symbol
Condition
Min.
High level input voltage
VIH
RSTN, SCLK, SDATA CSN 0.8DVDD
Low level input voltage
VIL
RSTN, SCLK, SDATA CSN
High level input current
IIH
Low level input current
IIL
High level output voltage
VOH
Low level output voltage
VOL
VIH=DVDD
RSTN, SCLK, SDATA CSN
VIL=0V
-10
RSTN, SCLK, SDATA CSN
IOH=+0.2mA
DVDD-0.4
SDATA
IOL=-0.4mA
0.0
SDATA, DETO
MS1431-E-01
Typ.
V
0.2DVDD
V
10
uA
uA
DVDD
V
0.4
V
2012/10
-7-
[AK2364]
9. Digital AC Timing
1) Serial Interface Timing
AK2364 is connected to a CPU by three-wired interface through CSN, SCLK and SDATA pins,
which can make reading and writing data for control registers.
Serial data named SDATA is consist of 1-bit read and write instruction(R/W), 6-bit address (A5 to
A0) and 8-bit data (D7 to D0) in one frame.
Write mode
CSN
SCLK
SDATA
(Input)
SDATA
R/W
A5
A4
A3
A2
A1
A0
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D5
D4
D3
D2
D1
D0
Hi-Z
(Output)
Read mode
CSN
SCLK
SDATA
(Input)
SDATA
Hi-Z
R/W
Hi-Z
D7
D6
(Output)
R/W
: Instruction bit controls to write data to AK2364 or read back from it.
When set to low, AK2364 is in write mode. When set to high,
AK2364 is in read mode.
A5 to A0: Register address to be accessed.
D7 to D0: Write or read date to be accessed.
<1>
CSN(Chip select) is normally selected high for disable.
When CSN is set to low, serial interface becomes active.
<2>
In write mode, instruction, address and data input from SDATA pin are synchronized and
latched with the rising edge of 16 iterations of SCLK clock. Set to low between address A0 and
data D7.Input data is fixed synchronized with the rising edge of 16th clock. Note that if CSN
become “H” before 16th clock, setting data becomes invalid. During the period when CSN is
set to “L”, consecutive writing is available.
<3>
In read mode, instruction and address are synchronized and latched with the rising edge of 7
iterations of SCLK clock. And the register data are output from SDATA pin synchronized with
the falling edge of 9 iterations of SCLK clock. The data between address A0 and data D7 is
unstable. During the period when data is output, input to SDATA must be “Hi-z”. Set CSN to
“H” once reading is completed because consecutive reading is not valid.
MS1431-E-01
2012/10
-8-
[AK2364]
2) Detail Timing Chart
Write mode
tCSLH
tCSS
tCSHH
CSN
tWH
tWL
SCLK
tDS
SDATA
(Input)
R/W
SDATA
(Output)
High-Z
tDH
A5
A4
A3
A0
D7
D6
D1
D0
Read mode
tCSLH
tCSS
tCD
CSN
tSD
tDD
SCLK
High-Z
SDATA
(Input)
R/W
SDATA
(Output)
High-Z
A5
A4
A1
A0
D7
D6
D1
D0
Rising and falling time
tR
tF
SCLK
VIH
VIL
Parameter
CSN setup time
SDATA setup time
SDATA hold time
SCLK high time
SCLK low time
CSN low hold time
CSN high hold time
SDATA Hi-Z setup time
SCLK to SDATA output delay
time
CSN to SDATA input delay
time
SCLK rising time
SCLK falling time
Symbol
tCSS
tDS
tDH
tWH
tWL
tCSLH
tCSHH
tSD
tDD
tCD
Condition
Min.
100
100
100
500
500
100
100
500
20pF load
20pF load
tR
tF
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
400
ns
200
ns
250
250
ns
ns
Note: Digital input and output timing is relative to 0.5DVDD of rising signal and falling signal.
MS1431-E-01
2012/10
-9-
[AK2364]
10. System Reset
Parameter
Symbol Condition
Hardware reset signal
tRSTN RSTN pin
input width
Typ.
Max.
1
SRST
register
Software reset
*1)
Min.
Unit
Remarks
us
*1)
*2)
After power-on, be sure to perform a hardware reset operation (register initialization). The
system is reset by a low pulse input of 1μs (min.) and enters the normal operation state. At this
moment, the digital (DI) pins are set as follows: RSTN pin to high, SCLK pin to Low, SDATA pin
to low, CSN pin to low.
tRSTN
VIH
RSTN
VIL
*2)
When data 0x03:10101010 is written to the SRST[7:0] register, software reset is performed.
This setting initializes the registers and the operation mode is set to mode 0 (power down).
After software reset is completed, this register comes to “0”.
MS1431-E-01
2012/10
- 10 -
[AK2364]
11. Power Consumption
Parameter
Symbol
IDD0
Consumption
Current
IDD1
IDD2
IDD3
Condition
Min.
Typ.
Max.
Units
10
μA
0.1
0.2
mA
0.6
1.4
mA
7.0
10
mA
Mode 0
Power down
Mode 1
Standby, AGN DIN
Mode 2
Standby, Lo buffer, VIREF
Mode 3
When no input signal
MS1431-E-01
2012/10
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[AK2364]
12. Analog Characteristics
For the following conditions unless otherwise specified: LOIN=50.4MHz,MIXIP=50.85MHz,
Δf=±1.5kHz, fmod=1kHz、AGC+BPF=F4, the exposure back pad of the package is connected to VSS,
with the external circuit shown in example page 21 to 24.
1) Local
Parameter
Symbol
Local Frequency
FLO
Condition
Min.
LOIN
Input amplitude
VLO
LOIN
Note) Input from LOIN pin through DC cut
2) 2nd Mixer
Parameter
Typ.
45.9
50.4
57.6
Max.
1.0
Min.
Typ.
VPP
Max.
Note)
Units
50
Ω
FLO
+0.45
MHz
Voltage Gain
23
dB
Noise Figure
13
dB
Input Impedance
Note)
Input Frequency
Notes
MHz
0.2
Condition
Units
Notes
Note)
Note) Include external matching circuit
3) Discriminator
Parameter
Demodulation
Output Level
S/N Ratio
Condition
Δf=±3.0kHz,fmod=1kHz,
LIMITER IN to AUDIOOUT Note)
Δf=±1.5kHz,fmod=1kHz,
LIMITER IN to AUDIOOUT Note)
Δf=±3.0kHz,fmod=1kHz,
LIMITER IN to AUDIOOUT Note)
Min.
Typ.
Max.
Units
60
100
140
mVrms
60
100
140
mVrms
50
dB
Notes
BAND
=1
BAND
=0
BAND
=1
Note) With De-emphasis＋BPF(0.3 to 3kHz)
4) RX Overall Characteristics
Parameter
12dB SINAD Input
Note)
Sensitivity
Condition
Min.
IIP3
Δf=±3.0kHz,fmod=1kHz,
AGC+BPF=F3
Δf=±1.5kHz,fmod=1kHz,
AGC+BPF=F4
Δf=±3.0kHz,fmod=1kHz,
AGC+BPF=F3
S/N Ratio
Δf=±1.5kHz,fmod=1kHz,
AGC+BPF=F4
Note)With De-emphasis＋BPF(0.3 to3kHz)
Demodulation
Output
Level
Note)
Note)
Note)
Note)
MS1431-E-01
Typ.
Max.
Units
-104
dBm
-16
dBm
60
100
140
mVrms
60
100
140
mVrms
40
46
dB
34
40
dB
Notes
BAND
=1
BAND
=0
BAND
=1
BAND
=0
2012/10
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[AK2364]
5) RSSI Characteristics
Parameter
Condition
MIXIP --> RSSIOUT
MIXIP=-100dBm Input
RSSI Output
Voltage
MIXIP --> RSSIOUT
MIXIP=-30dBm Input
Min.
Typ.
Max.
Units
0.1
0.36
0.62
V
1.4
2.0
2.6
V
Min.
Typ.
Max.
Units
0.5
0.7
V
Notes
RSSI Characteristics
(VDD=3V)
3.0
RSSI output lvel (V)
2.5
2.0
1.5
1.0
0.5
0.0
-120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10
0
Mixer input level (dBm)
6) Noise Squelch Characteristics
Parameter
Condition
NRECTO --> DETO
Noise Detect
Detect High
Level
NRECTO --> DETO
Detect Low
NAMPI --> NRECTO
Input: 31kHz, 0.1mVrms
Noise Detect
Characteristic
NAMPI --> NRECTO
Input: 31kHz, 0.25mVrms
0.3
0.4
0.1
0.26
0.36
V
0.4
0.65
0.8
V
Notes
V
Noise Detect Characteristics
NRECTO output level [V]
(VDD=3V, fin=31kHz)
1.6
1.2
0.8
0.4
0.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Filter amplifier input level [mVrms]
MS1431-E-01
2012/10
- 13 -
[AK2364]
7) AGC+BPF Characteristics
7.1) F1 (D type)
Parameter
Attenuation
Characteristics
Condition
Min.
Typ.
430kHz
(relative to the gain
at 450kHz)
7.2) F2 (E type)
Parameter
Attenuation
Characteristics
7.3) F3 (F type)
Parameter
Attenuation
Characteristics
460kHz
-6
dB
Condition
Min.
Typ.
435kHz
7.4) F4 (G type)
Parameter
Attenuation
Characteristics
(relative to the gain
at 450kHz)
3
dB
Max.
Units
-50
dB
dB
457.5kHz
-6
dB
Condition
Min.
Typ.
437.5kHz
-50
dB
3
dB
Max.
Units
-50
dB
444kHz
-6
dB
456kHz
-6
dB
Within 450±4kHz
Condition
Min.
439kHz
Typ.
-50
dB
3
dB
Max.
Units
-50
dB
445.5kHz
-6
dB
454.5kHz
-6
dB
461kHz
Gain Ripple
dB
-6
462.5kHz
Gain Ripple
-50
442.5kHz
Within 450±5kHz
(relative to the gain
at 450kHz)
dB
dB
465kHz
Gain Ripple
-50
-6
Within 450±7kHz
(relative to the gain
at 450kHz)
Units
440kHz
470kHz
Gain Ripple
Max.
Within 450±3kHz
MS1431-E-01
-50
dB
3
dB
Notes
Notes
Notes
Notes
2012/10
- 14 -
[AK2364]
BPF F1 (BW=±10kHz)
BPF F2 (BW=±7.5kHz)
10
10
500
Gain
0
500
Gain
0
G.D.T
G.D.T
-10
-10
400
-50
200
-60
-30
300
-40
-50
200
-60
-70
100
-70
-80
100
-80
430
435
440
445
450
455
460
465
470
0
475
-90
425
430
435
440
BPF F3 (BW=±6kHz)
10
450
455
460
465
470
0
475
BPF F4 (BW=±4.5kHz)
500
10
500
Gain
0
Gain
0
G.D.T
-10
400
G.D.T
-10
-20
400
300
-40
-50
200
-30
300
-40
-50
200
G.D.T[.μs]
-30
Gain[dB]
-20
G.D.T[.μs]
Gain [dB]
445
Frequency [kHz]
Frequency [kHz]
-60
-60
-70
100
-70
100
-80
-80
-90
425
G.D.T[.μs]
300
-40
Gain [dB]
-30
-90
425
400
-20
G.D.T[.μs]
Gain [dB]
-20
430
435
440
445
450
455
460
465
470
-90
425
0
475
Frequency [kHz]
430
435
440
445
450
455
460
465
470
0
475
Frequency [kHz]
MS1431-E-01
2012/10
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[AK2364]
13. Serial Interface Configuration
1) Register Configuration
Name
Control
register 1
ADRS D7(MSB)
D6
LDOSTAT PDLDON
D5
D4
D3
D2
BPF_BW[1:0]
LOFREQ[1:0]
0
0
D1
D0(LSB) W/R
BS[1:0]
0x01
W/R
1
0
0
Reserved
Control
register 2
0x02
Software
-reset
0x03
0
0
AGC_TIME[1:0]
0
0
1
0
1
AGC0_
STEP
BAND
CAL
1
0
0
⎯
⎯
⎯
0
W/R
SRST[7:0]
⎯
⎯
⎯
⎯
⎯
W
Note: Do not access the data except specified address above.
MS1431-E-01
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[AK2364]
2) Description of registers
Address 0x01 (Control Register 1)
Name
D7(MSB)
Control
Register 1
Initial Value
D6
D5
LDOSTAT PDLDON
1
0
D4
BPF_BW[1:0]
0
0
D3
D2
D1
LOFREQ[1:0]
0
1
D0(LSB)
BS[1:0]
0
1
LDO setting
Data
Function
LDO
STAT
PDLDON
Operation
0
1
Output status
In LDO power down
AVSS shorted
AVDD shorted
LDO power control
OFF
ON
Notes
BPF band width setting
BPF_BW
[1]
BPF_BW
[0]
name
6dB attenuation
0
1
F1
±10kHz
0
0
F2
±7.5kHz
1
0
F3
±6kHz
1
1
F4
±4.5kHz
Local frequency setting
LOFREQ
[1]
LOFREQ
[0]
Local frequency
0
0
45.9MHz
0
1
50.4MHz
1
0
57.6MHz
Note: Do no set the combination of the code which is not defined in the table given above.
Operation mode setting
Circuits except AGNDIN,
BS[1]
BS[0]
Mode name
AGNDIN
VIREF system
0
0
Mode0(Power-down)
OFF
OFF
OFF
0
1
Mode1(standby)
ON
OFF
OFF
1
0
Mode2
ON
ON
OFF
1
1
Mode3
ON
ON
ON
MS1431-E-01
LOBUF,VIREF
2012/10
- 17 -
[AK2364]
Address 0x02 (Control Register 2)
Name
D7(MSB) D6
Control
Reserved
Register 2
0
0
Initial Value
D5
D4
D3
D2
AGC_TIME[1:0]
0
0
0
AGC0_
STEP
1
D1
D0(LSB)
BAND
CAL
0
0
AGC_TIME[1:0] : AGC response time setting
This register set response time for AGC0 gain and AGC1 gain to change by 1step.
AGC response time [ms]
AGC_TIME
[1]
AGC_TIME
[0]
AGC0_STEP=0 setting
AGC0_STEP=1 setting
State A
State B
State C
State A
State B
State C
0
0
0.56
8.50
8.50
0.38
4.35
4.35
0
1
0.92
8.79
8.79
0.56
4.50
4.50
1
0
1.64
9.37
9.37
0.93
4.79
4.79
1
1
3.08
10.52
10.52
1.66
5.38
5.38
Note: Values above indicate response time during AGC gain changes from maximum to minimum or
from minimum to maximum.
Note: AGC response time differs according to the following states.
State A: AGC0 output level is beyond the upper limit.
State B: AGC0 output level is within the upper limit and AGC1 output level is beyond the upper limit.
State C: AGC1 output level is under the lower limit.
Data
Function
AGC0_
STEP
Operation
0
1
AGC0 gain switching
range setting
±1dB
±2dB
BAND
Demodulated signal
level setting (Note1)
NARROW
WIDE
CAL
Discriminator circuit
calibration start
trigger (Note2)
Invalid
Start
Notes
Note1: When {BAND} register is set to “0”, demodulated signal level at AUDIOOUT pin, when input
signal is Δf=±1.5kHz dev, is 100mVrms typ. When {BAND} register is set to “1”, demodulated signal
level at AUDIOOUT pin, when input signal is Δf=±3.0kHz dev, is 100mVrms typ.
Note2: calibration is performed synchronized with the rising edge of {CAL}. After calibration is
completed, this register is set to “0” automatically. It takes 1.3ms before calibration is completed.
Refer to “calibration procedure” for further information.
Address 0x03 (Software Reset)
Name
Software-reset
Initial Value
D7(MSB)
D6
D5
D4
D3
D2
D1
D0(LSB)
⎯
⎯
⎯
SRST[7:0]
⎯
⎯
⎯
⎯
⎯
When data 0x03:10101010 is written to the SRST[7:0] register, software reset is performed.
Refer to System Reset for further information.
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14. Calibration Procedure
1) AVDD=2.6 to 3.6V operation
When you use AK2364 in AVDD=2.6 to 3.6V operation, VREFA pin is connected to AVDD pin for
power supplying. Please set LDO (Low Drop Out) power off setting. Refer to 4-1) in page 22.
AK2364 employs a function to calibrate free-running frequency of VCO in Discriminator and
demodulated signal level. Before starting RX Operation, calibration is required in order to acquire
proper VCO operation range and demodulated signal level.
Following procedure is required before calibration in LDO power off setting.
<1> Start up the external TCXO and continuously supply LO signal to AK2364.
<2> Set “11” to 0x01 {BS[1:0]} and start up all circuits. After this operation, the circuits necessary
for calibration (LOBUF, VIREF and Discriminator) will be powered on and calibration can be
possible in 500us.
<3> Calibration is begun by setting "1" to address 0x02 {CAL}. When the calibration is executed
once, the calibration operation cannot be stopped excluding master reset. Even if "0" is written
in {CAL}, the calibration is completely executed.
<4> Calibration data is maintained excluding the time when the master reset is executed or DVDD
power supply is down.
<5> It takes 1.5ms for Discriminator to become steady after the calibration is completed.
Power-up sequence recommendation
LOIN（external）
{BS[1:0]}
Unstable
“11”
“01”
(500μs)
LOBUF
VIREF
Discriminator
Unstable
Stable
(1.3ms)
{CAL}
Reset itself automatically after calibration is completed
(1.5ms)
Unstable
Internal
Discriminator
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[AK2364]
2) AVDD=3.6 to 5.5V operation
When you use AK2364 in AVDD=3.6 to 5.5V operation, please set LDO power on setting.
Refer to 4-2) in page 23.
Following procedure is required before calibration in LDO power on setting.
<1> Start up the external TCXO and continuously supply LO signal to AK2364.
<2> Set “10” to 0x01 {BS[1:0]} and start up VIREF circuits. This makes LDO set power up standby.
<3> Set “0” to 0x01 {LDOSTAT} and LDO output shortened VSS once. This makes LDO power up
time shortly.
<4> Set “1” to 0x01 {LDOSTAT} and “1” to 0x01 {PDLDON}, then LDO power is on. It takes 130ms
for AGNDIN pin output voltage to become stable.
<5> Set “11” to 0x01 {BS[1:0]} and start up all circuits. After this operation, the circuits necessary for
calibration (LOBUF,VIREF and Discriminator) will be powered on and calibration can be
possible in 500us.
<6> Calibration is begun by setting "1" to address 0x02 {CAL}. When the calibration is executed
once, the calibration operation cannot be stopped excluding master reset. Even if "0" is written
in {CAL}, the calibration is completely executed.
<7> Calibration data is maintained excluding the time when the master reset is executed or DVDD
power supply is down.
<8> It takes 1.5ms for Discriminator to become stable after the calibration is completed.
Power-up sequence recommendation
LOIN（External）
Unstable
{BS[1:0]}
“10”
“01”
“11”
(100μs) (50μs)
{LDOSTAT}
(130ms)
{PDLDON}
AGNDIN
Unstable
{CAL}
Stable
(500μs)
LOBUF
VIREF
Discriminator
Unstable
Reset itself automatically after calibration is completed
Stable
(1.3ms)
(1.5ms)
Internal Discriminator
Unstable
Note: These values refer to the following recommended external application circuits.
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[AK2364]
15. Recommended External Application Circuits
1) Power supply stabilizing capacitors
Connect capacitors between VDD and VSS pins to eliminate ripple and noise included in power
supply. For maximum effect, the capacitors should be placed at a shortest distance between the
pins.
25
DVDD
C1=0.1μF (Ceramic cap)
C2
C1
C2=10μF (Electrolytic cap)
26
DVSS
4
AVDD
C1
2
C2
AVSS
LSI
2) AGND stabilizing capacitors
It is recommended that capacitors with 1μF or lager be connected between VSS and the AGND
and AGNDIN pins to stabilize the AGND signal. The capacitors must be placed as close to the
pins as possible.
17
AGNDOUT
18
AGNDIN
C1
AVSS
C1=1μF (Electrolytic capacitor)
C1
AVSS
LSI
3) BIAS
16
BIAS
R1
R1=47kΩ±1%
AVSS
LSI
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[AK2364]
4-1) VREFA (AVDD=2.6 to 3.6V operation)
3
VREFA
4
AVDD
LSI
4-2) VREFA (AVDD=3.6 to 5.5V operation)
3
VREFA
C1=220nF
C1
AVSS
LSI
5) MIX
MIXIP
1
C2
C1
R1
L1
IF_INPUT
C1=18pF, L1=470nF for 46.35MHz
C1=15pF, L1=470nF for 50.85MHz
C1=12pF, L1=390nF for 58.05MHz
C2=10nF
R1=2.4kΩ
LSI
6) LOIN
LOIN
28
LO_INPUT
C1
C2
27
C1=C2=100pF
LOCAP
AVSS
LSI
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[AK2364]
7) Discriminator
10
R1
PDOUT
C1=1000pF
C1
R1=220kΩ
11
DISCOUT
R2=1MΩ
R2
LSI
8) Noise AMP
The following gives a sample configuration of a BPF when input frequency is 31 kHz.
Some parameters can be calculated using following (1) to (3) equations.
14
NAMPO
C1=0.47uF
C2
C2=C3=220pF
R3
R1 C1
C3
_
+
13
NAMPI
R2
Noise Amp
R1=10kΩ
R2=5.6KΩ
AVSS
R3=150kΩ
LSI
(1) f 0 =
1
2π R3 ( R1 // R2 )C 2
( 2) Gv =
R3
2 R1
(3) Q 2 =
R3
4( R1 // R2 )
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[AK2364]
9) NECTO
Rise time of noise detection is proportionate to C1=0.1uF and internal resistance 75kΩ
15
NRECTO
C1
C1=0.1μF
AVSS
LSI
10) RSSIOUT
9
RSSIOUT
C1
R1
R1=51kΩ
C1=1000pF
AVSS
LSI
11) DETO
DVDD
24
DETO
R1
R1=100kΩ
LSI
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[AK2364]
16. Packaging
□ Marking
2364
YWWL
●
［Contents of YWWL］
Y： Last digit of calendar year. (Year 2011->1, 2012->2)
WW: Manufacturing week number.
L: Lot identification, given to each product lot which is made in a week.
LOT ID is given in alphabetical order (A, B, C…).
□ Mechanical Outline
Package：28pin QFN
(4.0 x 4.0 x 0.7mm, 0.4mm pitch)
2.30±0.10
B
21
15
22
28
8
7
A
0.40±0.05
2.30±0.10
4.00±0.05
14
1
C0.3
4.00±0.05
0.07 M
C A
B
0.18±0.05
0.75±0.05
0.40 Ref
0.05 MAX
0.08 C
C
Note）The exposure pad(Exposed Pad）of the center of the package back is connected to opening
or VSS.
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[AK2364]
17. Important Notice
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales
office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current
status of the products.
z Descriptions of external circuits, application circuits, software and other related information
contained in this document are provided only to illustrate the operation and application examples
of the semiconductor products. You are fully responsible for the incorporation of these external
circuits, application circuits, software and other related information in the design of your
equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising
from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export
license or other official approval under the law and regulations of the country of export pertaining
to customs and tariffs, currency exchange, or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any
safety, life support, or other hazard related device or systemNote2), and AKM assumes no
responsibility for such use, except for the use approved with the express written consent by
Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be
expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of
the device or system containing it, and which must therefore meet very high standards of
performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or
maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other
fields, in which its failure to function or perform may reasonably be expected to result in loss
of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or
otherwise places the product with a third party, to notify such third party in advance of the above
content and conditions, and the buyer or distributor agrees to assume any and all responsibility
and liability for and hold AKM harmless from any and all claims arising from the use of said
product in the absence of such notification.
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