ETC UCC284DP

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ
LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR
SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002
D Precision Negative Series Pass Voltage
D
D
D
D
D
D
DP PACKAGE
(FRONT VIEW)
Regulation
0.2 V Dropout at 0.5 A
Wide Input Voltage Range –3.2 V to –15 V
Low Quiescent Current Irrespective of Load
Simple Logic Shutdown Interfacing
–5 V, –12 V, and Adjustable Output
2.5% Duty Cycle Short Circuit Protection
VOUTS 1
8
SD/CT
VIN 2
7
VIN
VIN
3
6
VIN
GND
4
5
VOUT
description
The UCC384-x family of negative linear-series pass regulators is tailored for low-dropout applications where
low-quiescent power is important. Fabricated with a BCDMOS technology ideally suited for low input-to-output
differential applications, the UCC384-x passes 0.5 A while requiring only 0.2 V of input-voltage headroom.
Dropout voltage decreases linearly with output current, so that dropout at 50 mA is less than 20 mV.
Quiescent current consumption for the device under normal (non-dropout) conditions is typically 200 µA. An
integrated charge pump is internally enabled only when the device is operating near dropout with low VIN. This
ensured that the device meets the dropout specifications even for maximum load current and a VIN of –3.2 V
with only a modest increase in quiescent current. Quiescent current is always less than 350 µA, with the charge
pump enabled. The quiescent current of the UCC384 does not increase with load current.
Short-circuit current is internally limited. The device responds to a sustained overcurrent condition by turning
off after a tON delay. The device then stays off for a period, tOFF, that is 40 times the tON delay. The device then
begins pulsing on and off at the tON/tOFF duty cycle of 2.5%. This drastically reduces the power dissipation during
short circuit such that heat sinking, if at all required, must only accommodate normal operation. An external
capacitor sets the on time. The off time is always 40 times tON.
The UCCx84-x can be shutdown to 45 µA (maximum) by pulling the SD/CT pin more positive than –0.7 V. To
allow for simpler interfacing, the SD/CT pin may be pulled up to 6 V above the ground pin without turning on
clamping diodes.
Internal power dissipation is further controlled with thermal-overload protection circuitry. Thermal shutdown
occurs if the junction temperature exceeds 140°C. The chip remains off until the temperature has dropped 20°C
(TJ = 120°C).
AVAILABLE OPTIONS
TA
– 40°C
40 C to 85°C
85 C
0°C to 70°C
OUTPUT VOLTAGE (V)
PACKAGE DEVICES
TYP
(SOIC) DP
–5
UCC284DP–5
–12
UCC284DP–12
ADJ
UCC284DP–ADJ
–5
UCC384DP–5
–12
UCC384DP–12
ADJ
UCC384DP–ADJ
† All package types are available taped and reeled. Add TR suffix to device type
(e.g. UCC284DP–5TR) to order quantities of 3000 devices per reel.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ
LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR
SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002
functional block diagram
(+)
1– µ A
DISCHARGE
UCC384–ADJ
+
SHUTDOWN
–2.2 V
–0.7 V
R1
R2
0
OPEN
UCC384–5
375K
125K
UCC384–12
375K 43.6K
1.25 V
50 k
4
GND
1
VOUTS
5
VOUT
R2
+
–1.6 V
SD/CT
S
Q
R
Q
TON
8
–2.6 V
+
TOFF
VPUMP
+
GM
40 µA
CHARGE
R1
OVERCURRENT
700 mA
+
VIN
2
VIN
3
VIN
6
VIN
7
THERMAL
SHUTDOWN
UVLO
(–)
(–)
UDG–99030
absolute maximum ratings over operating free-air temperature (unless otherwise noted)Ĕ}
Input voltage range‡, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –16 V
Shutdown voltage range, SD/CT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to 6 V
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
Storage temperature range Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature (Soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltages are with respect to ground. Currents are positive into and negative out of the specified terminals.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ
LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR
SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002
electrical characteristics TA = 0°C to 70°C for the UCC384 and –40°C to 85°C for the UCC284,
VIN = VOUT – 1.5 V, IOUT = 0 mA, COUT = 4.7 µF, and CT = 0.015 µF. For UCC384–ADJ, VOUT is set
to –3.3V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
–4.925
V
UCC384–5 Fixed –5-V 0.5-A Regulation Section
–5.075
–5
Output voltage
TA = 25°C
Over all conditions
Line regulation
VIN = –5.2 V to –15 V
1.5
10
Load regulation
IOUT = 0 mA to 0.5 A
TA = 25°C,
BW = 10 Hz to 10 kHz
0.1
0.25
200
Output noise voltage
Dropout voltage
voltage, VOUT – VIN
IOUT 0.5 A,
IOUT 50 mA,
–5.100
–4.850
V
mV
%
µVRMS
VOUT = –4.8 V
0.20
0.50
VOUT = –4.8 V
20
50
V
mV
UCC384–5 Fixed –5-V 0.5-A Power Supply Section
Input voltage range
–15
Quiescent current charge pump on
VIN = –4.85 V,
Quiescent current
VIN = –15 V
Quiescent current in shutdown
VIN = –13 V,
TA = 0°C to 85°C,
See Note 1
SD/CT = 0 V
See Note 2
Shutdown threshold
VIN = –13 V,
SD/CT = 0 V
TA = –40°C to 0°C, See Note 2
At shutdown pin (SD/CT)
Shutdown input current
SD/CT = 0 V
Output leakage in shutdown
VIN = –15 V,
See Note 3
–5.2
V
280
350
µA
200
250
µA
15
45
µA
100
µA
–1.0
–0.7
–0.4
V
5
10
25
µA
1
50
µA
VOUT = 0 V,
Overtemperature shutdown
140
°C
Overtemperature hysteresis
20
°C
UCC384–5 Fixed –5-V 0.5-A Current Limit Section
Peak current limit
VOUT = 0 V
Overcurrent threshold
Current limit duty cycle
VOUT = 0 V
Overcurrent time out, tON
VOUT = 0 V
0.7
1.1
1.5
A
0.55
0.7
0.9
A
2.5
4
%
300
500
700
µs
–12.18
–12
–11.82
V
UCC384–12 Fixed 12-V 0.5-A Regulation Section
Output voltage
TA = 25°C
Over all conditions
Line regulation
VIN = –12.5 V to –15 V
Load regulation
IOUT= 0 mA to 0.5 A
TA = 25°C
BW = 10 Hz to 10 kHz
Output noise voltage
Dropout voltage
voltage, VOUT – VIN
IOUT 0.5 A,
IOUT 50 mA,
–12.24
–11.64
5
15
0.1
0.3
V
mV
%
µVRMS
200
VOUT = –11.6 V
0.15
0.5
V
VOUT = –11.6 V
15
50
mV
UCC384–12 Fixed –12 V-0.5-A Power Supply Section
Input voltage range
Quiescent current
Quiescent current in shutdown
–15
VIN = –15 V
VIN = –13 V,
TA = 0°C to 85°C,
SD/CT = 0 V
See Note 2
–12.5
V
220
350
µA
15
45
µA
VIN = –13 V,
SD/CT = 0 V
100
µA
TA = –40°C to 0°C, See Note 2
NOTES: 1. The internal charge pump is enabled only for dropout condition with low VIN. Only in this condition is the charge pump required to
provide additional output FET fate drive to maintain dropout specifications. For conditions where the charge pump is not required,
it is disabled, which lowers overall device power consumption.
2. Ensured by design. Not production tested.
3. In the application during shutdown mode, output leakage current adds to quiescent current.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ
LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR
SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002
electrical characteristics TA = 0°C to 70°C for the UCC384 and –40°C to 85°C for the UCC284,
VIN = VOUT – 1.5 V, IOUT = 0 mA, COUT = 4.7 µF, and CT = 0.015 µF. For UCC384–ADJ, VOUT is set
to –3.3V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
UCC384–12 Fixed –12 V-0.5-A Power Supply Section (continued)
Shutdown threshold
At shutdown pin (SD/CT)
Shutdown input current
SD/CT = 0 V
Output leakage in shutdown
VIN = –15 V,
See Note 3
–1.0
–0.7
–0.4
V
5
10
25
µA
1
50
µA
VOUT = 0 V,
Overtemperature shutdown
140
°C
Overtemperature hysteresis
20
°C
UCC384–12 Fixed –12-V 0.5-A Current Limit Section
Peak current limit
VOUT = 0 V
Overcurrent threshold
Current limit duty cycle
VOUT = 0 V
Overcurrent time out, tON
VOUT = 0 V
0.7
1.1
1.5
0.55
0.7
0.9
A
A
2.5
4
%
300
500
700
µs
–1.27
–1.25
–1.23
V
UCC384–ADJ Adjustable 0.5-A Regulation Section
Reference voltage
TA = 25°C
Over temperature
Line regulation
VIN = –3.5 V to –15 V,
Load regulation
IOUT = 0 mA to 0.5 A
BW = 10 Hz to 10 kHz,
Output noise voltage
Dropout voltage
voltage, VOUT – VIN
IOUT 0.5 A,
IOUT 50 mA,
–1.275
–1.215
V
VOUT = VOUTS
0.5
3
0.1
0.18
TA = 25°C
VOUT = –3.15 V
200
0.25
0.5
V
VOUT = –3.15 V
25
50
mV
100
250
nA
–3.5
V
Sense pin input current
mV
%
µVRMS
UCC384–ADJ Adjustable 0.5-A Power Supply Section
Input voltage range
–15
Undervoltage lockout
–3.2
Quiescent current charge pump on
VIN = –3.15 V,
Quiescent current
VIN = –15 V
Quiescent current in shutdown
VIN = –13 V,
TA = 0°C to 85°C,
See Note 1
SD/CT = 0 V
See Note 2
Shutdown threshold
VIN = –13 V,
SD/CT = 0 V
TA = –40°C to 0°C, See Note 2
At shutdown pin (SD/CT)
Shutdown input current
SD/CT = 0V
Output leakage in shutdown
VIN = –15V,
See Note 3
–2.95
–2.7
V
200
350
µA
200
250
µA
15
45
µA
100
µA
–1.0
–0.7
–0.4
V
5
10
25
µA
1
50
µA
VOUT = 0 V,
Overtemperature shutdown
140
°C
Overtemperature hysteresis
20
°C
UCC384–ADJ Adjustable 0.5-A Current Limit Section
Peak current limit
VOUT = 0 V
Overcurrent threshold
Current limit duty cycle
VOUT = 0 V
Overcurrent time out, tON
VOUT = 0 V
0.7
1.1
1.5
A
0.55
0.7
0.9
A
2.5
4
%
300
500
700
µs
NOTES: 1. The internal charge pump is enabled only for dropout condition with low VIN. Only in this condition is the charge pump required to
provide additional output FET fate drive to maintain dropout specifications. For conditions where the charge pump is not required,
it is disabled, which lowers overall device power consumption.
2. Ensured by design. Not production tested.
3. In the application during shutdown mode, output leakage current adds to quiescent current.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ
LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR
SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002
pin descriptions
GND: This is the low noise ground reference input. All voltages are measured with respect to the GND pin.
SD/CT: This is the shutdown pin and also the short-circuit timing pin. Pulling this pin more positive than –0.7 V
puts the circuit in a low-current shutdown mode. Placing a timing capacitor between this pin and GND sets the
short-circuit charging time, tON during an overcurrent condition. During an overcurrent condition, the output
pulses at approximately a 2.5% duty cycle.
NOTE:The CT capacitor must be connected between this pin and GND, not VIN, to assure that the
SD/CT pin is not pulled significantly negative during power-up. This pin should not be externally
driven more negative than –5 V or the device will be damaged.
VIN: This is the negative input supply. Bypass this pin to GND with at least 1 µF of low ESR or ESL capacitance.
VOUT: Regulated negative-output voltage. A single 4.7-µF capacitor should be connected between this pin and
GND. Smaller value capacitors can be used for light loads, but this degrades the load-step performance of the
regulator.
VOUTS: This is the feedback pin for sensing the output of the regulator. For the UCC384-5 and UCC384-12
versions, VOUTS can be connected directly to VOUT. If the load is placed at a considerable distance from the
regulator, the VOUTS lead can be used as a Kelvin connection to minimize errors due to lead resistance.
Connecting VOUTS at the load moves the resistance of the VOUT wire into the control loop of the regulator,
thereby effectively canceling the IR drop associated with the load path.
APPLICATION INFORMATION
overview
The UCCx84-x family of negative low-dropout linear (LDO) regulators provides a regulated-output voltage for
applications with up to 0.5 A of load current. The regulators feature a low-dropout voltage and short-circuit
protection, making their use ideal for demanding applications requiring fault protection.
programming the output voltage on the UCC384
The UCC384-5 and UCC384-12 have output voltages that are fixed at –5 V and –12 V respectively. Connecting
VOUTS to VOUT gives the proper output voltage with respect to ground.
The UCC384-ADJ can be programmed for any output voltage between –1.25 V and –15 V. This is easily
accomplished with the addition of an external resistor divider connected between GND and VOUT with VOUTS
connected to the center tap of the divider. For an output of –1.25 V, no resistors are needed and VOUTS is
connected directly to VOUT. The regulator-input voltage cannot be more positive than the UVLO threshold, or
approximately –3 V. Thus, low dropout cannot be achieved when programming the output voltage more positive
than approximately –3.3 V. A typical application circuit is shown in Figure 1.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ
LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR
SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002
APPLICATION INFORMATION
programming the output voltage on the UCC384 (continued)
(+)
(+)
CT
0.015µF
4
R2
GND
8
SD/CT
VOUTS 1
CIN
+ 1 µF
VIN
COUT
4.7µF
C1
UCC384–ADJ
VOUT
VIN
VIN
VIN
VIN
2
3
6
7
VOUT
+
R1
5
(–)
(–)
UDG–99029
Figure 1. Typical Application Circuit
For the UCC384–ADJ, the output voltage is programmed by the following equation:
VOUT + * 1.25
ǒ1 ) R1
Ǔ
R2
(1)
When R1 or R2 are selected to be greater than about 100 kΩ, a small ceramic capacitor should be placed across
R1 to cancel the input pole created by R1 and the parasitic capacitance appearing on VOUTS. Values of
approximately 20 pF should be adequate.
dropout performance
The UCC384 is tailored for low-dropout applications where low-quiescent power is important. Fabricated with
a BCDMOS technology ideally suited for low input-to-output differential applications, the UCC384 passes 0.5 A
while requiring only 0.2 V of headroom. The dropout voltage is dependent on operating conditions such as load
current, input and load voltages, and temperature. The UCC384 achieves a low RDS(on) through the use of an
internal charge-pump that drives the MOSFET gate.
Figure 2 shows typical dropout voltages versus output voltage for the UCC384-5 V and -12 V versions as well
as the UCC384–ADJ version programmed between –3.3 V and –15 V. Since the dropout voltage is also affected
by output current, Figure 3 shows typical dropout voltages versus load current for different values of VOUT.
Operating temperatures also affect the RDS(on) and the dropout voltage of the UCC384. Figure 4 shows typical
dropout voltages for the UCC384 over temperature under a full load of 0.5 A.
short-circuit protection
The UCC384 provides unique short-circuit protection circuitry that reduces power dissipation during a fault.
When an overcurrent condition is detected, the device enters a pulsed mode of operation, limiting the output
to a 2.5% duty cycle. This reduces the heat sink requirements during a fault. The operation of the UCC384 during
an overcurrent condition is shown in Figure 5.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ
LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR
SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002
APPLICATION INFORMATION
short-circuit protection (continued)
DROPOUT VOLTAGE
vs
OUTPUT VOLTAGE
IOUT = 0.4 A
0.20
IOUT = 0.5 A
0.15
0.10
0.05
IOUT = 0.2 A
(VIN–VOUT) – Dropout Voltage – V
0.25
IOUT = 0.3 A
0.25
VOUT = –5 V
0.20
VOUT = –3.3 V
0.15
0.10
VOUT = –12 V
0.05
VOUT = –15 V
IOUT = 0.1 A
0.00
3
6
9
12
VOUT – Output Voltage – V
0.05
15
0.15
0.25
0.35
IOUT – Load Current – A
0.45
Figure 3
Figure 2
DROPOUT VOLTAGE
vs
TEMPERATURE
0.40
(VIN–VOUT) – Dropout Voltage – V
(VIN–VOUT) – Dropout Voltage – V
0.30
DROPOUT VOLTAGE
vs
LOAD CURRENT
0.35
VOUT = –3.3 V
0.30
VOUT = –5 V
0.25
0.20
VOUT = –12 V
0.15
0.10
VOUT = –15 V
0.05
0
–50
–25
0
25
50
75
100
TA – Free-Air Temperature – _C
Figure 4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ
LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR
SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002
APPLICATION INFORMATION
t OFF
t OFF
t ON
t ON
t ON
IOUT=0A
~40 x tON
~40 x tON
IOUT (NOM)
IOVER
IPEAK
NOTE: CURRENT FLOW IS INTO THE DEVICE
VOUT = 0V
VOUT
=(IPEAK)(RL)
VOUT NOM. (–V)
CT = 0V
CT (NOM) = – 1.6V
CT = – 2.6V
UDG–99031
Figure 5. Short Circuit Timing
UCC384 short circuit timing
During normal operation the output voltage is in regulation and the SD/CT pin is held to –1.5 V via a 50-kΩ
internal-source impedance. If the output-current rises above the overcurrent threshold, the CT capacitor is
charged by a 40-µA current sink. The voltage on the SD/CT pin moves in a negative direction with respect to
GND.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ
LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR
SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002
APPLICATION INFORMATION
UCC384 short-circuit timing (continued)
During an overcurrent condition, the regulator actively limits the maximum output current to the peak-current
limit. This limits the output voltage of the regulator to:
V
OUT
+I
PEAK
R
(1)
L
If the output current stays above the overcurrent threshold, the voltage on the SD/CT pin reaches –2.6 V with
respect to GND and the output turns off. The CT capacitor is then discharged by a 1-µA current source. When
the voltage on the SD/CT pin reaches –1.6 V with respect to GND, the output turns back on. This process repeats
until the output current falls below the overcurrent threshold.
tON, the time the output is on during an overcurrent condition is determined by the following equation:
t
ON
1 V seconds
40 mA
+ CT (mF)
(2)
tOFF, the time the output is off during an overcurrent condition is determined by the following equation:
t
OFF
+ CT (mF)
1 V seconds
1 mA
(3)
capacitive loads
A capacitive load on the regulator’s output appears as a short-circuit during start-up. If the capacitance is too
large, the output voltage does not begin to regulate during the initial tON period and the UCC384 enters a pulsed
mode operation. For a constant current load the maximum allowed output capacitance is calculated as follows:
C
OUT(max)
ƪ PEAK(A) * ILOAD(A)ƫ
+ I
t
(sec)
ON
Farads
V
(V)
OUT
(4)
For worst case calculations, the minimum value for tON should be used, which is based on the value of CT
capacitor selected. For a resistive load the maximum output capacitor can be estimated as follows:
C
OUT(max)
t
+
R
LOAD
(W)
(sec)
ON
ȡ
ȧ
ȏnȧ
ȧ1
Ȣ
*
ȣ
ȧ
1
ȧ
V
(V)
OUT
ǒIMAX(A) RLOAD(W)ǓȧȤ
Farads
(5)
Figure 6 and Figure 7 are oscilloscope photos of the UCC384–ADJ operating during an overcurrent condition.
Figure 6 shows operation of the circuit as the output current initially rises above the overcurrent threshold. This
is shown on a 1ms/div. scale. Figure 7 shows operation of the same circuit on a 25 ms/div. scale showing one
complete cycle of operation during an overcurrent condition.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ
LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR
SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002
APPLICATION INFORMATION
UCC384–ADJ
OVERCURRENT CONDITION OPERATION
1 ms/div
UCC384–ADJ
OVERCURRENT CONDITION OPERATION
25 ms/div
Figure 6
Figure 7
shutdown feature of the UCC384
The shutdown feature of the UCC384 allows the device to be placed in a low quiescent current mode. The
UCC384 is shut down by pulling the SD/CT pin more positive than –0.7 V with respect to GND. Figure 8 shows
how a shutdown circuit can be configured for the UCC384 using a standard transistor-transistor logic signal to
control it.
TTL SHUTDOWN CIRCUIT
+5 V
+5 V
LOGIC
INPUT
470 k
GND
(+)
(+)
0.015µF
CT
4
R2
GND
8 SD/CT
+
VIN
CIN
VOUTS
VOUT
VIN
VIN
VIN
VIN
2
3
6
7
VOUT
COUT
4.7µF
C1
UCC384–ADJ
1 µF
+
1
5
R1
(–)
(–)
UDG–99032
Figure 8. TTL Controlled Shutdown Circuit for the UCC384
10
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UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ
LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR
SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002
APPLICATION INFORMATION
controlling the SD/CT pin
Forcing the SD/CT pin to any fixed voltage affects the operation of the circuit. As mentioned before, pulling the
SD/CT pin more positive than –0.7 V puts the circuit in a shutdown mode, limiting the quiescent current to less
than 45 µA. Pulling this pin more positive than 6 V with respect to GND damages the device.
Forcing the SD/CT pin to any fixed voltage between –0.7 V and –1.6 V with respect to GND enables the output.
However, in an overcurrent condition, the output does not pulse at a 2.5% duty cycle, but the output current is
still limited to the peak current limit. This circuit may be used where a fixed current limit is needed, where a 2.5%
duty cycle is undesirable. The UCC384 supplies a maximum current in this configuration as long as the
temperature of the device does not exceed the overtemperature shutdown. This is determined by the peak
current being supplied, the input and output voltages, and the type of heat sink being used. Thermal design
is discussed later on in this data sheet.
Forcing the SD/CT pin to a voltage level between approximately –1.6 V and –2.6 V with respect to GND is not
recommended as the output may or may not be enabled.
Forcing the SD/CT pin to a voltage level between approximately –2.6 V and –5 V with respect to GND turns the
output off completely. The output remains off as long as the voltage is applied. Pulling this pin more negative
than –5 V with respect to GND damages the device (see Table 1).
Table 1 SD/CT Voltage Levels
SD/CT
6 V to –0.7 V
STATE
Output disabled and device in low quiescent shutdown mode.
–0.7 V to –1.6 V
Output enabled
–1.6 V to –2.6 V
Output enabled or disabled depending on the previous state.
–2.6 V to –5 V
Output disabled
VIN TO VOUT DELAY TIME
DURING POWER-UP WITH CT = 0.22 µF
Figure 9
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UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ
LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR
SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002
APPLICATION INFORMATION
VIN to VOUT Delay
During power-up there is a delay between VIN and VOUT. The majority of this delay time is due to the charging
time of the CT capacitor. When VIN moves more negative than the UVLO of the device with respect to GND,
the CT capacitor begins to charge. A 17-µA current sink is used only during power up to charge the CT capacitor.
When the voltage on the SD/CT pin reaches approximately –1.6 V with respect to GND, the output turns on and
regulates. The larger the value of the CT capacitor, the greater the delay time between VIN and VOUT. Figure 9
shows the VIN to VOUT start-up delay, approximately 16 ms for a circuit with CT = 0.22 µF.
Shorter delay times can be achieved with a smaller CT capacitor. The problem with a smaller CT capacitor is
that with a very large load, the circuit may stay in overcurrent mode and never turn on. A circuit with a large
capacitive load needs a large CT capacitor to operate properly.
One way to shorten the delay from VIN to VOUT during powerup, is with the use of the quick start-up circuit
shown in Figure 10.
(+)
(+)
R2
4
CT
0.22µF
GND
8 SD/CT
VIN
+ CIN
1 µF
+
COUT
4.7µF
VOUTS 1
C1
R4
18 k
C2
0.1µF
UCC384–ADJ
VOUT
R1
VOUT 5
(–)
Q1
2N7000
R3
12 k
VIN
VIN
VIN
VIN
2
3
6
7
(–)
QUICK START CURRENT
UDG–99033
Figure 10. Quick Start-Up Circuit for UCC384
With the quick start-up circuit, the delay time between VIN and VOUT during start-up can be reduced
dramatically. Figure 11 shows that with the quick start-up circuit, the VIN to VOUT delay time has been reduced
to approximately 1 ms.
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UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ
LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR
SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002
APPLICATION INFORMATION
VIN to VOUT Delay
VIN TO VOUT DELAY TIME
WITH QUICK START-UP CIRCUIT
VIN TO VOUT DELAY TIME
WITH CT CAPACITOR REMOVED
Figure 11
Figure 12
operation of the quick start-up circuit
During normal start-up, the UCC384 does not turn on until the voltage on the SD/CT pin reaches approximately
–1.6 V with respect to ground. It takes a certain amount of time for the CT capacitor to charge to this point. For
a circuit that has a very large load, the CT capacitor needs to be large in order for the overcurrent timing to work
properly. A large value of capacitance on the SD/CT pin increases the VIN to VOUT delay time.
The quick start-up circuit uses Q1 to quickly pull the SD/CT pin in a negative direction during start-up, thus
decreasing the VIN-to-VOUT delay time. When VIN is applied to the circuit, Q1 turns on and starts to charge
the CT capacitor. The current pulled through R4 determines the rate at which CT is charged. R4 can be
calculated as follows:
V (V)
R4 + IN
1.6
T
seconds
D
ohms
CT (F)
(6)
tD is the approximate VIN-to-VOUT delay time desired.
Q1 needs to be turned off after a fixed time to prevent the SD/CT pin from going too far negative with respect
to GND. If the SD/CT pin is allowed to go too far negative with respect to GND, the output turns off again or
possibly even damages the SD/CT pin. The maximum amount of time that Q1 should be allowed to be on is
referred to as tM and can be calculated as follows:
t
M
+ 2.6
1.6
t
D
(7)
seconds
R3 along with C2 set the time that Q1 is allowed to be on. Since tM is the maximum amount of time that Q1 should
be allowed to stay on, an added safety margin may be to use 0.9 × tM instead. This ensures that Q1 is turned
off in the proper amount of time. With a chosen value for C2, R3 can be calculated as follows:
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LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR
SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002
APPLICATION INFORMATION
operation of the quick start-up circuit (continued)
0.9
R3 +
C2(F)
ȏn
t
ǒ
M
seconds
Ǔ
V
(8)
Ohms
(V)*1.6
1 * IN
V (V)
IN
After the CT capacitor has charged up for a time equal to 0.9 × tM , Q1 turns off and allows the SD/CT pin to
be pulled back to –1.5 V with respect to GND through a 50-kΩ resistor. At this point , the SD/CT pin can be used
by the UCC384 overcurrent timing control.
minimum VIN to VOUT delay time
Although it may desirable to have as short a delay time as possible, a small portion of this delay time is fixed
by the UCC384 and cannot be shortened. This is shown in Figure 12, where the CT capacitor has been removed
from the circuit completely, giving a fixed VIN to VOUT delay of approximately 150 µs for a circuit with VIN = –6 V
and VOUT = –5 V.
thermal design
The Packaging Information section of the Power Supply Control Products Data Book (TI Literature
No. SLUD003) contains reference material for the thermal ratings of various packages. The section also
includes an excellent article entitled Thermal Characteristics of Surface Mount Packages, which is the basis
for the following discussion.
Thermal design for the UCC384 includes two modes of operation, normal and pulsed. In normal mode, the linear
regulator and heat sink must dissipate power equal to the maximum forward voltage drop multiplied by the
maximum load current. Assuming a constant current load, the expected heat rise at the regulator’s junction can
be calculated as follows:
t
RISE
+P
DISS
(qjc ) qca)
(9)
Theta (θ) is the thermal resistance and PDISS is the power dissipated. The junction-to-case thermal resistance
(θjc) of the SOIC–8 DP package is 22°C/W. In order to prevent the regulator from going into thermal shutdown,
the case-to-ambient thermal resistance (θca) must keep the junction temperature below 150°C. If the UCC384
is mounted on a 5 square inch pad of 1-ounce copper, for example, the thermal resistance (θja) becomes
40–70°C/W. If a lower thermal resistance is required for the application, the device heat sinking needs to be
improved.
When the UCC384 is in a pulsed mode, due to an overcurrent condition, the maximum average power
dissipation is calculated as follows:
ƪ
P avg + V
(V) * V
(V)
IN
OUT
ƫ
I
(A)
PEAK
ǒ
t
(seconds)
ON
40 t
(seconds)
ON
Ǔ
Watts
(10)
As seen in equation (10), the average power during a fault is reduced dramatically by the duty cycle, allowing
the heat sink to be sized for normal operation. Although the peak power in the regulator during the tON period
can be significant, the thermal mass of the package normally keeps the junction temperature from rising unless
the tON period is increased to several milliseconds.
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