TI UCC284SDR-5EP

UCC284-EP
www.ti.com ....................................................................................................................................... SLVS862A – NOVEMBER 2008 – REVISED NOVEMBER 2008
LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR
FEATURES
1
•
•
•
•
•
•
Precision Negative Series Pass Voltage
Regulation
0.2-V Dropout at 0.5 A
Wide Input Voltage Range –3.2 V to –15 V
Low Quiescent Current Irrespective of Load D
Simple Logic Shutdown Interfacing
–5 V, –12 V, and Adjustable Output
2.5% Duty Cycle Short Circuit Protection
SUPPORTS DEFENSE, AEROSPACE AND
MEDICAL APPLICATIONS
•
•
•
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in S-Temp (–55°C/100°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
(1)
Additional temperature ranges are available – contact factory.
D PACKAGE
(FRONT VIEW)
VOUTS
1
8
SD/CT
VIN
2
7
VIN
VIN
3
6
VIN
GND
4
5
VOUT
DESCRIPTION
The UCC284-x family of negative linear-series pass regulators is tailored for low-dropout applications where
low-quiescent power is important. Fabricated with a BCDMOS technology ideally suited for low input-to-output
differential applications, the UCC284-x passes 0.5 A while requiring only 0.2 V of input-voltage headroom.
Dropout voltage decreases linearly with output current, so that dropout at 50 mA is less than 20 mV.
Quiescent current consumption for the device under normal (non-dropout) conditions is typically 200 µA. An
integrated charge pump is internally enabled only when the device is operating near dropout with low VIN. This
ensured that the device meets the dropout specifications even for maximum load current and a VIN of –3.2 V
with only a modest increase in quiescent current. Quiescent current is always less than 360 µA, with the charge
pump enabled. The quiescent current of the UCC284 does not increase with load current.
Short-circuit current is internally limited. The device responds to a sustained overcurrent condition by turning off
after a tON delay. The device then stays off for a period, tOFF, that is 40 times the tON delay. The device then
begins pulsing on and off at the tON/tOFF duty cycle of 2.5%. This drastically reduces the power dissipation during
short circuit such that heat sinking, if at all required, must only accommodate normal operation. An external
capacitor sets the on time. The off time is always 40 times tON.
The UCC284-x can be shutdown to 45 µA (maximum) by pulling the SD/CT pin more positive than –0.7 V. To
allow for simpler interfacing, the SD/CT pin may be pulled up to 6 V above the ground pin without turning on
clamping diodes.
Internal power dissipation is further controlled with thermal-overload protection circuitry. Thermal shutdown
occurs if the junction temperature exceeds 140°C. The chip remains off until the temperature has dropped 20°C
(TJ = 120°C).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
UCC284-EP
SLVS862A – NOVEMBER 2008 – REVISED NOVEMBER 2008 ....................................................................................................................................... www.ti.com
ORDERING INFORMATION (1)
OUTPUT VOLTAGE (V) PACKAGE DEVICES
TYP
(SOIC) D (2)
TA
–55°C to 100°C
–5
UCC284SDR-5EP
–55°C to 100°C
–12
UCC284SDR-12EP
–55°C to 100°C
–5 (Adj)
UCC284SDR-ADJEP
(1)
(3)
(3)
For the most current package and ordering information, see the
Package Option Addendum at the end of this document, or see the
TI website at www.ti.com.
Package drawings, standard packing quantities, symbolization, and
PCB design guidelines are available at www.ti.com/sc/package.
Thermal data can be found at
http://www-s.ti.com/cgi-bin/sc/thermal_derating_curve.cgi.
Product preview only.
(2)
(3)
functional block diagram
(+)
1− µ A
DISCHARGE
R1
R2
0
OPEN
UCC384−5
375K
125K
UCC384−12
375K 43.6K
UCC384−ADJ
+
SHUTDOWN
−0.7 V
−2.2 V
1.25 V
50 k
4
GND
1
VOUTS
5
VOUT
R2
+
−1.6 V
SD/CT
S
Q
R
Q
TON
8
−2.6 V
+
TOFF
VPUMP
+
GM
40 µA
CHARGE
R1
OVERCURRENT
700 mA
+
VIN
2
VIN
3
VIN
6
VIN
7
THERMAL
SHUTDOWN
UVLO
(−)
(−)
UDG−99030
2
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ABSOLUTE MAXIMUM RATINGS (1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Input voltage range (2)
MAX
UNIT
-16
SD/CT Shutdown voltage range
V
-5
6
V
TJ
Operating virtual junction temperature range
-55
150
V
Tstg
Storage temperature range
-65
150
°C
300
°C
Lead temperature (Soldering, 10 seconds)
(1)
(2)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground. Currents are positive into and negative out of the specified terminals.
ELECTRICAL CHARACTERISTICS
TA = –55°C to 100°C for the UCC284, VIN = VOUT – 1.5 V, IOUT = 0 mA, COUT = 4.7 µF, and CT = 0.015 µF. For
UCC284-ADJ, VOUT is set to –3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
TA = 25°C
–5.075
–5
–4.925
Over all temperature conditions
–5.150
UNIT
UCC284-5 Fixed –5-V 0.5-A Regulation Section
Output voltage
Line regulation
TA = 25°C, VIN = –5.2 V to –15 V
1.5
Over all temperature conditions
Load regulation
Output noise voltage
Dropout voltage, VOUT – VIN
V
–4.850
V
10
mV
12
TA = 25°C, IOUT = 0 mA to 0.5 A
0.1
0.25
Over all temperature conditions
0.1
0.30
TA = 25°C, BW = 10 Hz to 10 kHz
200
TA = 25°C, IOUT 0.5 A, VOUT = –4.8 V
0.2
0.5
Over all temperature conditions
0.2
0.55
TA = 25°C, IOUT 50 mA, VOUT = –4.8 V
20
50
Over all temperature conditions
20
55
%
µVRMS
V
mV
UCC284-5 Fixed –5-V 0.5-A Power Supply Section
Input voltage range
Quiescent current charge pump on
–15
TA = 25°C, VIN = –4.85 V
(1)
280
Over all temperature conditions
Quiescent current
Shutdown threshold
Shutdown input current
Output leakage in shutdown
V
350
µA
360
TA = 25°C, VIN = –15 V
200
Over all temperature conditions
Quiescent current in shutdown
–5.2
250
VIN = –13 V, SD/CT = 0 V, TA = 0°C to 100°C
(2)
VIN = –13 V, SD/CT = 0 V, TA = –55°C to 0°C
(2)
15
TA = 25°C, At shutdown pin (SD/CT)
–1.0
Over all temperature conditions
-1.2
–0.7
45
µA
100
µA
–0.4
V
-0.2
TA = 25°C, SD/CT = 0 V
5
10
25
Over all temperature conditions
3
10
30
1
50
VIN = –15 V, VOUT = 0 V
(3)
µA
260
µA
µA
Overtemperature shutdown
140
°C
Overtemperature hysteresis
20
°C
UCC284-5 Fixed –5-V 0.5-A Current Limit Section
(1)
(2)
(3)
The internal charge pump is enabled only for dropout condition with low VIN. Only in this condition is the charge pump required to
provide additional output FET fate drive to maintain dropout specifications. For conditions where the charge pump is not required, it is
disabled, which lowers overall device power consumption.
Ensured by design. Not production tested.
In the application during shutdown mode, output leakage current adds to quiescent current.
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ELECTRICAL CHARACTERISTICS (continued)
TA = –55°C to 100°C for the UCC284, VIN = VOUT – 1.5 V, IOUT = 0 mA, COUT = 4.7 µF, and CT = 0.015 µF. For
UCC284-ADJ, VOUT is set to –3.3 V (unless otherwise noted)
PARAMETER
Peak current limit
MIN
TYP
MAX
TA = 25°C, VOUT = 0 V
TEST CONDITIONS
0.7
1.1
1.5
Over all temperature conditions
0.5
Overcurrent threshold
UNIT
A
1.7
0.55
0.7
2.5
4
%
500
700
µs
Current limit duty cycle
VOUT = 0 V
Overcurrent time out, tON
TA = 25°C, VOUT = 0 V
300
Over all temperature conditions
300
0.9
A
720
UCC284-12 Fixed 12-V 0.5-A Regulation Section
Output voltage
TA = 25°C
–12.18
Over all conditions
–12.24
–12
–11.82
V
–11.64
V
Line regulation
VIN = –12.5 V to –15 V
5
15
Load regulation
IOUT = 0 mA to 0.5 A
0.1
0.3
Output noise voltage
TA = 25°C, BW = 10 Hz to 10 kHz
200
IOUT = 0.5 A, VOUT = –11.6 V
0.15
0.5
V
15
50
mV
Dropout voltage, VOUT - VIN
IOUT = 50 mA, VOUT = –11.6 V
mV
%
µVRMS
UCC284-12 Fixed –12-V 0.5-A Power Supply Section
Input voltage range
Quiescent current
–15
VIN = -15 V
VIN = –13 V, SD/CT = 0 V
Quiescent current in shutdown
TA = 0°C to 100°C
(4)
–12.5
V
220
350
µA
15
45
µA
100
µA
VIN = –13 V, SD/CT = 0 V
TA = –55°C to 0°C (4)
(4)
Ensured by design. Not production tested.
ELECTRICAL CHARACTERISTICS
TA = –55°C to 100°C for the UCC284, VIN = VOUT – 1.5 V, IOUT = 0 mA, COUT = 4.7 µF, and CT = 0.015 µF. For
UCC284-ADJ, VOUT is set to –3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
–1.0
–0.7
–0.4
V
5
10
25
µA
1
50
µA
UCC284-12 Fixed –12 V –0.5-A Power Supply Section (continued)
Shutdown threshold
At shutdown pin (SD/CT)
Shutdown input current
SD/CT = 0 V
Output leakage in shutdown
VIN = –15 V, VOUT = 0 V (1)
Overtemperature shutdown
140
°C
Overtemperature hysteresis
20
°C
UCC284-12 Fixed –12-V 0.5-A Current Limit Section
Peak current limit
VOUT = 0 V
Overcurrent threshold
Current limit duty cycle
VOUT = 0 V
Overcurrent time out, tON
VOUT = 0 V
0.7
1.1
1.5
A
0.55
0.7
0.9
A
2.5
4
%
300
500
700
µs
–1.27
–1.25
–1.23
V
UCC284-ADJ Adjustable 0.5-A Regulation Section
Reference voltage
TA = 25°C
Over temperature
Line regulation
VIN = –3.5 V to –15 V, VOUT = VOUTS
Load regulation
Output noise voltage
(1)
4
–1.275
–1.215
0.5
3
IOUT = 0 mA to 0.5 A
0.1
0.18
BW = 10 Hz to 10 kHz, TA = 25°C
200
V
mV
%
µVRMS
In the application during shutdown mode, output leakage current adds to quiescent current.
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ELECTRICAL CHARACTERISTICS (continued)
TA = –55°C to 100°C for the UCC284, VIN = VOUT – 1.5 V, IOUT = 0 mA, COUT = 4.7 µF, and CT = 0.015 µF. For
UCC284-ADJ, VOUT is set to –3.3 V (unless otherwise noted)
PARAMETER
Dropout voltage, VOUT - VIN
TEST CONDITIONS
MIN
IOUT 0.5 A, VOUT = –3.15 V
IOUT 50 mA, VOUT = –3.15 V
Sense pin input current
TYP
MAX
0.25
0.5
UNIT
V
25
50
mV
100
250
nA
UCC284-ADJ Adjustable 0.5-A Power Supply Section
Input voltage range
–15
Undervoltage lockout
–3.2
Quiescent current charge pump on
VIN = –3.15 V
Quiescent current
VIN = –15 V
(2)
VIN = –13 V, SD/CT = 0 V
Quiescent current in shutdown
TA = 0°C to 100°C (3)
–3.5
V
–2.95
–2.7
V
200
350
µA
200
250
µA
15
45
µA
100
µA
VIN = –13 V, SD/CT = 0 V
TA = –55°C to 0°C (3)
Shutdown threshold
At shutdown pin (SD/CT)
Shutdown input current
SD/CT = 0 V
Output leakage in shutdown
VIN = –15 V, VOUT = 0 V (4)
–1.0
–0.7
–0.4
V
5
10
25
µA
1
50
µA
Overtemperature shutdown
140
°C
Overtemperature hysteresis
20
°C
UCC284-ADJ Adjustable 0.5-A Current Limit Section
Peak current limit
VOUT = 0 V
Overcurrent threshold
Current limit duty cycle
VOUT = 0 V
Overcurrent time out, tON
VOUT = 0 V
(2)
(3)
(4)
0.7
1.1
1.5
0.55
0.7
0.9
A
2.5
4
%
500
700
µs
300
A
The internal charge pump is enabled only for dropout condition with low VIN. Only in this condition is the charge pump required to
provide additional output FET fate drive to maintain dropout specifications. For conditions where the charge pump is not required, it is
disabled, which lowers overall device power consumption.
Ensured by design. Not production tested.
In the application during shutdown mode, output leakage current adds to quiescent current.
PIN DESCRIPTION
GND: This is the low noise ground reference input. All voltages are measured with respect to the GND pin.
SD/CT: This is the shutdown pin and also the short-circuit timing pin. Pulling this pin more positive than –0.7 V
puts the circuit in a low-current shutdown mode. Placing a timing capacitor between this pin and GND sets the
short-circuit charging time, tON during an overcurrent condition. During an overcurrent condition, the output pulses
at approximately a 2.5% duty cycle.
NOTE:
The CT capacitor must be connected between this pin and GND, not VIN, to assure
that the SD/CT pin is not pulled significantly negative during power-up. This pin
should not be externally driven more negative than –5 V or the device will be
damaged.
VIN: This is the negative input supply. Bypass this pin to GND with at least 1 µF of low ESR or ESL capacitance.
VOUT: Regulated negative-output voltage. A single 4.7–µF capacitor should be connected between this pin and
GND. Smaller value capacitors can be used for light loads, but this degrades the load-step performance of the
regulator.
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VOUTS: This is the feedback pin for sensing the output of the regulator. For the UCC284-5 and UCC284-12
versions, VOUTS can be connected directly to VOUT. If the load is placed at a considerable distance from the
regulator, the VOUTS lead can be used as a Kelvin connection to minimize errors due to lead resistance.
Connecting VOUTS at the load moves the resistance of the VOUT wire into the control loop of the regulator,
thereby effectively canceling the IR drop associated with the load path.
6
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APPLICATION INFORMATION
overview
The UCC284–x family of negative low-dropout linear (LDO) regulators provides a regulated-output voltage for
applications with up to 0.5 A of load current. The regulators feature a low-dropout voltage and short-circuit
protection, making their use ideal for demanding applications requiring fault protection.
programming the output voltage on the UCC284
The UCC284–5 and UCC284–12 have output voltages that are fixed at –5 V and –12 V respectively. Connecting
VOUTS to VOUT gives the proper output voltage with respect to ground.
The UCC284–ADJ can be programmed for any output voltage between –1.25 V and –15 V. This is easily
accomplished with the addition of an external resistor divider connected between GND and VOUT with VOUTS
connected to the center tap of the divider. For an output of –1.25 V, no resistors are needed and VOUTS is
connected directly to VOUT. The regulator-input voltage cannot be more positive than the UVLO threshold, or
approximately –3 V. Thus, low dropout cannot be achieved when programming the output voltage more positive
than approximately –3.3 V. A typical application circuit is shown in Figure 1.
(+)
(+)
CT
0.015µF
4
R2
GND
8
SD/CT
VOUTS 1
CIN
+ 1 µF
VIN
COUT
4.7µF
C1
UCC384−ADJ
VOUT
VIN
VIN
VIN
VIN
2
3
6
7
VOUT
+
R1
5
(−)
(−)
Figure 1. Typical Application Circuit
For the UCC284-ADJ, the output voltage is programmed by the following equation:
VOUT + * 1.25
ǒ1 ) R1
Ǔ
R2
(1)
When R1 or R2 are selected to be greater than about 100 kΩ, a small ceramic capacitor should be placed across
R1 to cancel the input pole created by R1 and the parasitic capacitance appearing on VOUTS. Values of
approximately 20 pF should be adequate.
dropout performance
The UCC284 is tailored for low-dropout applications where low-quiescent power is important. Fabricated with a
BCDMOS technology ideally suited for low input-to-output differential applications, the UCC284 passes 0.5 A
while requiring only 0.2 V of headroom. The dropout voltage is dependent on operating conditions such as load
current, input and load voltages, and temperature. The UCC284 achieves a low RDS(on) through the use of an
internal charge-pump that drives the MOSFET gate.
Figure 2 shows typical dropout voltages versus output voltage for the UCC284–5 V and –12 V versions as well
as the UCC284-ADJ version programmed between –3.3 V and –15 V. Since the dropout voltage is also affected
by output current, Figure 3 shows typical dropout voltages versus load current for different values of VOUT.
Operating temperatures also affect the RDS(on) and the dropout voltage of the UCC284. Figure 4 shows typical
dropout voltages for the UCC284 over temperature under a full load of 0.5 A.
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short-circuit protection
The UCC284 provides unique short-circuit protection circuitry that reduces power dissipation during a fault. When
an overcurrent condition is detected, the device enters a pulsed mode of operation, limiting the output to a 2.5%
duty cycle. This reduces the heat sink requirements during a fault. The operation of the UCC284 during an
overcurrent condition is shown in Figure 5.
DROPOUT VOLTAGE
vs
OUTPUT VOLTAGE
0.30
DROPOUT VOLTAGE
vs
LOAD CURRENT
0.25
IOUT = 0.3 A
(VIN−VOUT) − Dropout Voltage − V
0.25
IOUT = 0.4 A
0.20
IOUT = 0.5 A
0.15
0.10
0.05
IOUT = 0.2 A
(VIN−VOUT) − Dropout Voltage − V
VOUT = −5 V
0.20
VOUT = −3.3 V
0.15
0.10
VOUT = −12 V
0.05
VOUT = −15 V
IOUT = 0.1 A
0.00
3
6
9
12
VOUT − Output Voltage − V
15
0.05
0.15
0.25
0.35
IOUT − Load Current − A
Figure 2.
Figure 3.
DROPOUT VOLTAGE
vs
TEMPERATURE
0.40
0.35
(VIN−VOUT) − Dropout Voltage − V
0.45
0.30
VOUT = −3.3 V
VOUT = −5 V
0.25
0.20
VOUT = −12 V
0.15
0.10
VOUT = −15 V
0.05
0
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − _C
Figure 4.
8
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t OFF
t ON
t OFF
t ON
t ON
IOUT=0A
~40 x tON
~40 x tON
IOUT (NOM)
IOVER
IPEAK
NOTE: CURRENT FLOW IS INTO THE DEVICE
VOUT = 0V
VOUT
=(IPEAK)(RL)
VOUT NOM. (−V)
CT = 0V
CT (NOM) = − 1.6V
CT = − 2.6V
UDG−99031
Figure 5. Short Circuit Timing
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short-circuit timing
During normal operation the output voltage is in regulation and the SD/CT pin is held to -1.5 V via a 50-kΩ
internal-source impedance. If the output-current rises above the overcurrent threshold, the CT capacitor is
charged by a 40-µA current sink. The voltage on the SD/CT pin moves in a negative direction with respect to
GND.
During an overcurrent condition, the regulator actively limits the maximum output current to the peak-current limit.
This limits the output voltage of the regulator to:
(2)
V
+I
R
OUT
PEAK
L
If the output current stays above the overcurrent threshold, the voltage on the SD/CT pin reaches –2.6 V with
respect to GND and the output turns off. The CT capacitor is then discharged by a 1-µA current source. When
the voltage on the SD/CT pin reaches –1.6 V with respect to GND, the output turns back on. This process
repeats until the output current falls below the overcurrent threshold.
tON, the time the output is on during an overcurrent condition is determined by the following equation:
1 V seconds
(3)
t
+ CT (mF)
ON
40 mA
tOFF, the time the output is off during an overcurrent condition is determined by the following equation:
1 V seconds
(4)
t
+ CT (mF)
OFF
1 mA
capacitive loads
A capacitive load on the regulator's output appears as a short-circuit during start-up. If the capacitance is too
large, the output voltage does not begin to regulate during the initial tON period and the UCC284 enters a pulsed
mode operation. For a constant current load the maximum allowed output capacitance is calculated as follows:
t
(sec)
ON
(5)
C
+ I
(A) * I
(A)
Farads
OUT(max)
PEAK
LOAD
V
(V)
OUT
ƪ
ƫ
For worst case calculations, the minimum value for tON should be used, which is based on the value of CT
capacitor selected. For a resistive load the maximum output capacitor can be estimated as follows:
t
(sec)
ON
(6)
C
+
Farads
OUT(max)
R
LOAD
(W)
ȡ
ȧ
ȏnȧ
ȧ1
Ȣ
ǒ
*
I
1
V
MAX
OUT
(A) R
(V)
(W)
LOAD
ȣ
ȧ
ȧ
ȧ
Ȥ
Ǔ
Figure 6 and Figure 7 are oscilloscope photos of the UCC284-ADJ operating during an overcurrent condition.
Figure 6 shows operation of the circuit as the output current initially rises above the overcurrent threshold. This is
shown on a 1 ms/div. scale. Figure 7 shows operation of the same circuit on a 25 ms/div. scale showing one
complete cycle of operation during an overcurrent condition.
10
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UCC284−ADJ
OVERCURRENT CONDITION OPERATION
1 ms/div
Figure 6.
UCC284−ADJ
OVERCURRENT CONDITION OPERATION
25 ms/div
Figure 7.
shutdown feature of the UCC284
The shutdown feature of the UCC284 allows the device to be placed in a low quiescent current mode. The
UCC284 is shut down by pulling the SD/CT pin more positive than -0.7 V with respect to GND. Figure 8 shows
how a shutdown circuit can be configured for the UCC284 using a standard transistor-transistor logic signal to
control it.
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11
UCC284-EP
SLVS862A – NOVEMBER 2008 – REVISED NOVEMBER 2008 ....................................................................................................................................... www.ti.com
TTL SHUTDOWN CIRCUIT
+5 V
+5 V
LOGIC
INPUT
470 k
GND
(+)
(+)
0.015µF
CT
4
R2
GND
8 SD/CT
+
VIN
CIN
VOUTS
COUT
4.7µF
C1
UCC384−ADJ
1 µF
VOUT
VIN
VIN
VIN
VIN
2
3
6
7
VOUT
+
1
R1
(−)
5
(−)
Figure 8. TTL Controlled Shutdown Circuit
controlling the SD/CT pin
Forcing the SD/CT pin to any fixed voltage affects the operation of the circuit. As mentioned before, pulling the
SD/CT pin more positive than –0.7 V puts the circuit in a shutdown mode, limiting the quiescent current to less
than 45 µA. Pulling this pin more positive than 6 V with respect to GND damages the device.
Forcing the SD/CT pin to any fixed voltage between –0.7 V and –1.6 V with respect to GND enables the output.
However, in an overcurrent condition, the output does not pulse at a 2.5% duty cycle, but the output current is
still limited to the peak current limit. This circuit may be used where a fixed current limit is needed, where a 2.5%
duty cycle is undesirable. The UCC284 supplies a maximum current in this configuration as long as the
temperature of the device does not exceed the overtemperature shutdown. This is determined by the peak
current being supplied, the input and output voltages, and the type of heat sink being used. Thermal design is
discussed later on in this data sheet.
Forcing the SD/CT pin to a voltage level between approximately –1.6 V and –2.6 V with respect to GND is not
recommended as the output may or may not be enabled.
Forcing the SD/CT pin to a voltage level between approximately –2.6 V and –5 V with respect to GND turns the
output off completely. The output remains off as long as the voltage is applied. Pulling this pin more negative
than –5 V with respect to GND damages the device (see Table 1).
Table 1. SD/CT Voltage Levels
SD/CT
6 V to –0.7 V
Output disabled and device in low quiescent shutdown mode.
–0.7 V to –1.6 V
Output enabled
–1.6 V to –2.6 V
Output enabled or disabled depending on the previous state.
–2.6 V to –5 V
12
STATE
Output disabled
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UCC284-EP
www.ti.com ....................................................................................................................................... SLVS862A – NOVEMBER 2008 – REVISED NOVEMBER 2008
VIN TO VOUT DELAY TIME
DURING POWER-UP WITH CT = 0.22 µF
Figure 9.
VIN to VOUT Delay
During power-up there is a delay between VIN and VOUT. The majority of this delay time is due to the charging
time of the CT capacitor. When VIN moves more negative than the UVLO of the device with respect to GND, the
CT capacitor begins to charge. A 17-µA current sink is used only during power up to charge the CT capacitor.
When the voltage on the SD/CT pin reaches approximately –1.6 V with respect to GND, the output turns on and
regulates. The larger the value of the CT capacitor, the greater the delay time between VIN and VOUT. Figure 9
shows the VIN to VOUT start-up delay, approximately 16 ms for a circuit with CT = 0.22 µF.
Shorter delay times can be achieved with a smaller CT capacitor. The problem with a smaller CT capacitor is that
with a very large load, the circuit may stay in overcurrent mode and never turn on. A circuit with a large
capacitive load needs a large CT capacitor to operate properly.
One way to shorten the delay from VIN to VOUT during powerup is with the use of the quick start-up circuit
shown in Figure 10.
(+)
(+)
R2
4
CT
0.22µF
GND
8 SD/CT
VIN
+ CIN
C2
0.1µF
1 µF
+
COUT
4.7µF
VOUTS 1
C1
R4
18 k
UCC384−ADJ
VOUT 5
VOUT
R1
(−)
Q1
2N7000
R3
12 k
VIN
VIN
VIN
VIN
2
3
6
7
(−)
QUICK START CURRENT
Figure 10. Quick Start-Up Circuit
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UCC284-EP
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With the quick start-up circuit, the delay time between VIN and VOUT during start-up can be reduced
dramatically. Figure 11 shows that with the quick start-up circuit, the VIN to VOUT delay time has been reduced
to approximately 1 ms.
VIN TO VOUT DELAY TIME
WITH QUICK START-UP CIRCUIT
Figure 11.
VIN TO VOUT DELAY TIME
WITH CT CAPACITOR REMOVED
Figure 12.
operation of the quick start-up circuit
During normal start-up, the UCC284 does not turn on until the voltage on the SD/CT pin reaches approximately
–1.6 V with respect to ground. It takes a certain amount of time for the CT capacitor to charge to this point. For a
circuit that has a very large load, the CT capacitor needs to be large in order for the overcurrent timing to work
properly. A large value of capacitance on the SD/CT pin increases the VIN to VOUT delay time.
The quick start-up circuit uses Q1 to quickly pull the SD/CT pin in a negative direction during start-up, thus
decreasing the VIN-to-VOUT delay time. When VIN is applied to the circuit, Q1 turns on and starts to charge the
CT capacitor. The current pulled through R4 determines the rate at which CT is charged. R4 can be calculated
as follows:
V (V) T seconds
D
(7)
R4 + IN
ohms
1.6 CT (F)
tD is the approximate VIN-to-VOUT delay time desired.
Q1 needs to be turned off after a fixed time to prevent the SD/CT pin from going too far negative with respect to
GND. If the SD/CT pin is allowed to go too far negative with respect to GND, the output turns off again or
possibly even damages the SD/CT pin. The maximum amount of time that Q1 should be allowed to be on is
referred to as tM and can be calculated as follows:
(8)
t + 2.6 t seconds
M
D
1.6
14
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R3 along with C2 set the time that Q1 is allowed to be on. Since tM is the maximum amount of time that Q1
should be allowed to stay on, an added safety margin may be to use 0.9 × tM instead. This ensures that Q1 is
turned off in the proper amount of time. With a chosen value for C2, R3 can be calculated as follows:
0.9 t seconds
M
(9)
R3 +
Ohms
V (V)*1.6
C2(F) ȏn 1 * IN
V (V)
IN
ǒ
Ǔ
After the CT capacitor has charged up for a time equal to 0.9 × tM, Q1 turns off and allows the SD/CT pin to be
pulled back to –1.5 V with respect to GND through a 50-kΩ resistor. At this point, the SD/CT pin can be used by
the UCC284 overcurrent timing control.
minimum VIN to VOUT delay time
Although it may desirable to have as short a delay time as possible, a small portion of this delay time is fixed by
the UCC284 and cannot be shortened. This is shown in Figure 12, where the CT capacitor has been removed
from the circuit completely, giving a fixed VIN to VOUT delay of approximately 150 µs for a circuit with
VIN = –6 V and VOUT = –5 V.
thermal design
The Packaging Information section of the Power Supply Control Products Data Book (literature number
SLUD003) contains reference material for the thermal ratings of various packages. The section also includes an
excellent article entitled Thermal Characteristics of Surface Mount Packages, which is the basis for the following
discussion.
Thermal design for the UCC284 includes two modes of operation, normal and pulsed. In normal mode, the linear
regulator and heat sink must dissipate power equal to the maximum forward voltage drop multiplied by the
maximum load current. Assuming a constant current load, the expected heat rise at the regulator’s junction can
be calculated as follows:
(10)
(qjc ) qca)
t
+P
RISE
DISS
Theta (θ) is the thermal resistance and PDISS is the power dissipated. The junction-to-case thermal resistance
(θjc) of the SOIC-8 D package is 22°C/W. In order to prevent the regulator from going into thermal shutdown, the
case-to-ambient thermal resistance (θca) must keep the junction temperature below 150°C. If the UCC284 is
mounted on a 5 square inch pad of 1-ounce copper, for example, the thermal resistance (θja) becomes
40-70°C/W. If a lower thermal resistance is required for the application, the device heat sinking needs to be
improved.
When the UCC284 is in a pulsed mode, due to an overcurrent condition, the maximum average power
dissipation is calculated as follows:
ƪ
P avg + V
(V) * V
(V)
IN
OUT
ƫ
I
PEAK
(A)
ǒ
t
(seconds)
ON
40 t
(seconds)
ON
Ǔ
Watts
(11)
As seen in equation (10), the average power during a fault is reduced dramatically by the duty cycle, allowing the
heat sink to be sized for normal operation. Although the peak power in the regulator during the tON period can be
significant, the thermal mass of the package normally keeps the junction temperature from rising unless the tON
period is increased to several milliseconds.
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15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
UCC284SDR-5EP
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
V62/09609-01XE
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Dec-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
UCC284SDR-5EP
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
6.4
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Dec-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UCC284SDR-5EP
SOIC
D
8
2500
346.0
346.0
29.0
Pack Materials-Page 2
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