MINGSTAR ELECTRONIC CORPORATION S p e c . N o . 4 1 3 -2 1 2 -0 7 4 Ve rs io n : 1 To ta l p a g e s : 1 9 1 D a te : 2 0 0 0 /0 3 /2 2 1 9 9 9 /1 2 /0 1 TFT-LCD CONTROLLER LSI (UPS017) PRELIMINARY SPECIFICATION MODEL NAME: UPS017 The content of this technical information is subject to change without notice. Please contact Mingstar or its agent for further information. Mingstar copyright 2000 All rights reserved, copying forbidden. SPEC NO.:413-212-074 PAGE : 1/19 Contents : A. General description ....................................................................... P3 B. Feature ............................................................................................ P3 C. Pin description ............................................................................... P4 D. DC characteristics ......................................................................... P8 1. Absolute maximum ratings .......................................................... P8 2. Recommended operating conditions ........................................... P8 3. General DC characteristics.......................................................... P8 4. Current consumption for 5 volts operation................................... P8 E. AC characteristics.......................................................................... P9 1. Timing condition........................................................................... P9 (I) 1440 resolution mode............................................................... P9 a. Input signal characteristics ................................................ P9 b. Output signal characteristics ............................................. P9 (II) 1200 resolution mode.............................................................. P9 a. Input signal characteristics ................................................ P10 b. Output signal characteristics ............................................. P10 (III) Zoom in/out display mode ...................................................... P11 a. 1440 mode........................................................................ P11 b. 1200 mode........................................................................ P11 2. Timing diagram ............................................................................ P11 F. Test circuit ...................................................................................... P12 ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM MINGSTAR ELECTRONIC CORP. SPEC NO.:413-212-074 PAGE : 2/19 G. Package information ..................................................................... P13 Appendix Fig.1 Fig.2 (a) Fig.2 (b) Fig.3 Fig.4 Sampling clock timing ....................................................... P15 Horizontal timing............................................................... P16 Horizontal timing(detail).................................................... P17 Vertical shift clock timing .................................................. P18 Vertical timing .................................................................. P19 ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM MINGSTAR ELECTRONIC CORP. SPEC NO.:413-212-074 PAGE : 3/19 A.General description: This timing controller is a synchronizing signal controlling CMOS gate-array LSI for Mingstar LCD module. It provides all the necessary control timing signals to the LCD source and gate drivers. With external VCO as the master clock, the controller has built-in phase locked loop system which can synchronize the master clock with the horizontal and vertical Sync. signals from a classical TV system. This IC support Mingstar's 16:9 aspect ratio series TFT-LCD modules and it also provides different zoom in/out display mode. B. Feature: * Programmable resolution mode. * Low Power Consumption. * Single Supply : +5.0 Volts. * 48 pins LQFP. * Shift Clocks Signal for the Source Driver. (3 - Clock) * Line Inversion Driving Scheme. * NTSC TV Standard System . * Master Clock Frequency : 30 MHz max. * Provides Timing Scan Signals for Left / Right and Up / Down Shift Control. * Built-in zoom in/zoom out display mode selection. * Display Timing Range = 49.4 s ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM MINGSTAR ELECTRONIC CORP. SPEC NO.:413-212-074 PAGE : 4/19 C.Pin description: Pin no 1 2 3 4 5 6 7 8 9 10 11 Symbol I/O NPFRP O HZ_OUT O HOE_OUT O VOE_OUT O D_MOD I FDV_OUT O Description Inverted output of PFRP_OUT Zoom in control signal Output enable control signal for source driver Output enable control signal for gate driver Digital mode setting pin. Test pin. GND Ground MOD_OUT O Simultaneous/sequential sampling control setting of LCD. RES_C I Horizontal resolution mode setting pin . H: 1440, L:1200 VO2 O Gate driver start pulse. When (1).UDC=H, VO2 is output pin of start pulse. (2).UDC=L, VO2 is in high impedance state. VO1 O Gate driver start pulse. when (1).UDC=H, VO1 is in high impedance state. (2).UDC=L, VO1 is output pin of start pulse. 12 13 VCC STHL 14 STHR 15 16 17 18 19 20 21 22 23 24 25 26 PD_OUT V_CK CK1A CK2A CK3A ZX1 ZX2 ZX3 GND VCC F_OUT F_IN O Source driver start pulse. when (1).L_R=H, STHL is in high impedance state. (2).L_R=L, STHL is output pin of start pulse. O Source driver start pulse. when (1).L_R=H, STHR is output pin of start pulse. (2).L_R=L, STHR is in high impedance state. O Negative polarity phase detector output. O Gate driver shift clock. O Source driver shift clock 1 . O Source driver shift clock 2 . O Source driver shift clock 3 . I Zoom in/out modes setting I Zoom in/out modes setting I Zoom in/out modes setting Ground Remark Note 2 Note 2 Note 2 O Inverted F_IN signal output I Master system clock input. This input pin is connected to the external VCO output for system clock timing & synchronization to the TV sync. Signals through the phase locked loop block. ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM MINGSTAR ELECTRONIC CORP. SPEC NO.:413-212-074 PAGE : 5/19 Pin no Symbol I/O 27 28 29 VSY_OUT HSYW GR_IN O O I 30 V_IN I 31 32 33 UD_OUT ZTC AUXS O I I 34 35 36 HSY_OUT Csync GND O I 37 UDC I 38 39 PD_SW L_R I I 40 41 LR_A CSYN_OUT O 42 43 44 45 46 47 48 TC NPC PFRP_OUT NP_SW CP_OUT CP_IN VCC I I O I O I o Description Negative polarity vertical sync. output Test pin Global reset. It should be connected to VCC in normal operation. If connected to GND, the controller is in reset state. Vertical synchronization signal input from the sync. Separator of a TV system. It should be a negative polarity. Inverted UDC signal output. Test pin Setting pin of zoom in/out control. Please set to “L”. Negative polarity horizontal sync. output. Positive polarity composite sync. input. Ground Up / Down scan control pin. (1) Normal Scan : set to Low (2) Reverse Scan : set to High Horizontal noise counter setting pin. Left / Right scan control pin. (1) Normal Scan : set to Low (2) Reverse scan : set to High Inverted L_R signal output. Test pin. Test pin It should be pulled to Vcc in normal operation. Polarity alternating signal for Vcom Test pin Compare pulse output. Compare pulse input. Remark Note 1 Note 1 Note 1 Note 1 Note 1 : All these pins should be electrically opened. ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM MINGSTAR ELECTRONIC C O P RP . SPEC NO.:413-212-074 PAGE : 6/19 Note 2 : Zoom in/out display mode setting : Display mode ZX1 ZX2 ZX3 Display Characteristics (4:3 aspect-ratio input signal) Note Full H H H Input signals are displayed on full screen. ( To display 4 : 3 signal on 16 : 9 screen) Zoom1 L H H Central 176 lines of input signals are displayed on full screen. (Vertically extension, zoom factor = 4/3) Zoom-Wide1 H L H Central 176 lines of input signals are displayed on full screen. (Vertically extension and different horizontal timing scaling.) Normal L L H Input signal (4:3) are displayed on center 75% screen. (4 :3 aspect-ratio) ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM MINGSTAR ELECTRONIC CORP. SPEC NO.:413-212-074 PAGE : 7/19 Display Mode ZX1 ZX2 Zx3 Display Characteristics (4:3 aspect-ratio input signal) Note Zoom2 H H L Lower 205 lines of input signals are displayed on full screen. (Zoom factor = 8/7, vertically offset extension ) Wide L H L Input signals are displayed on full screen. ( Different horizontal timing scaling.) Zoom-Wide2 H L L Lower 205 lines of input signal are displayed on full screen. ( Vertically extension and different horizontal timing scaling.) Zoom3 L L L Center 205 lines of input signal are displayed on full screen. (Vertically extension, Zoom factor = 8/7) ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM MINGSTAR ELECTRONIC CORP. SPEC NO.:413-212-074 PAGE : 8/19 D.DC characteristics 1. Absolute maximum ratings: SYMBOL VCC VIN VOUT TSTG PARAMETER Power supply Input voltage Output voltage Storage temperature RATING -0.3 to 6.0 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -40 to 125 UNITS V V V 2.Recommended operating conditions: SYMBOL VCC VIN TOPR PARAMETER Power supply Input voltage Operating temperature MIN 4.5 0 -20 TYP 5.0 - MAX 5.5 VCC 85 UNITS V V 3.General DC characteristics: SYMBOL PARAMETER IIL Input low current CONDITIONS no pull-up or pull-down no pull-up or pull-down MIN -1 TYP - MAX 1 -1 - 1 -10 - 10 UNITS Remark A IIH Input high current IOZ Tri-state leakage current CIN Input capacitance - 3 - PF COUT Output capacitance 3 - 6 PF VIL VSIL VIH VSIH VOL VOH RI Logic input low voltage Schmitt input low voltage Logic input high voltage Schmitt input high voltage Output low voltage Output high voltage Input pull up/down resistance CMOS CMOS CMOS CMOS IOL=4mA IOH=4mA VIL=0V or VIH=VCC 0.7Vcc 3.5 - 0.3Vcc 1.76 3.2 0.4 50 - A A V V V V V V K Note 1 Note 1 Note 2 Note 1: The applicable pins are F_IN, V_IN, Csync, CP_IN. Note 2: When IOH = 3mA , VOH Min.= 4V. 4.Current consumption for 5 volts operating: Symbol Parameter Condition Min Typ Current Vcc=5V (12) (18) IIN consumption (10) (15) Max (25) Unit mA (21) mA Loading MTL070D01W-XX Series MTL056D01W-XX Series ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM MINGSTAR ELECTRONIC CORP. SPEC NO.:413-212-074 PAGE : 9/19 E. AC characteristics 1.Timing condition ( ) 1440 resolution mode. a.Input signal characteristics(In non-zoom display mode) Parameter F_IN period Symbol tOSC Min. 33 Typ. 34 Max. 35 TH 61.5 63.5 65.5 Csync pulse width tCSYN 4 4.7 5.4 Csync rising time TCr - - 700 ns Csync falling time TCf - - 300 ns V_IN pulse width tVSY 1 3 5 tH V_IN rising time TVr - - 700 ns V_IN falling TVf - - 1.5 256 262.5 268 Csync period Horizontal lines per field Unit. ns Remark s s s line Note 1 Note 1: Please don't use odd horizontal lines to drive LCD panel for both odd and even field simultaneously. b.Output signal characteristics Parameter Rising time Falling time Clock high and low level Pulse width Clock pulse duty 3 clock phase difference Symbol tr tf tCPH Min. - Typ. 3 Max. 10 10 - Unit. ns ns tOSC Remark Note 1 Note 1 CK1A~CK3A 40 - 50 tCPH /3 60 - % ns CK1A~CK3A STH setup time tCWH tC12 tC23 tC31 tSUH - tCPH /2 - ns STH pulse width tSTH - 1 - tCPH HSY_OUT pulse width tHSY - 4.62 - HOE_OUT pulse width tOEH - 1.22 - Sample & hold disable time tDIS1 - 8.17 - VOE_OUT pulse width s s s tOEV - 4.62 - V_CK pulse width tCKV - 3.81 - CP_OUT period tCP - 1 - tH tWCP - 1/2 - tH t1 - 3.38 - t2 - 2.86 - t3 - 0.816 - t4 - 3.26 - VO1/2 setup time tSUV - 2 - VO1/2 pulse width tSTV - 1 - CP_OUT pulse duty HSY_OUT-HOE_OUT timing difference HSY_OUT-V_CK timing difference HSY_OUT-VOE_OUT timing difference HSY_OUT-CP_OUT timing difference s s s s s s s tH ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM MINGSTAR ELECTRONIC CORP. SPEC NO.:413-212-074 PAGE : 10/19 VSY_OUT-VO1/2 timing difference(UDC="H") VSY_OUT-VO1/2 timing difference(UDC="L") HOE_OUT-VO1/2 timing difference tVS1 - 19 - tH tVS2 - 19 - tH tOES - 2 - tH Note 1: For all of the logic signals. ( ) 1200 resolution mode. a.Input signal characteristics (In non-zoom display mode) Parameter F_IN period Symbol tOSC Min. 40.3 Typ. 41.6 Max. 43 TH 61.5 63.5 65.5 Csync pulse width tCSYN 4 4.7 5.4 Csync rising time TCr - - 700 ns Csync falling time TCf - - 300 ns V_IN pulse width tVSY 1 3 5 tH V_IN rising time TVr - - 700 ns V_IN falling TVf - - 1.5 256 262.5 268 Csync period Horizontal lines per field Unit. ns Remark s s s line Note 1 Note 1: Please don't use odd horizontal lines to drive LCD panel for both odd and even field simultaneously. b.Output signal characteristics Parameter Rising time Falling time Clock high and low level Pulse width Clock pulse duty 3 clock phase difference Symbol tr tf tCPH Min. - Typ. 3 Max. 10 10 - Unit. ns ns tOSC Remark Note 1 Note 1 CK1A~CK3A 40 - 50 tCPH /3 60 - % ns CK1A~CK3A STH setup time tCWH tC12 tC23 tC31 tSUH - tCPH /2 - ns STH pulse width tSTH - 1 - tCPH HSY_OUT pulse width tHSY - 4.64 - HOE_OUT pulse width tOEH - 1.49 - Sample & hold disable time tDIS1 - 7.97 - VOE_OUT pulse width tOEV - 5.13 - V_CK pulse width tCKV - 4.14 - CP_OUT period tCP - 1 - tWCP - 1/2 - t1 - 3.13 - t2 - 2.49 - t3 - 1.49 - CP_OUT pulse duty HSY_OUT-HOE_OUT timing difference HSY_OUT-V_CK timing difference HSY_OUT-VOE_OUT timing difference s s s s s tH tH s s s ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM MINGSTAR ELECTRONIC CORP. SPEC NO.:413-212-074 PAGE : 11/19 HSY_OUT-CP_OUT timing difference t4 - 2.98 - VO1/2 setup time tSUV - 2.00 - VO1/2 pulse width tSTV - 1 - tH VSY_OUT-VO2 timing difference(UDC="H") VSY_OUT-VO1 timing difference(UDC="L") HOE_OUT-VO1/2 timing difference tVS1 - 19 - tH tVS2 - 19 - tH tOES - 2 - tH s s Note 1: For all of the logic signals. Zoom in/out display mode a. 1440 mode Zoom mode ZX1 ZX2 ZX3 L L L H L L L H L H H L L L H H L H L H H H H H REMARK Horizontal display Start 12.94us 12.98us 12.98us 12.94us 8.83us 12.98us 12.94us 12.94us Vertical display Start 33H 45H 19H 45H 19H 48H 48H 19H From falling edge of HSY_OUT to rising edge of STHR(L) From falling edge of VSY_OUT to rising edge of VO1(2) Horizontal display Start 12.59us 12.65us 12.65us 12.59us 8.65us 12.65us 12.59us 12.59us Vertical display Start 33H 45H 19H 45H 19H 48H 48H 19H From falling edge of HSY_OUT to rising edge of STHR(L) From falling edge of VSY_OUT to rising edge of VO1(2) b. 1200 mode Zoom mode ZX1 ZX2 ZX3 L L L H L L L H L H H L L L H H L H L H H H H H REMARK 2.Timing diagram Please refer to the attached drawing. from Fig.1 to Fig.4. ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM MINGSTAR ELECTRONIC CORP. SPEC NO.:413-212-074 PAGE : 12/19 F. Test circuit ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM MINGSTAR ELECTRONIC CORP. SPEC NO.:413-212-074 PAGE : 13/19 G. Package information ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM MINGSTAR ELECTRONIC CORP. SPEC NO.:413-212-074 PAGE : 14/19 ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM MINGSTAR ELECTRONIC CORP. SPEC NO.:413-212-074 PAGE : 15/19 ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM MINGSTAR ELECTRONIC CORP. SPEC NO.:413-212-074 PAGE : 16/19 ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM MINGSTAR ELECTRONIC CORP. SPEC NO.:413-212-074 PAGE : 17/19 ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM MINGSTAR ELECTRONIC CORP. SPEC NO.:413-212-074 PAGE : 18/19 ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM MINGSTAR ELECTRONIC CORP. SPEC NO.:413-212-074 PAGE : 19/19 ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM MINGSTAR ELECTRONIC CORP. Mingstar Electronic Corp. 365-A Cloverleaf Drive Baldwin Park, CA 91706 Fax:626-369-1655 Tel :888-314-1126 Mingstar copyright 2000 All rights reserved , copying forbidden.