PIXART PAS5101PE

PAS5101PE Specification
PAS5101PE CMOS 1.3MEGA DIGITAL IMAGE SESNSOR
General Description
The PAS5101PE is a highly integrated CMOS active-pixel image sensor that has resolution of 1280( H ) x
1024 ( V ). To have an excellent image quality, the PAS5101PE output 10-bits RGB raw data though a parallel
data bus. It is available in 48-pin LCC.
The PAS5101PE can be programmed to set the exposure time for different luminance condition via I2CTM
serial control bus. By programming the internal register sets, it performs on-chip frame rate adjustment, offset
correction DAC, programmable gain control, 10-bits ADC, 10-bits output companding, interpolated subsampling and defect compensation.
Features
Key Specification
z
1.3Mega resolution, ~1/3” Lens.
Supply Voltage
z
Bayer RGB color filter array.
z
10-bits parallel RGB raw data output.
z
On-Chip 10-bits pipeline A/D converter.
z
On-Chip programmable gain amplifier
Pixel Size
„
4-bits color gain amplifier.
Max. Frame Rate
„
4-bits global gain amplifier.
2.5v ~ 3.3v
Resolution
1280 ( H ) x 1024 ( V )
Array Diagonal
5.9mm ( ~1/3” Optic )
3.6μm x 3.6μm
~15 fps @ 1.3Mega
Max. System Clock
Up to 48MHz
Max. Pixel Clock
Up to 24MHz
z
Digital gain stage.
z
Continuous variable frame time.
z
Continuous variable exposure time.
Color Filter
z
I2CTM interface.
Exposure Time
z
20mA power dissipation ( 15fps / 2.5v ).
z
< 10uA low power-down dissipation.
z
Window-of-Interest (WOI).
z
RGB Bayer Pattern
~ Frame time to Line time
Scan Mode
Progressive
Sensitivity
TBD
Sub-sampling.
S/N Ratio
TBD
z
Defect compensation.
Chief Ray Angle
z
Lens shading compensation.
Package Type
20° ~ 24°
48-pin LCC
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PAS5101PE Specification
NC
PX7
VSSD
PX9
SYSCLK
RESET
PXCLK
VDDMD
VSYNC
NC
NC
Pin Assignment
NC
1.
18
17
16
15
14
13
12
11
10
9
8
7
NC
19
6
NC
NC
20
5
NC
NC
21
4
HSYNC
PX8
22
3
NC
VDDD
23
2
NC
PX6
24
PAS5101PE
1
VDDMA
-- Top View -PX0
NC
28
45
PWDN
NC
29
44
NC
NC
30
43
NC
33
34
35
36
37
38
39
VSSA
32
PX3
31
40
41
42
NC
VDDA
NC
46
NC
27
NC
PX1
SDA
VREF
SCL
26
PX2
PX5
PX4
NC
NC
48
47
NC
25
Figure 1.1 Shows the PAS5101PE pin diagram
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PAS5101PE Specification
Pin No.
Name
Type
Description
1
VDDMA
PWR
Analog main power, 2.5V.
2-3
NC
4
HSYNC
OUT
Horizontal synchronization signal.
5-8
NC
9
VSYNC
OUT
Vertical synchronization signal.
10
VDDMD
PWR
Digital main power, 2.5~3.3V.
11
PXCLK
OUT
Pixel clock output.
12
RESET
IN
Resets all registers to default values ( chip reset if high .)
13
SYSCLK
IN
Master clock input.
14
PX9
OUT
Digital data out.
15
VSSD
PWR
Digital ground.
16
PX7
OUT
Digital data out.
17-21
NC
22
PX8
OUT
Digital data out.
23
VDDD
PWR
Nc, Internal Regulator 1.8V
24
PX6
OUT
Digital data out.
25
PX0
OUT
Digital data out.
26
PX5
OUT
Digital data out.
27
PX1
OUT
Digital data out.
28-32
NC
33
PX4
OUT
Digital data out.
34
PX3
OUT
Digital data out.
35
PX2
OUT
Digital data out.
36
SCL
IN
I2C clock.
37
SDA
I/O
I2C data. Internal pull high resister is 10KΩ.
38
NC
39
VSSA
GND
Analog ground.
40-44
NC
45
PWDN
IN
Power Down (chip power down if high ).
46
VDDA
PWR
Analog power, 2.5V.
47
VREF
ANA
Internal voltage reference.
48
NC
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PAS5101PE Specification
2.
Sensor Array Format & Output Timing
2.1. Physical Sensor Array Format
Figure 2.1 Physical Sensor Array Format
2.2. Output Timing
1.3Mega mode ( 1288 x 1032 ) pixel readout:
H_Start[9:0] = 0,
V_Start[8:0] = 0,
LPF[7:0] = 1035,
Nov_Size_By4[7:0] = 63,
H_Size[9:0] = 1287,
V_Size[8:0]= 1035,
Figure 2.2 Inter-line timing
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PAS5101PE Specification
Figure 2.3 Inter-frame timing
Figure 2.4 Inter-frame timing @ Dark masked
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PAS5101PE Specification
3.
Block Diagram & Function Description
3.1. Block Diagram
Figure 3.1 Shows the PAS5101PE sensor block diagram
The PAS5101PE is a 1/3” CMOS imaging sensor with 1280 ( H ) x 1024 ( V ) physical pixels. The active
region of sensor array is 1288 ( H ) x 1032 ( V ) as shown in Figure 3.1. The sensor array is cover with
Bayer pattern color filters and μ-lens. The first pixel location ( 0,0 ) is programmable in 2 direction ( X
and Y ) and the default value is at the left-down side of sensor array.
After a programmable exposure time, the image is sampled first with CDS ( Correlated Double Sampling )
block to improve S/N ration and reduce fixed pattern noise.
Three analog gain stages are implemented before signal transferred by the 10-bits A/D converter. The
front gain stage ( FG ) can be programmed to fit the saturation level of sensor to the full-range input of
ADC. The programmable color gain stage ( CG ) is used to balance the luminance response difference
between B/G/R. The global gain stage ( GG ) is programmed to adapt the gain to the image luminance.
The fine gained signal will be digitized by the on-chip 10-bits A/D converter. After the image data has
been digitized, further alteration to the signal can be applied before the data is output.
3.2. Defect Compensation
The defect compensation block can detect the possible defect pixel and replace it with average output of
like-colored pixels on either side of defective pixel. There is no limitation in the capability of defect
number. This function is also Enable / Disable by user.
3.3. Companding Curves
The companding function is used to simulate the gamma curve and do non-linear transformation before
the data is output. There are 4 curves selected by setting register Compand_Sel as shown in Figure 3.2
and this function is also Enable / Disable by user.
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PAS5101PE Specification
Figure 3.2 Companding curves program by Compand_EnH and Compand_Sel
3.4. Power Down Mode
The PAS5101PE can be power down by setting register “SW_PwrDn” or by enable PWDN pin.
PAS5101PE supports two power down modes :
z
Software Power Down : Set register “SW_PwrDn” = 0x01 to power down all the internal
block except I2CTM.
z
Hardware Power Down : Pull PWDN pin to high to power down the chip. The chip will go
into standby mode.
3.5. Reset Mode
The PAS5101PE can be reset by setting “SW_Reset” or by enable Reset pin. PAS5101PE supports two
reset modes :
z
Software Reset : Set register “SW_Reset” = 0x01 to reset all the I2CTM registers. It’s only
reset the register value not reset full chip.
z
HardwareReset : Pull Reset pin to high to reset the full chip.
3.6. Window-of-Interest ( WOI )
Users are allowed to define window size as well as window location in PAS5101PE. The location of
window can be anywhere in the pixel array. Window size and window location is defined by register
“H_Start”, “V_Start”, “V_Size” and “H_Size”; The “H_Start” defines the starting column while
“V_Start” defines the starting rom of the window; The “H_Size” define the column width of the window
and “V_Size” defines the row depth of the window.
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PAS5101PE Specification
Figure 3.3
3.7.1. Output timing of WOI
Hardware windowing VGA ( 640x480 ) pixels readout ( With 4 dark lines ):
H_Start[9:0] = 0,
V_Start[8:0] = 0,
LPF[7:0] = 483,
Nov_Size_By4[7:0] = 63,
H_Size[9:0] = 639,
V_Size[8:0]= 483,
Figure 3.4 Inter-line timing of W.O.I
Figure 3.5 Inter-frame timing of W.O.I
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PAS5101PE Specification
3.7. Sub-Sampling
PAS5101PE can be programmed to output image in VGA、 QVGA and QQVGA size. In the VGA subsampling mode, both vertical and horizontal pixels are sub-sampling at 1/2; In QVGA sub-sampling mode,
both vertical and horizontal pixels are sub-sampling at 1/4; While in QQVGA sub-sampling mode, subsampling at 1/8. By programming Skip_Analog and Skip_Digital, The maximum sub-sampling rate is
1/32 ( Skip_Analog + Skip_Digital ).
3.7.1. Skip_Analog
Sub-sampling ( Skip_Analog ) to VGA ( 640x480 ) pixels readout ( With 4 dark lines ):
H_Start[9:0] = 0,
V_Start[8:0] = 0,
H_Size[9:0] = 1287,
V_Size[8:0]= 1035,
LPF[7:0] = 519,
Nov_Size_By4[7:0] = 63, Skip_Analog = 1 ( sub-sampling 1/2 )
Figure 3.6
Valid pixel = ( H_Size + 1 ) / Skip_Analog = 1288 / 2 = 644
Valid line = (((( V_Siez + 1 ) – 4 ) / Skip_Analog ) + 4) = (((( 1035 + 1 ) – 4 ) / 2 ) + 4 ) = 520
Figure 3.7 Inter-line timing of W.O.I
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PAS5101PE Specification
Figure 3.8 Inter-frame timing of W.O.I
3.7.2. Skip_Digital
Sub-sampling ( Skip_Digital ) to VGA ( 640x480 ) pixels readout ( With 4 dark lines ):
H_Start[9:0] = 0,
V_Start[8:0] = 0,
H_Size[9:0] = 1287,
LPF[7:0] = 1036,
Nov_Size_By4[7:0] = 63, Skip_Digital = 1
V_Size[8:0]= 1035,
Valid pixel = ( H_Size + 1 ) / Skip_Digital = 1288 / 2 = 644
Valid line = ( V_Siez + 1 ) / Skip_Digital = ( 1035 + 1 ) / 2 = 518
Figure 3.9 Inter-line timing
Figure 3.10 Inter-frame timing
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PAS5101PE Specification
4.
I2CTM Bus
PAS5101PE supports I2C bus transfer protocol and is acting as slave device. The 7 bits unique slave
address is “1000000” and supports receiving / transmitting speed up to 400KHz.
4.1. I2C Bus Overview
z
Only two wires SDA ( serial data ) and SCL ( serial clock ) carry information between the
devices connected to the I2C bus. Normally both SDA and SCL lines are open collector
structure and pull high by external pull-up resistors.
z
Only the master can initiates a transfer ( start ), generates clock signals, and terminates a
transfer ( stop ).
z
Start and stop condition : A high to low transition of the SDA line while SCA is high defines
a start condition. A low to high transition of the SDA line while SCA is high defines a stop
condition. Please refer to Figure 4.1.
z
Valid data : The data on the SDA line must be stable during the high period of the SCA clock.
Within each byte, MSB is always transferred first. Read / Write control bit is the LSB of the
first byte. Please refer to Figure 4.2.
z
Both the master and slave can transmit and receive data from the bus.
z
Acknowledge : The receiving device should pull down the SDA line during high period of the
SCL clock line when a complete byte was transferred by transmitter. In the case of a master
received data from a slave, the master does not generate an acknowledgment on the last byte
to indicate the end of a master read cycle.
Figure 4.1 Start and Stop conditions
Figure 4.2 Valid Data
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PAS5101PE Specification
4.2. Data Transfer Format
4.2.1. Master transmits data to salve ( write cycle )
z
S : Start.
z
A : Acknowledge by salve.
z
P : Stop.
z
RW : The LSB of 1ST byte to decide whether current cycle is read or write cycle. RW = 1 –
Read cycle, RW = 0 – Write cycle.
z
SUBADDRESS : The address values of PAS5101PE internal control registers. ( Please refer
to PAS5101PE register description )
During write cycle, the master generates start condition and then places the 1st byte data that are
combined slave address ( 7 bits ) with a read / write control bit to SDA line. After slave ( PAS5101PE )
issues acknowledgment, the master places 2nd byte ( Sub Address ) data on SDA line. Again follow the
PAS5101PE acknowledgment, the master places the 8 bits data on SDA line and transmit to PAS5101PE
control register ( address was assigned by 2nd byte ). After PAS5101PE issue acknowledgment, the master
can generate a stop condition to end of this write cycle. In the condition of multi-byte write, the
PAS5101PE sub-address is automatically increment after each DATA byte transferred. The data and A
cycles is repeat until last byte write. Every control registers value inside PAS5101PE can be
programming via this way.
4.2.2. Slave transmits data to master ( read cycle )
z
The sub-address was taken from previous write cycle.
z
The sub-address is automatically increment after each byte read.
z
Am : Acknowledge by master.
z
Note there is no acknowledgment from master after last byte read.
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PAS5101PE Specification
During read cycle, the master generates start condition and then place the 1st byte data that are combined
slave address ( 7 bits ) with a read / write control bit to SDA line. After issue acknowledgment, 8 bits
DATA was also placed on SDA line by PAS5101PE. The 8 bits data was read from PAS5101PE internal
control register that address was assigned by previous write cycle. Follow the master acknowledgment,
the PAS5101PE place the next 8 bits data ( address is increment automatically ) on SDA line and then
transmit to master serially. The DATA and Am cycles is repeat until the last byte read. After last byte
read, Am is no longer generated by master but instead by keep SDA line high. The slave ( PAS5101PE )
must releases SDA line to master to generate STOP condition.
4.3. I2CTM Bus Timing
4.4. I2CTM Bus Timing Specification
Parameter
Symbol
Standard Mode
Unit
Min.
Max
fscl
10
400
KHz
tHD:STA
4.0
-
μs
Low period of the SCL clock.
tLOW
4.7
-
μs
High period of the SCL clock.
tHIGH
0.75
-
μs
tSU;STA
4.7
-
μs
SCL clock frequency.
Hold time ( repeated ) Start condition.
After this period, the first clock pulse is generated.
Set-up time for a repeated START condition.
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PAS5101PE Specification
Data hold time. For I2C-bus device.
tHD;DAT
0
3.45
μs
Data set-up time.
tSU;DAT
250
-
ns
Rise time of both SDA and SCL signals.
tr
30
N.D.
ns
( notel )
Fall time of both SDA and SCL signals.
tf
30
N.D.
ns
( notel )
tSU;STO
4.0
-
μs
Bus free time between a STOP and START.
tBUF
4.7
-
μs
Capacitive load for each bus line.
Cb
1
15
pF
Noise margin at LOW level for each connected device.
( Including hysteresis )
VnL
0.1 VDD
-
V
Noise margin at HIGH level for each connected device.
( including hysteresis )
VnH
0.2 VDD
-
V
Set-up time for STOP condition.
Note : It depends on the “high” period time of SCL.
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PAS5101PE Specification
5.
Specifications
Absolute Maximum Ratings
-40℃ ~ +125℃
Ambient Storage Temperature
Supply Voltage ( with respect to ground )
VDDD
3V
VDDA
3V
VDDMD
4V
VDDMA
4V
All Input / Output Voltage ( with respect to ground )
-0.3V to VDDMD + 1V
Lead temperature, Surface-mount process
+230℃
ESD rating, Human Body model
2000V
DC Electrical Characteristics ( Ta = 0℃ ~ 70℃ )
Symbol
Parameter
Min.
Typ.
Max.
Unit
2.4
2.5
2.6
V
Type : POWER
VDDA
DC supply voltage – Analog
VDDD
DC supply voltage – Digital
VDDMD
DC supply voltage – I/O
IDD
Operating Current ( ~ 15fps / 2.5v )
20
mA
IPWDN
Power Down Current
10
μA
1.8
2.4
V
3.3
V
Type : IN & I/O Reset and System Clock
0.7 x
VDDMD
VIH
Input Voltage HIGH
V
VIL
Input Voltage LOW
0.3 x
VDDMD
V
CIN
Input Capacitor
10
pF
Type : OUT & I/O for PX 0 : 7, PXCLK, H/VSYNC & SDA, load 10pF, 1.2KΩ, 2.5V
VOH
Output Voltage HIGH
VOL
Output Voltage LOW
0.9 x
VDDMD
V
0.1 x
VDDMD
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V
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PAS5101PE Specification
AC Operating Condition
Symbol
Parameter
Sysclk
Pxclk
Min.
Typ.
Max.
Unit
Master clock frequency
48
MHz
Pixel clock output frequency
24
MHz
Sensor Characteristics
Parameter
Typ.
Unit
Sensitivity
TBD
V/Lux-sec
Signal to Noise Ratio
TBD
dB
Dynamic Range
TBD
dB
Temperature Range
Operation
-10 ~ +70
Stable Image
0 ~ +50
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℃
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25
26
27
PX0
PX5
PX1
30
29
28
24
23
22
PX6
PX8
21
NC
NC
NC
PX1
PX5
PX0
PX6
VDDD
PX8
NC
NC
31
20
NC
18
NC
NC
17
32
19
PX7
PAS5101PE
33
PX4
NC
34
NC
16
DGND
15
PX9
PX3
PX7
SYSCLK
35
PX2
PX2
PX4
RESET
36
SCL
37
SCL
SDA
SDA
VSSD
PXCLK
38
PX3
14
PX9
13
SYSCLK
12
RESET
11
PXCLK
VDDMD
AGND 39
NC
10
VDDMD
VSSA
VSYNC
9
40
VSYNC
NC
8
NC
NC
41
7
NC
NC
NC
NC
PWDN
VDDA
VREF
NC
VDDMA
NC
NC
HSY NC
NC
NC
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42
VDDMA
PWDN
46
45
43
44
VREF
VDDMA
HSY NC
47
48
1
2
3
4
5
6
U1
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VDDMD
PX9
SY SCLK
PX8
DGND
PX7
PXCLK
PX6
PX2
PX5
PX3
PX4
PX1
PX0
AGND
SDA
VDDMA
SCL
RESET
VSY NC
PWDN
HSY NC
0.1uF
C4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
JP1
Notes:
VDDMD is 2.5V ~ 3.3V sensor IO power.
VDDMA is 2.5V sensor analog power.
C1 should close to sensor VDDA and AGND.
C2 should close to sensor VREF and AGND.
DGND
AGND
VDDMA
0.1uF
C2
6.
CONN FLEX 24/SM
VREF
PAS5101PE Specification
Reference Circuit Schematic
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PAS5101PE Specification
7.
Package Information
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PAS5101PE Specification
8.
Reflow Profile for Non Lead-Free
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PAS5101PE Specification
9.
Lens & Holder
9.1. LarGan 40-900L
9.2. LarGan 40-519C
9.3. MaxEmil SS-4828GA
9.4. 久禾 PEH-0116-03AA
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