LMV112 40 MHz Dual Clock Buffer General Description Features The LMV112 is a high speed dual clock buffer designed for portable communications and accurate multi-clock systems. The LMV112 integrates two 40 MHz low noise buffers which optimizes application and out performs large discrete solutions. This device enables superb system operation between the base band and the oscillator signal path while eliminating crosstalk. (Typical values are: VSUPPLY = 2.7V and CL = 20 pF, unless otherwise specified) n Small signal bandwidth 40 MHz n Supply voltage range 2.4V to 5V n Slew rate 110 V/µs n Total supply current 1.6 mA n Shutdown current 59 µA n Rail-to-rail input and output n Individual buffer enable pins n Rapid Ton technology n Crosstalk rejection circuitry n 8-pin LLP, pin access packaging n Temperature range −40˚C to 85˚C National Semiconductor’s unique technology and design deliver accuracy, capacitance and load resistance while increasing the drive capability of the device. The low power consumption makes the LMV112 perfect for battery applications. The robust, independent, and flexible buffers are designed to provide the customer with the ability to manage complex clock signals in the latest wireless applications. The buffers deliver 110 V/µs internal slew rate with independent shutdown and duty cycle precision. The patented analog circuit drives capacitive loads beyond 20 pF. National’s proven biasing technique has 1V centering, rail-to-rail input/output unity gain, and AC coupled convenient inputs. These integrated cells save space and require no external bias resistors. National’s rapid recovery after disable optimizes performance and current consumption. The LMV112 offers individual enable pin controls and since there is no internal ground reference either single or split supply configurations offer additional system flexibility and power choices. The LMV112 is a proven replacement for any discrete circuitry and simplifies board layout while minimizing related parasitic components. The LMV112 is produced in the small LLP package which offers high quality while minimizing its use of PCB space. National’s advanced packaging offers direct PCB-IC evaluation via pin access. Applications n n n n n 3G mobile applications WLAN–WiMAX modules TD_SCDMA multi-mode MP3 and camera GSM modules Oscillator modules Typical Application 20135302 © 2005 National Semiconductor Corporation DS201353 www.national.com LMV112 40 MHz Dual Clock Buffer June 2005 LMV112 Absolute Maximum Ratings (Note 1) Soldering Information Infrared or Convection (35 sec.) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltages (V+– V−) Operating Ratings (Note 1) 5.5V Supply Voltage (V+ – V−) ESD Tolerance (Note 2) Human Body Machine Model −40˚C to +85˚C Package Thermal Resistance (Notes 3, 4) 200V LLP-8 (θJA) −65˚C to +150˚C Junction Temperature (Note 3) 2.4V to 5.0V Temperature Range (Notes 3, 4) 2000V Storage Temperature Range 235˚C 217˚C/W +150˚C 2.7V Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TJ = 25˚C, VDD = 2.7V, VSS = 0V, VCM = 1V, Enable1,2 = VDD, CL = 20 pF, RL = 30 kΩ, CCOUPLING = 1 nF. Boldface limits apply at temperature range extremes of operating condition. See (Note 4) Symbol Parameter Conditions Min (Note 6) Typ (Note 5) Max (Note 6) Units Frequency Domain Response SSBW Small Signal Bandwidth VIN = 0.63 VPP; −3 dB 40 MHz FPBW Full Power Bandwidth VIN = 1.6 VPP; −3 dB 28 MHz GFN Gain Flatness < 0.1 dB f > 100 kHz 3.4 MHz Distortion and Noise Performance en Input-Referred Voltage Noise f = 1 MHz 26 ISOLATION Output to Input f = 1 MHz 91 dB CT Crosstalk Rejection f = 26 MHz, PIN = 0 dBm 54 dB 0.1 VPP Step (10-90%), f = 1 MHz 7 ns nV/ Time Domain Response tr Rise Time tf Fall Time ts Settling Time to 0.1% 1 VPP Step, f = 1 MHz 6 ns 118 ns OS Overshoot 0.1 VPP Step, f = 1 MHz 41 % SR Slew Rate (Note 7) VIN = 1.6 VPP, f = 26 MHz 110 V/µs Static DC Performance IS Supply Current Enable1,2 = VDD ; No Load Enable1,2 = VSS ; No Load PSRR Power Supply Rejection Ratio DC (3.0V to 5.0V) ACL Small Signal Voltage Gain VOUT = 0.1 VPP VOS Output Offset Voltage TC VOS Temperature Coefficient Output Offset Voltage (Note 8) ROUT Output Resistance 1.6 2.0 2.1 mA 59 72 78 µA 58 57 68 0.97 0.95 1.01 1.05 1.07 V/V 0.4 16 17 mV 4 f = 100 kHz 0.5 f = 26 MHz 140 Enable = VDD 141 Enable = VSS 141 Enable = VDD 2.3 Enable = VSS 2.3 f = 26 MHz, Enable = VDD 10.4 f = 26 MHz, Enable = VSS 10.9 dB µV/˚C Ω Miscellaneous Performance RIN CIN ZIN Input Resistance per Buffer Input Capacitance per Buffer Input Impedance www.national.com 2 kΩ pF kΩ (Continued) Unless otherwise specified, all limits are guaranteed for TJ = 25˚C, VDD = 2.7V, VSS = 0V, VCM = 1V, Enable1,2 = VDD, CL = 20 pF, RL = 30 kΩ, CCOUPLING = 1 nF. Boldface limits apply at temperature range extremes of operating condition. See (Note 4) Symbol VO ISC Parameter Conditions Min (Note 6) Typ (Note 5) 2.65 2.63 2.69 Output Swing Positive VIN = VDD Output Swing Negative VIN = VSS Output Short-Circuit Current (Note 9) Sourcing −18 −13 −27 Sinking 20 16 30 10 Ven_hmin Enable High Active Minimum Voltage 1.2 Ven_lmax Enable Low Inactive Maximum Voltage 0.6 Max (Note 6) Units V 50 65 mV mA V 5V Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TJ = 25˚C, VDD = 5V, VSS = 0V, VCM = 1V, Enable1,2 = VDD, CL = 20 pF, RL = 30 kΩ, CCOUPLING = 1 nF. Boldface limits apply at temperature range extremes of operating condition. See (Note 4) Symbol Parameter Conditions Min (Note 6) Typ (Note 5) Max (Note 6) Units Frequency Domain Response SSBW Small Signal Bandwidth VIN = 0.63 VPP; −3 dB 42 MHz FPBW Full Power Bandwidth VIN = 1.6 VPP; −3 dB 31 MHz GFN Gain Flatness < 0.1 dB f > 100 kHz 4.9 MHz Distortion and Noise Performance en Input-Referred Voltage Noise f = 1 MHz 27 ISOLATION Output to Input f = 1 MHz 90 dB CT Crosstalk Rejection f = 26 MHz, PIN = 0 dBm 61 dB 0.1 VPP Step (10-90%), f = 1 MHz 7 ns 6 ns ns nV/ Time Domain Response tr Rise Time tf Fall Time ts Settling Time to 0.1% 1 VPP Step, f = 1 MHz 80 OS Overshoot 0.1VPP Step, f = 1 MHz 20 % SR Slew Rate (Note 7) VIN = 1.6 VPP, f = 26 MHz 120 V/µs Static DC Performance IS Supply Current Enable1,2 = VDD ; No Load Enable1,2 = VSS ; No Load PSRR Power Supply Rejection Ratio DC (3.0V to 5.0V) ACL Small Signal Voltage Gain VOUT = 0.1 VPP VOS Output Offset Voltage TC VOS Temperature Coefficient Output Offset Voltage (Note 8) ROUT Output Resistance 2.5 3.5 3.8 mA 62 80 89 µA 58 57 68 0.99 0.97 1.00 1.01 1.03 V/V 1.3 16 17 mV 3 f = 100 kHz 0.5 f = 26 MHz 118 3 dB µV/˚C Ω www.national.com LMV112 2.7V Electrical Characteristics LMV112 5V Electrical Characteristics (Continued) Unless otherwise specified, all limits are guaranteed for TJ = 25˚C, VDD = 5V, VSS = 0V, VCM = 1V, Enable1,2 = VDD, CL = 20 pF, RL = 30 kΩ, CCOUPLING = 1 nF. Boldface limits apply at temperature range extremes of operating condition. See (Note 4) Symbol Parameter Conditions Min (Note 6) Typ (Note 5) Max (Note 6) Units Miscellaneous Performance RIN CIN ZIN VO ISC Input Resistance per Buffer Input Capacitance per Buffer Input Impedance Enable = VDD 134 Enable = VSS 134 Enable = VDD 2.0 Enable = VSS 2.0 f = 26 MHz, Enable = VDD 7.2 f = 26 MHz, Enable = VSS 8.0 Output Swing Positive VIN = VDD 4.96 4.94 Output Swing Negative VIN = VSS Output Short-Circuit Current (Note 9) Sourcing -40 -28 -68 Sinking 70 50 98 kΩ pF kΩ 4.99 10 Ven_hmin Enable High Active Minimum Voltage 1.2 Ven_lmax Enable Low Inactive Maximum Voltage 0.6 V 40 55 mV mA V Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics Tables. Note 2: Human Body Model: 1.5 kΩ in series with 100 pF. Machine Model: 0Ω in series with 200 pF. Note 3: The maximum power dissipation is a function of TJ(MAX), θJA , and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) − TA) / θJA. All numbers apply for packages soldered directly onto a PC board. Note 4: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA . There is no guarantee of parametric performance as indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Note 5: Typical Values represent the most likely parametric norm. Note 6: All limits are guaranteed by testing or statistical analysis. Note 7: Slew rate is the average of the positive and negative slew rate. Note 8: Average Temperature Coefficient is determined by dividing the changing in a parameter at temperature extremes by the total temperature change. Note 9: Short−Circuit test is a momentary test. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150˚C. www.national.com 4 LMV112 Block Diagram 20135301 Pin Description Pin No. Pin Name 1 VDD Voltage supply connection 2 IN 1 Input 1 3 IN 2 Input 2 4 ENABLE 2 5 VSS 6 OUT 2 7 OUT 1 8 ENABLE 1 Description Enable buffer 2 Ground connection Output 2 Output 1 Enable buffer 1 Connection Diagram 8-Pin LLP 20135331 Top View Ordering Information Package Part Number 8-Pin LLP No Pull Back LMV112SD LMV112SDX Package Marking Transport Media 1k Units Tape and Reel 112SD 4.5k Units Tape and Reel 5 NSC Drawing SDA08A www.national.com LMV112 Typical Performance Characteristics TJ = 25˚C, VDD = 2.7V, VSS = 0V, Enable1,2 = VDD, CL = 20 pF, RL = 30 kΩ and CCOUPLING = 1 nF, unless otherwise specified. Frequency Response Phase Response 20135303 20135304 Frequency Response Over Temperature Frequency Response Over Temperature 20135305 20135306 Phase Response Over Temperature Phase Response Over Temperature 20135307 www.national.com 20135308 6 Full Power Bandwidth Gain Flatness 0.1 dB (GFN) 20135310 20135309 Voltage Noise Isolation Output to Input vs. Frequency 20135329 20135317 Crosstalk Rejection vs. Frequency Transient Response Positive 20135314 20135311 7 www.national.com LMV112 Typical Performance Characteristics TJ = 25˚C, VDD = 2.7V, VSS = 0V, Enable1,2 = VDD, CL = 20 pF, RL = 30 kΩ and CCOUPLING = 1 nF, unless otherwise specified. (Continued) LMV112 Typical Performance Characteristics TJ = 25˚C, VDD = 2.7V, VSS = 0V, Enable1,2 = VDD, CL = 20 pF, RL = 30 kΩ and CCOUPLING = 1 nF, unless otherwise specified. (Continued) Transient Response Negative Small Signal Pulse Response 20135312 20135325 Small Signal Pulse Response Large Signal Pulse Response 20135326 20135327 Large Signal Pulse Response ISUPPLY vs. VSUPPLY 20135328 www.national.com 20135332 8 ISUPPLY vs. VSUPPLY ISUPPLY vs. VSUPPLY 20135333 20135334 PSRR vs. Frequency VOS vs. VSUPPLY 20135324 20135335 ROUT vs. Frequency Input Impedance vs. Frequency 20135316 20135315 9 www.national.com LMV112 Typical Performance Characteristics TJ = 25˚C, VDD = 2.7V, VSS = 0V, Enable1,2 = VDD, CL = 20 pF, RL = 30 kΩ and CCOUPLING = 1 nF, unless otherwise specified. (Continued) LMV112 Typical Performance Characteristics TJ = 25˚C, VDD = 2.7V, VSS = 0V, Enable1,2 = VDD, CL = 20 pF, RL = 30 kΩ and CCOUPLING = 1 nF, unless otherwise specified. (Continued) VOUT vs. IOUT (Sourcing) VOUT vs. IOUT (Sourcing) 20135336 20135337 VOUT vs. IOUT (Sinking) VOUT vs. IOUT (Sinking) 20135338 20135339 ISC Sourcing vs. VSUPPLY over Temperature ISC Sinking vs. VSUPPLY over Temperature 20135341 www.national.com 20135342 10 ISUPPLY vs VENABLE ISUPPLY vs VENABLE 20135347 20135348 11 www.national.com LMV112 Typical Performance Characteristics TJ = 25˚C, VDD = 2.7V, VSS = 0V, Enable1,2 = VDD, CL = 20 pF, RL = 30 kΩ and CCOUPLING = 1 nF, unless otherwise specified. (Continued) LMV112 A block diagram of the isolation is shown in Figure 2. Crosstalk rejection between buffers prevents signals from affecting each other. Figure 2 shows a Base band IC and a Bluetooth module as examples of this. See the characteristic graphic labeled “Crosstalk Rejection vs. Frequency” for more information. Application Section GENERAL The LMV112 is designed to minimize the effects of spurious signals from the base band chip to the oscillator. Also the influence of varying load resistance and capacitance to the oscillator is minimized, while the drive capability is increased. The inputs of the LMV112 are internally biased at 1V, making AC coupling possible without external bias resistors. To optimize current consumption, the buffer not in use can be disabled by connecting the enable pin to VSS. The LMV112 has no internal ground reference; therefore, either single or split supply configurations can be used. The LMV112 is an easy replacement for discrete circuitry. It simplifies board layout and minimizes the effect of layout related parasitic components. 20135345 INPUT CONFIGURATION AC coupling is made possible by biasing the input. A large DC load at the oscillator input could change the load impedance and therefore it’s oscillating frequency. To avoid external resistors the inputs are internally biased. This biasing is set at 1V as depicted in Figure 1. Because this biasing is set at 1V, the maximum amplitude of the AC signal is 2 VPP. The coupling capacitance should be large enough to let the AC signal pass. This is a unity gain buffer with rail-to-rail inputs and outputs. FIGURE 2. Isolation Block Diagram DRIVING CAPACITIVE LOADS Each buffer can drive a capacitive load. Be aware that every capacitor directly connected to the output becomes part of the loop of the buffer. In most applications the load consists of the capacitance of copper tracks and the input capacitance of the application blocks. Capacitance reduces the gain/phase margin and increases the instability. It leads to peaking in the frequency response and in extreme situations oscillations can occur. To drive a large capacitive load it is recommended that a series resistor is included between the buffer and the load capacitor. The best value for this isolation resistance is often found by experimentation. The LMV112 datasheet reflects measurements with capacitance loads of 20 pF at the output of the buffers. Most common applications will probably use a lower capacitance load, which will result in lower peaking and significantly greater bandwidth, see Figure 3. 20135344 FIGURE 1. Input Configuration FREQUENCY PULLING Frequency pulling is the frequency variation of an oscillator caused by a varying load. In the typical application, the load of the oscillator is a fixed capacitor (C1) and the input impedance of the buffer. To keep the input impedance as constant as possible, the input is biased at 1V, even when the part is disabled. A simplified schematic of the input configuration is shown in Figure 1. 20135346 FIGURE 3. Bandwidth and Peaking ISOLATION AND CROSSTALK Output to input isolation prevents the clock from being affected by spurious signals generated by the digital blocks at the output buffer. See the characteristic graphic entitled “Isolation Output to Input vs. Frequency.” www.national.com 12 Another important issue is the value of the components, which also determines the sensitivity to disturbances. Resistor value’s should be but avoid using values that cause a significant increase in power consumption while loading inputs or outputs to heavily. (Continued) LAYOUT DESIGN RECOMMENDATION Careful consideration for circuitry design and PCB layout will eliminate problems and will optimize the performance of the LMV112. It is best to have the same ground plane on the PCB for all power supply lines. This gives a low impedance return path for all decoupling and other ground connections. To ensure a clean supply voltage it is best to place decoupling capacitors close to the LMV112, between VCC and ground. The output of the VCO must be correctly terminated with proper load impedance. 13 www.national.com LMV112 Application Section LMV112 40 MHz Dual Clock Buffer Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin LLP NS Package Number SDA08A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. Leadfree products are RoHS compliant. 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