SN74AUP2G08 LOW-POWER DUAL 2-INPUT POSITIVE-AND GATE www.ti.com SCES681A – JANUARY 2008 – REVISED JANUARY 2008 FEATURES 1 • Available in the Texas Instruments NanoFree™ Package • Low Static-Power Consumption (ICC = 0.9 µA Max) • Low Dynamic-Power Consumption (Cpd = 4.3 pF Typ at 3.3 V) • Low Input Capacitance (Ci = 1.5 pF Typ) • Low Noise – Overshoot and Undershoot <10% of VCC • Ioff Supports Partial-Power-Down Mode Operation • Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typ at 3.3 V) • • • 2 8 1 2 W IE7 V RE 3 P4 6 5 RSE PACKAGE (TOP VIEW) VCC 1Y 2B 2A YZP PACKAGE (BOTTOM VIEW) 1Y 1 2B 2 2A R 3 P 8 7 EW VI 6 E 4 5 1A GND 2Y 1B 1A 4 5 3 6 2 7 1 8 YFP PACKAGE (BOTTOM VIEW) GND 2Y 1B 1A 2A 2B 1Y VCC 45 36 27 1 8 2A 2B 1Y VCC 1B 2Y GND 1A 1B 2Y GND • VCC DCU PACKAGE (TOP VIEW) • • • Wide Operating VCC Range of 0.8 V to 3.6 V Optimized for 3.3-V Operation 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation tpd = 4.3 ns Max at 3.3 V Suitable for Point-to-Point Applications Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 – 2000-V Human-Body Model (A114-B, Class II) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) See mechanical drawings for dimensions. DESCRIPTION/ORDERING INFORMATION The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2). Static-Power Consumption Dynamic-Power Consumption (µA) (pF) Switching Characteristics at 25 MHz† 100% 100% 3.5 80% 80% 2.5 40% 60% 3.3-V Logic† 3.3-V Logic LVC † 40% AUP 0% Input 2 1.5 1 Output 0.5 20% 20% 0% Voltage − V 60% 3 AUP 0 −0.5 † Single, dual, and triple gates † Figure 1. AUP – The Lowest-Power Family 0 5 10 15 20 25 30 Time − ns 35 40 45 AUP1G08 data at CL = 15 pF Figure 2. Excellent Signal Integrity 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated SN74AUP2G08 LOW-POWER DUAL 2-INPUT POSITIVE-AND GATE www.ti.com SCES681A – JANUARY 2008 – REVISED JANUARY 2008 DESCRIPTION/ORDERING INFORMATION (CONTINUED) This dual 2-input positive-AND gate performs the Boolean function Y + A • B or Y + A ) B in positive logic. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION PACKAGE (1) (2) TA –40°C to 85°C (1) (2) (3) ORDERABLE PART NUMBER TOP-SIDE MARKING (3) NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YFP Reel of 3000 SN74AUP2G08YFPR _ _ _ HE_ NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) Reel of 3000 SN74AUP2G08YZPR _ _ _ HE_ QFN – RSE Reel of 3000 SN74AUP2G08RSER HE VSSOP – DCU Reel of 3000 SN74AUP2G08DCUR H08_ Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). DCU – The actual top-side marking has one additional character to denote assembly/test site. FUNCTION TABLE INPUTS B OUTPUT Y L L L L H L A H L L H H H LOGIC DIAGRAM (POSITIVE LOGIC) 1A 1B 2A 2B 1 2 7 1Y 5 6 3 2Y Pin numbers shown are for DCU, YFP, and YZP packages. 2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN74AUP2G08 SN74AUP2G08 LOW-POWER DUAL 2-INPUT POSITIVE-AND GATE www.ti.com SCES681A – JANUARY 2008 – REVISED JANUARY 2008 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 4.6 V VI Input voltage range (2) –0.5 4.6 V –0.5 4.6 V –0.5 VCC + 0.5 (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off state VO Output voltage range in the high or low state (2) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±20 mA Continuous current through VCC or GND ±50 mA DCU package θJA Tstg (1) (2) (3) Package thermal impedance (3) 227 RSE package 253 YFP package 98.8 YZP package 102 Storage temperature range V –65 150 °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN74AUP2G08 3 SN74AUP2G08 LOW-POWER DUAL 2-INPUT POSITIVE-AND GATE www.ti.com SCES681A – JANUARY 2008 – REVISED JANUARY 2008 RECOMMENDED OPERATING CONDITIONS (1) VCC Supply voltage VCC = 0.8 V VIH High-level input voltage VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V MIN MAX 0.8 3.6 Low-level input voltage VI Input voltage VO Output voltage 0.65 × VCC High-level output current 2 0 0.35 × VCC VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V 0.7 Low-level output current 3.6 0 Input transition rise or fall rate TA Operating free-air temperature (1) 4 V VCC V VCC = 0.8 V –20 µA VCC = 1.1 V –1.1 VCC = 1.4 V –1.7 VCC = 1.65 –1.9 VCC = 2.3 V –3.1 mA –4 VCC = 0.8 V 20 VCC = 1.1 V 1.1 VCC = 1.4 V 1.7 VCC = 1.65 V 1.9 VCC = 2.3 V 3.1 VCC = 3 V Δt/Δv V 0.9 0 VCC = 3 V IOL V 1.6 VCC = 3 V to 3.6 V IOH V VCC VCC = 0.8 V VIL UNIT µA mA 4 VCC = 0.8 V to 3.6 V –40 200 ns/V 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN74AUP2G08 SN74AUP2G08 LOW-POWER DUAL 2-INPUT POSITIVE-AND GATE www.ti.com SCES681A – JANUARY 2008 – REVISED JANUARY 2008 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH TEST CONDITIONS VCC TA = –40°C to 85°C MAX MIN 0.8 V to 3.6 V VCC – 0.1 VCC – 0.1 IOH = –1.1 mA 1.1 V 0.75 × VCC 0.7 × VCC IOH = –1.7 mA 1.4 V 1.11 1.03 IOH = –1.9 mA 1.65 V 1.32 1.3 2.05 1.97 1.9 1.85 2.72 2.67 2.3 V IOH = –3.1 mA IOH = –2.7 mA 3V IOH = –4 mA IOL = 20 µA 0.8 V to 3.6 V IOL = 1.1 mA 2.6 MAX UNIT V 2.55 0.1 0.1 1.1 V 0.3 × VCC 0.3 × VCC IOL = 1.7 mA 1.4 V 0.31 0.37 IOL = 1.9 mA 1.65 V 0.31 0.35 0.31 0.33 0.44 0.45 0.31 0.33 0.44 0.45 0 V to 3.6 V 0.1 0.5 µA IOL = 2.3 mA 2.3 V IOL = 3.1 mA IOL = 2.7 mA 3V IOL = 4 mA II TYP IOH = –20 µA IOH = –2.3 mA VOL TA = 25°C MIN A or B input VI = GND to 3.6 V V Ioff VI or VO = 0 V to 3.6 V 0V 0.2 0.6 µA ΔIoff VI or VO = 0 V to 3.6 V 0 V to 0.2 V 0.2 0.9 µA ICC VI = GND or IO = 0 (VCC to 3.6 V) 0.8 V to 3.6 V 0.5 0.9 µA ΔICC VI = VCC – 0.6 V (1), IO = 0 40 50 µA Ci VI = VCC or GND Co VO = GND (1) 3.3 V 0V 2 3.6 V 2 0V 3 pF pF One input at VCC – 0.6 V, other input at VCC or GND Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN74AUP2G08 5 SN74AUP2G08 LOW-POWER DUAL 2-INPUT POSITIVE-AND GATE www.ti.com SCES681A – JANUARY 2008 – REVISED JANUARY 2008 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL = 5 pF (unless otherwise noted) (see Figure 3 and Figure 4) PARAMETER FROM (INPUT) TO (OUTPUT) VCC TA = 25°C MIN 0.8 V tpd A or B Y TYP TA = –40°C to 85°C MAX MIN MAX UNIT 19.8 1.2 V ± 0.1 V 0.5 7.8 18.8 0.5 19.8 1.5 V ± 0.1 V 0.5 5.4 11.8 0.5 13.9 1.8 V ± 0.15 V 0.5 4.3 9 0.5 11.1 2.5 V ± 0.2 V 0.5 3 5.7 0.5 7.8 3.3 V ± 0.3 V 0.5 2.4 4.6 0.5 5.9 ns SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL = 10 pF (unless otherwise noted) (see Figure 3 and Figure 4) PARAMETER FROM (INPUT) TO (OUTPUT) VCC TA = 25°C MIN 0.8 V tpd 6 A or B Y TYP TA = –40°C to 85°C MAX MIN MAX UNIT 23.1 1.2 V ± 0.1 V 0.5 8.9 21.1 0.5 22 1.5 V ± 0.1 V 0.8 6.3 13.2 0.5 15.1 1.8 V ± 0.15 V 0.6 5 10.1 0.5 12.2 2.5 V ± 0.2 V 0.5 3.6 7.4 0.5 9 3.3 V ± 0.3 V 0.5 2.9 5.1 0.5 6.5 Submit Documentation Feedback ns Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN74AUP2G08 SN74AUP2G08 LOW-POWER DUAL 2-INPUT POSITIVE-AND GATE www.ti.com SCES681A – JANUARY 2008 – REVISED JANUARY 2008 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3 and Figure 4) PARAMETER FROM (INPUT) TO (OUTPUT) TA = 25°C VCC MIN TYP 0.8 V tpd A or B Y TA = –40°C to 85°C MAX MIN MAX UNIT 24.7 1.2 V ± 0.1 V 0.5 9.8 21.7 0.5 22.7 1.5 V ± 0.1 V 1.3 4.6 14 0.5 15.7 1.8 V ± 0.15 V 1.2 5.5 10.6 0.5 12.6 2.5 V ± 0.2 V 0.7 4 7 0.5 8.9 3.3 V ± 0.3 V 0.9 3.3 5.5 0.5 6.9 ns SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 3 and Figure 4) PARAMETER FROM (INPUT) TO (OUTPUT) VCC TA = 25°C MIN 0.8 V tpd A or B Y TYP TA = –40°C to 85°C MAX MIN MAX 12.6 26.3 0.5 27 UNIT 31.8 1.2 V ± 0.1 V 0.6 1.5 V ± 0.1 V 2.5 9 16.6 0.7 18.3 1.8 V ± 0.15 V 2.3 7.3 12.9 0.5 14.8 2.5 V ± 0.2 V 2.1 5.4 8.8 0.8 10.5 3.3 V ± 0.3 V 2.1 4.5 6.7 0.9 8.2 ns OPERATING CHARACTERISTICS TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS f = 10 MHz VCC TYP 0.8 V 4 1.2 V ± 0.1 V 4 1.5 V ± 0.1 V 4 1.8 V ± 0.15 V 4 2.5 V ± 0.2 V 4.1 3.3 V ± 0.3 V 4.3 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN74AUP2G08 UNIT pF 7 SN74AUP2G08 LOW-POWER DUAL 2-INPUT POSITIVE-AND GATE www.ti.com SCES681A – JANUARY 2008 – REVISED JANUARY 2008 PARAMETER MEASUREMENT INFORMATION (Propagation Delays, Setup and Hold Times, and Pulse Duration) From Output Under Test CL (see Note A) 1 MΩ LOAD CIRCUIT CL VM VI VCC = 0.8 V VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC tw VCC Input VCC/2 VCC/2 VI VM Input 0V VM VOLTAGE WAVEFORMS PULSE DURATION 0V tPLH tPHL VOH VM Output VM VOL tPHL VCC Timing Input 0V tPLH tsu VOH VM Output th VCC VM VOL Data Input VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS NOTES: A. B. C. D. E. VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. The outputs are measured one at a time, with one transition per measurement. tPLH and tPHL are the same as tpd. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms 8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN74AUP2G08 SN74AUP2G08 LOW-POWER DUAL 2-INPUT POSITIVE-AND GATE www.ti.com SCES681A – JANUARY 2008 – REVISED JANUARY 2008 PARAMETER MEASUREMENT INFORMATION (Enable and Disable Times) 2 × VCC S1 5 kΩ From Output Under Test GND CL (see Note A) 5 kΩ TEST S1 tPLZ/tPZL tPHZ/tPZH 2 × VCC GND LOAD CIRCUIT CL VM VI V∆ VCC = 0.8 V VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.15 V 5, 10, 15, 30 pF VCC/2 VCC 0.15 V 5, 10, 15, 30 pF VCC/2 VCC 0.3 V VCC Output Control Output Waveform 1 S1 at 2 × VCC (see Note B) VCC/2 0V tPZL tPLZ VCC VCC/2 tPZH Output Waveform 2 S1 at GND (see Note B) VCC/2 VOL + V∆ VOL tPHZ VCC/2 VOH - V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. All parameters and waveforms are not applicable to all devices. Figure 4. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN74AUP2G08 9 PACKAGE OPTION ADDENDUM www.ti.com 22-Jul-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74AUP2G08YFPR ACTIVE DSBGA YFP 8 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM SN74AUP2G08YZPR ACTIVE DSBGA YZP 8 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Oct-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) SN74AUP2G08YFPR DSBGA YFP 8 3000 180.0 SN74AUP2G08YZPR DSBGA YZP 8 3000 180.0 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 8.4 0.83 1.63 0.59 4.0 8.0 Q1 8.4 1.1 2.1 0.56 4.0 8.0 Q1 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 20-Oct-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AUP2G08YFPR DSBGA YFP 8 3000 220.0 220.0 34.0 SN74AUP2G08YZPR DSBGA YZP 8 3000 220.0 220.0 34.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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