DP83231 CRD TM Device (FDDI Clock Recovery Device) General Description Features The DP83231 CRD device is a clock recovery device that has been designed for use in 100 Mbps FDDI (Fiber Distributed Data Interface) networks. The device receives serial data from a Fiber Optic Receiver in differential ECL NRZI 4B/5B group code format and outputs resynchronized NRZI received data and a 125 MHz received clock in differential ECL format for use by the DP83251/55 PLAYERTM device. Y Y Y Y Y Y Clock recovery at 100 Mbps data rate Internal 250 MHz VCO Ð 0.1% VCO operating range Ð Crystal controlled Precision window centering delay line Single a 5V supply 28-pin PLCC package BiCMOS processing TL/F/10384 – 1 FIGURE 1-1. FDDI Chip Set Block Diagram TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. BSITM , BMACTM , PLAYERTM , CDDTM and CRDTM are trademarks of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/10384 RRD-B30M105/Printed in U. S. A. DP83231 CRD Device (FDDI Clock Recovery Device) February 1991 Table of Contents 5.0 DETAILED INFORMATION 1.0 FDDI CHIP SET OVERVIEW 5.1 Special External Components 2.0 FUNCTIONAL DESCRIPTION 5.2 Layout Recommendations 3.0 PIN DESCRIPTIONS 5.3 Input and Output Schematics 4.0 ELECTRICAL CHARACTERISTICS 5.4 Debug Procedure 4.1 Absolute Maximum Ratings 5.5 AC Test Circuits 4.2 Recommended Operating Conditions 4.3 DC Electrical Characteristics 4.3 AC Electrical Characteristics 2 1.0 FDDI Chip Set Overview National Semiconductor’s FDDI chip set consists of five components as shown in Figure 1-1. For more information about the other devices in the chip set, consult the appropriate data sheets and application notes. DP83261 BMAC TM Device Media Access Controller The BMAC device implements the Timed Token Media Access Control protocol defined by the ANSI FDDI X3T9.5 MAC Standard. DP83231 CRD TM Device Clock Recovery Device Features The Clock Recovery Device extracts a 125 MHz clock from the incoming bit stream. # All of the standard defined ring service options # Full duplex operation with through parity # Supports all FDDI Ring Scheduling Classes (Synchro- Features nous, Asynchronous, etc.) # PHY Layer loopback test # Crystal controlled # Clock locks in less than 85 ms # Supports Individual, Group, Short, Long, and External Addressing # # # # DP83241 CDD TM Device Clock Distribution Device From a 12.5 MHz reference, the Clock Distribution Device synthesizes the 125 MHz, 25 MHz and 12.5 MHz clocks required by the BSI, BMAC, and PLAYER devices. Generates Beacon, Claim, and Void frames internally Extensive ring and station statistics gathering Extensions for MAC level bridging Separate management port that is used to configure and control operation # Multi-frame streaming interface DP83251/55 PLAYER TM Device Physical Layer Controller DP83265 BSI TM Device System Interface The PLAYER device implements the Physical Layer (PHY) protocol as defined by the ANSI FDDI PHY X3T9.5 Standard. The BSI Device implements an interface between the National FDDI BMAC device and a host system. Features Features # # # # # # # # # # # # # # # # # # # 4B/5B encoders and decoders Framing logic Elasticity Buffer, Repeat Filter, and Smoother Line state detector/generator Link error detector Configuration switch Full duplex operation Separate management port that is used to configure and control operation. In addition, the DP83255 contains an additional PHYÐData.request and PHYÐData.indicate port required for concentrators and dual attach stations. 3 32-bit wide Address/Data path with byte parity Programmable transfer burst sizes of 4 or 8 32-bit words Interfaces to low-cost DRAMs or directly to system bus Provides 2 Output and 3 Input Channels Supports Header/Info splitting Efficient data structures Programmable Big or Little Endian alignment Full Duplex data path allows transmission to self Comfirmation status batching services Receive frame filtering services Operates from 12.5 MHz to 25 MHz synchronously with host system 2.0 Functional Description in the direction which will reduce their phase error. When the phase of the VCO and the incoming data are aligned, a VCO divided by two signal can be used as the Receive Clock output. Because the two PLL’s share a common VCO feedback path, the cutoff frequency of the loop filters associated with the second PLL are specified to be approximately 10 times lower than the cutoff frequency of the first PLL to prevent instability between the two loops. The delay line associated with the second PLL precisely centers the data transitions within the data window. The delay line remains accurate independent of temperature, power supply, IC process variation or external components. The design also ensures that the charge pump up and down circuits both produce an active pulse at each zero phase crossing when in lock to guarantee a linear phase detector gain characteristic. The CRD continually monitors the data frequency at the selected data inputs. If this input frequency drops below (/2 the minimum allowed frequency (about 3 MHz) the CRD resets itself by internally deasserting CRD-EN. This centers the crystal frequency, and restarts the internal VCO. The CRD EN pin is provided to initialize the CLK DET circuitry and enable the crystal to track incoming data. The part is enabled when this pin is active High. Deassertion of this pin will cause the CLK DET circuitry and the OSC FLTR g pins to be disabled in a manner similar to when legitimate data is not being received. Deassertion of the CRD EN pin also momentarily causes (1 ms) the VCO FLTR pin to be pulled to ground and stops the VCO and RXC g outputs. After this time, the VCO will be restarted and its output frequency will climb quickly to approximately 250 MHz. The device is capable of locking on to a stream of Halt or Master line states in less than 100 ms when using a 10.41666 MHz crystal to govern the 250 MHz VCO. Lock on time for a stream of Idle line states is less than 10 ms once Halt or Master line status is obtained. During quiet line conditions the chip will output a continual stream of Received Clock whose frequency will be within less than 0.1% of the upstream station’s data rate. The Received Data outputs are always active. Prior to the CLK DET output transitioning active High, the Received Data outputs may issue invalid data (see Typical Waveforms). When the device is locked, Received Data is presented on the falling edge of the Receive Clock output insuring sufficient setup and hold margin for the receiving device. An ECL to TTL translator is provided on the chip to convert the FORX’s ECL signal detect output level to TTL for use by the PLAYER device. The DP83231 uses two phase locked loops (PLL’s) to perform the clock recovery function. The function of the first PLL is to establish a 250 MHz Voltage Controlled Oscillator (VCO) with a narrow frequency range which can be pulled by the second PLL. The function of the second PLL is to force this same VCO to track the incoming data so that a Receive Clock output and a data synchronizing flip-flop can be driven from it. Operation of the VCO at 250 MHz ensures that the received clock output operating at half of the VCO frequency has a 50% duty cycle waveform independent of any VCO waveform dissymmetry. The first PLL uses a 10.41666 MHz crystal as a pullable frequency reference to generate the 250 MHz VCO. The limited frequency pulling range of the crystal ensures that the capture range of the 250 MHz VCO is limited to less than 0.1% of the specified data transition rate, thus eliminating the possibility of fractional or harmonic lock up modes. The output of the VCO is divided by twenty four and applied to the feedback input of the phase detector in the first PLL. The phase detector compares the phase of the VCO divided by twenty four signal against the phase of the crystal to maintain VCO lock at 250 MHz. If the phase transition of the signal derived from the VCO arrives at the phase detector before that of the crystal, the charge pump circuitry will apply a negative current pulse to the VCO FLTR node who’s width is proportional to the phase error. The charge pulled out of the filter capacitors will drive the voltage applied to the VCO downward. This reduction in the VCO’s control voltage will slow down the frequency of the VCO and will appear during successive cycles to reduce the VCO’s phase and frequency error. As the frequency of the crystal varies, in response to the second PLL, the frequency of the 250 MHz VCO will change in an attempt to remain 24 times the crystal’s frequency. The second PLL delays the phase transitions of the selected incoming stream of data (DATA g or LBD g ), and then compares them against the phase transitions of a gated 125 MHz signal derived from the 250 MHz VCO. The delayed incoming data is applied to the reference input of a phase detector and the gated VCO signal is applied to it’s feedback input. If the positive and negative phase transitions of the incoming data do not line up with the phase transitions of the gate VCO signal, the charge pump circuitry associated with that phase detector will apply current pulses to the OSC FLTR g nodes which are proportional to the phase error. The change in the charge on the filter capacitors will modify the reverse bias on the varactors in the crystal’s tank circuit thus causing the frequency of the 10.41666 MHz crystal (and consequently the VCO) to shift 4 2.0 Functional Description (Continued) TL/F/10384 – 3 FIGURE 2-1. DP83231 Block Diagram 28-Pin PLCC Package TL/F/10384 – 2 Order Number DP83231AV See NS Package Number V28A TL/F/10384 – 4 FIGURE 2-2. DP83231 Pinout FIGURE 2-3. System Connection Diagram 5 3.0 Pin Descriptions Pin No. I/O DATA a , DATAb Symbol 8, 9 I DATA g : 4B/5B serial NRZI data inputs originating from a fiber optic receiver and presented for the purpose of resynchronization and clock recovery. These differential 100k ECL compatible inputs are selected when the ELB input is at a logic Low level. Description LBD a , LBDb 25, 24 I Loopback Data g : 4B/5B serial NRZI data inputs originating from a local PLAYER device and presented for the purpose of station diagnostics. These differential 100k ECL compatible inputs are selected when the ELB input is at a logic High level. ELB 4 I Enable Loopback: TTL compatible input which selects between the DATA g inputs or the LBD g inputs. The LBD inputs are selected when the ELB pin is at a logic High level and the DATA inputs when at a logic Low level. CLK DET 6 O Clock Detect: CMOS output used to indicate that the chip has detected the presence of a continuous data frequency greater than 3.0 MHz. A logic High level on the output will indicate that valid input data has been detected. CRD EN 7 I CRD Enable: TTL compatible input which directs the differential charge pump outputs to either operate the crystal oscillator at the center of its operating range or to track out the VCO phase errors in the second PLL. The CRD EN input will reset the CLK DET function and will force the oscillator to the center of its operating range when at a logic LOW level and will allow normal PLL tracking operation when at a logic High level. Deassertion of the CRD EN input will momentarily stop the VCO. OSC FLTR a , OSC FLTRb 23, 22 O Oscillator Filter g : The differential charge pump up and down outputs which are part of the second PLL. A three element filter should be connected to each of these pins which consists of one capacitor in parallel with a resistor and another capacitor to ground. These outputs are driven to their maximum upper operating level when the CRD EN pin is at a logic LOW level or when valid data frequencies are not recognized at the data inputs. DIF AMP OUT 21 O Differential Amplifier Output: The differential amplifier output associated with the second PLL which is used to adjust the frequency of the external crystal. OSCÐIN, OSCÐOUT 20, 19 I Oscillator Input and Output: The terminals for the crystal oscillator which require connection of the crystal tank circuit, varactors, and capacitors. RXC a , RXCb 3, 2 O Receive Clock: Differential 100K ECL receive clock outputs which operate at 125 MHz synchronized to the selected inputs (NRZI DATA g or LBD g ) when valid line state data is present. When valid line state data is not present these outputs continue to operate at a nominal frequency of 125 MHz g 12 kHz. These outputs should be terminated externally with a conventional ECL 50X equivalent load. RXD a , RXDb 27, 26 O Receive Data: Differential 100K ECL received data outputs which provide a resynchronized equivalent of the selected NRZI DATA or LBD inputs. The received data output transitions occur concurrent with the falling edge of the RXC g output. These outputs should be terminated externally with a conventional ECL 50X equivalent load. VCO FLTR 13 O VCO Filter: Low pass filter associated with the first PLL. A three element filter should be connected to this pin which consists of one capacitor in parallel with a resistor and another capacitor to ground. SD a , SDb 18, 17 I Signal Detect: Differential inputs to a 100K ECL to TTL translator intended for conversion of the fiber optic receiver’s ECL signal detect to TTL for a player device. The inputs are used in the test modes as inputs for single stepping and gating the VCO. TTLSD 5 O TTL Signal Detect: Intended to be a signal detect output in TTL format for use by the PLAYER chip. TEST EN 10 I Test Enable: CMOS input which enables the test functions. This input must be at a logic low level in normal operation. DVCC 16 Digital VCC: Positive power supply for most of the internal logic circuitry intended for a 5V operation g 5% relative to ground. Bypass capacitors should be placed as close as possible across the DVCC and DGND pins. DVCC, AVCC and EXTVCC should be tied together through chokes. 6 3.0 Pin Descriptions (Continued) Symbol Pin No. I/O Description EXTVCC 28 External VCC: Positive power supply for all the input and output buffers intended for a 5V operation g 10% relative to ground. Bypass capacitors should be placed as close as possible across the EXTVCC and EXTGND pins. DVCC, AVCC and EXTVCC should be tied together at the device pins through chokes. DGND 15 Digital Ground: Power supply return for the internal circuitry. DGND, AGND and EXT GND pins should be tied together. EXTGND 1 External Ground: Power supply return for the input and output buffers. DGND, AGND and EXT GND pins should be tied together. AVCC 11 Analog VCC: Positive power supply for the critical analog circuitry intended for a 5V operation g 5% relative to ground. Bypass capacitors should be placed as close as possible across the AVCC and AGND pins. DVCC, EXTVCC and AVCC should be tied together through chokes. AGND 14 Analog Ground: Power supply return for the critical analog circuitry. DGND, EXTGND and AGND pins should be tied together. VCO BIAS 12 I VCO Bias: TTL compatible input that sets the nominal frequency for the VCO by the selection of the resistor value between this input and AVCC. A 30 kX value for this resistor will provide nominally 125 MHz on the RXC outputs. 4.0 Electrical Characteristics ECL Signals Output Current 4.1 ABSOLUTE MAXIMUM RATINGS If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. b 65§ C to a 150§ C Storage Temperature TTL Signals Inputs Outputs b 20 mA Supplies EXTVCC to EXTGND DVCC to DGND AVCC to AGND ESD Susceptibility 5.5V 5.5V b 0.5V to a 7V b 0.5V to a 7V b 0.5V to a 7V 2000V 4.2 RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Typ Max Units 4.75 5 5.25 V VCC to GND Power Supply VIH High Level Input Voltage TTL 2.0 ECL VCC b 1.165 VCC b 0.880 Low Level Input Voltage TTL VCC b 1.810 VCC b 1.475 IOH High Level Output Current TTL Outputs (Note 1) b 0.4 mA IOL Low Level Output Current TTL Outputs (Note 1) 4.0 mA FVCO VCO Frequency FXTL Crystal Frequency TA Operating Temperature VIL ECL V 0.8 0 Note 1: TTL outputs include CLK DET and TTLSD. ECL outputs include RXC g and RXD g . 7 V 250 MHz 10.416667 MHz 25 70 §C 4.0 Electrical Characteristics (Continued) 4.3 DC ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions VIC Input Clamp Voltage IIN e 18 mA VOH High Level Output Voltage TTL Outputs: IOH e b400 mA VOL Low Level Output Voltage Min ECL Outputs: 50X Load to VCC b 2V VCC b 2 Max High Level Input Current TTL Inputs: VIN e 7V IIH High Level Input Current TTL Inputs: VIN e 2.7V IIL Low Level Input Current TTL Inputs: VIN e 0.4V Ifilter Charge Pump Current VCC b 1025 Source TRI-STATEÉ V VCC b 880 mV 0.5 V VCC b 1620 mV 100 mA b 20 20 mA b 20 20 mA b 0.3 b 0.7 mA 0.3 0.7 mA VCC b 1810 Sink Units V TTL Outputs: IOL e 4 mA ECL Outputs: 50X Load to VCC b 2V II ICC Max b 1.5 b 500 Supply Current 500 nA 180* mA *Includes 60 mA due to external ECL termination of two differential signals. For 100k ECL output buffers, output levels are specified as: VOHÐmax e VCC b 0.88V VOLÐmax e VCC b 1.62V Since the outputs are differential, the average output level is VCC b 1.25V. The test load per output is 50X at VCC b 2V. The external load current through this 50X resistor is thus: IÐload e [(VCC b 1.25) b (VCC b 2)]/50A e 0.015A e 15 mA There are 2 pairs of differential ECL signals, so the total ECL current is 60 mA. 4.4 AC ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions T1 Phase Difference T2 RXC Pos. Pulse Width (Note 1) T3 CLK DET Time CRD EN Neg. Pulse Width e 1 ms (Valid DATA g Present) T4 Valid Data Time CRD EN e High Note 1: These parameters are not tested, but are assured by correlation with characterization data. 8 Min Max Units b2 2 ns 3 5 ns 100 ms 100 ms 4.0 Electrical Characteristics (Continued) TYPICAL WAVEFORMS TL/F/10384 – 5 FIGURE 4-1. DP83231 Timing Waveforms TL/F/10384 – 6 FIGURE 4-2. Typical Waveforms 9 4.0 Electrical Characteristics (Continued) TL/F/10384 – 7 FIGURE 4-3. Synchronization Window TL/F/10384 – 8 All component values g 5%. FIGURE 4-4. General Wiring Diagram 10 5.0 Detailed Information Key Specifications: 5.1 SPECIAL EXTERNAL COMPONENTS Capacitance: Crystals @ # Manufacturer: Nel Frequency Controls (414) 763-3591 Vr e 1V: C l 85 pF Vr e 4V: 15 pF k C k 30 pF 5.2 LAYOUT RECOMMENDATIONS PartÝ: C5400N # Manufacturer: Standard Crystal Corporation (818) 443-2121 PartÝ: 800R-A-10.41667-32 # The part should be bypassed between the EXTVCC and EXTGND as close to the chip as possible (preferably under the chip using chip caps). The part should also be bypassed between the DVCC and DGND and the AVCC and AGND as close to the chip as possible. Key Specifications: Center Frequency: 10.41667 MHz Load Capacitance, CL: 32 pF Frequency Calibration: g 20 PPM Frequency Stability g 20 PPM (0§ C –70§ C): k g 10 PPM Aging: Pullability: either a motional capacitance of t 0.021 or a change of at least 100 PPM when the CL is changed from 32 pF to 18 pF and a change of b100 PPM when the CL is changed from 32 pF to 50 pF. # No TTL logic lines should pass through the crystal OSC FLTRs or VCO FLTR circuitry areas to avoid the possibility of noise due to crosstalk. # The crystal, OSC FLTRs and the VCO FLTR circuitries should be connected to Ground on isolated branches off of the DGND pin. If using a multilayered board with dedicated VCC and Ground planes ensure that for the ground plane that the ceramic resonator, OSC FLTRs and the VCO FLTR circuitries have their own small isolated islands that are connected to the DGND and AGND pins as described above. # The DVCC and AVCC pins should be connected to VCC on an isolated branches off of the EXTVCC pin, preferably being connected through a ferrite bead or a small inductor. # The DGND and AGND pins should be connected to GND on an isolated branches off of the EXTGND pin. Connection to the ground plane should be made only at the EXTGND pin. Varactors # Manufacturer: Alpha Industries (617) 935-5150 PartÝ: @ DKV6510-71 TL/F/10384 – 10 This drawing was done with convenience in mind. FIGURE 5-1. Recommended Layout 11 5.0 Detailed Information (Continued) 5.3 INPUT AND OUTPUT SCHEMATICS DATA g , LBD g SD g TL/F/10384 – 12 TL/F/10384–11 DIF AMP OSC FLTR TL/F/10384–13 TL/F/10384 – 14 VCO FLTR OSCIN, OSCOUT TL/F/10384–15 TL/F/10384 – 16 12 5.0 Detailed Information (Continued) 5.3 INPUT AND OUTPUT SCHEMATICS (Continued) TEST EN CRD EN, ELB TL/F/10384 – 17 TL/F/10384 – 18 RXC g , RXD g CLK DET, TTLSD TL/F/10384 – 19 TL/F/10384 – 20 Typical ESD Structure TL/F/10384 – 21 13 5.0 Detailed Information (Continued) from the nominal value dependent on temperature and data rate frequency error. If this pin is oscillating then the OSC FLTR pins are unstable and the filters should be examined for possible PC board shorts, opens or instability. If the DIF AMP pin is near ground then check to see if the ELB input is selecting the correct data input. If the DIF AMP pin continues to be near ground or VCC, then the accuracy of the 62.5 MHz source should be examined to verify it is within the g 3 KHz (50 PPM) FDDI system data rate specification. 5.4 DEBUG PROCEDURE Evaluation of the DP83231 should begin by tying the CRD EN and TEST EN pins low and confirming that the SD g pins are above 2V. This will disable the differential phase comparator allowing the crystal resonator to run at its center frequency and will keep the part out of a test mode. The first PLL (see Figure 5-2 ) should be evaluated. The variable capacitor in the crystal resonator circuitry should be tuned so that the crystal resonator oscillates at 10.41666 MHz. If the oscillator circuit fails to oscillate the voltage levels of the OSC IN and OSC OUT pins should be examined. The DC voltage on these pins should be equal to approximately VCC d 2 (with or without the crystal present). The capacitors which form the oscillator tank circuit should be returned to the isolated ground branch in close proximity. After checking the crystal frequency, examine the RXC g output and verify that this frequency is twelve times the crystal frequency. If this is not true then the VCO FLTR output should be examined for possible PC board shorts, opens or filter instability. The VCO FLTR pin should be stable at approximately a 1.5V DC level in operation. If the VCO FLTR pin is oscillating then the loop filter components for this pin were either chosen inappropriately or were placed in the incorrect position. Once it is known that the first PLL is working, force CRD EN high and input a constant 62.5 MHz g 50 ppm (1T pattern) data stream to the DATA g inputs (see Figure 5-3 ). To see how well the second loop is working examine the DIF AMP pin. If the incoming data rate is exactly 62.5 MHz and the crystal resonator was accurately adjusted as described above, then the DIF AMP pin voltage should be stable at approximately 2.25V. The voltage at this pin will vary TL/F/10384 – 22 FIGURE 5-2. 1st PLL TL/F/10384 – 23 FIGURE 5-3. 2nd PLL 14 5.0 Detailed Information (Continued) 5.5 AC TEST CIRCUITS TL/F/10384 – 25 FIGURE 5-5. Switching Test Circuit for All ECL Input and Output Signals TL/F/10384 – 24 FIGURE 5-4. Switching Test Circuit for All TTL Output Signals 15 DP83231 CRD Device (FDDI Clock Recovery Device) Physical Dimensions inches (millimeters) Plastic Leaded Chip Carrier (V) Order Number DP83231AV NS Package Number V28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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