FINAL Am79865/Am79866A Physical Data Transmitter/Physical Data Receiver DISTINCTIVE CHARACTERISTICS ■ Fully compliant with ANSI X3T9.5 FDDI, TP-FDDI, and 100BASE-TX/FX PHY standards ■ The on-chip Phase-Locked-Loop (PLL) only requires an external frequency reference ■ Provides data and clock recovery functions for FDDI and Fast Ethernet applications ■ 125 MBaud (100 Mbps) serial link data rate ■ Parallel input to the PDT is a 5-bit encoded NRZ symbol clocked by LSCLK ■ Parallel output from the PDR is a 5-bit unframed NRZ symbol clocked by RSCLK ■ Dedicated pins provide electrical loopback data path ■ 20-pin Plastic Leaded Chip Carrier (PLCC) ■ Single +5 V power supply operation ■ Interfaces to fiber or copper media GENERAL DESCRIPTION The Physical Data Transmitter (Am79865) and the Physical Data Receiver (Am79866) devices provide clock recovery/generation functions meeting the requirements of FDDI, TP-FDDI, and 100BASE-TX PHY standards. The PDT and PDR devices are part of the SUPERNET 2 FDDI Physical Layer Protocol chip set which also includes the Physical Layer Controller with Scrambler (PLC-S). The PLC-S (Am79C864A), PDT and PDR devices are collectively known as the AmPHY. The PLC-S performs the FDDI physical layer functions which includes, among others, the 4B5B encoding and decoding. The PDT converts encoded symbols into a serial NRZI data stream. The on-chip PLL generates a bit rate clock from the LSCLK reference. The PDR uses a built-in clock recovery PLL to extract clock information from the received data stream. The recovered clock is used for serial-to-parallel data conversion. Publication# 15451 Rev: D Amendment/0 Issue Date: June 1996 BLOCK DIAGRAM Am79865 PDT LPBCK TDAT 4-0 Input Register Output Control NRZ Shifter Test Mode Sync Logic LSCLK LTX, LTY NRZI ÷5 Clock Multiplier (PLL) Output Control TEST FOTOFF TX, TY 15451D-1 Am79866A PDR RDAT 4-0 RSCLK Output Register Shifter NRZ NRZI Clock Recovery PLL ÷5 TEST LSCLK SDO Q D Media Interface LSCLK SDI LRX, LRY 2 RX, RY Am79865/Am79866A 15451D-2 CONNECTION DIAGRAMS Top View RDAT2 GND1 16 15 14 8 LTX VCC1 GND1 NC VCC1 RDAT3 RDAT4 GND2 4 5 6 TEST 7 LPBCK 8 TY TX RSCLK Am79866A 16 15 PDR VCC2 SDO LSCLK 14 GND1 9 10 11 12 13 9 10 11 12 13 NC 18 17 LRY LRX RY 7 Am79865 PDT TEST VCC2 LSCLK 18 17 FOTOFF TDAT0 4 5 6 15451D-3 Am79865/Am79866A RX SDI TDAT4 TDAT2 TDAT3 LPBCK LTY 3 2 1 20 19 3 2 1 20 19 GND2 TDAT1 RDAT1 VCC1 RDAT0 20-Pin PLCC 20-Pin PLCC 15451D-4 3 LOGIC SYMBOLS Am79C864A PLC-S Interface Parallel Data Symbol TDAT 4–0 25 MHz Local Symbol Clock Test Mode Select Forcing Optical Transmitter Off Loopback Control FOTOFF LPBCK LTX, LTY Am79865 PDT LSCLK TEST Data Loopback to Local PDR TX, TY Serial Data Transmitted in NRZI Format Note: Three VCC pins and two GND pins. Fiber or Copper Interface 15451D-5 Am79C864A PLC-S Interface Parallel Data Symbol RDAT 4–0 25 MHz Local Symbol Clock Test Mode Select Note: Two VCC pins and three GND pins. 4 LSCLK TEST Recovered Light Symbol Level Clock Signal RSCLK Loopback Control SDO Am79866A PDR LPBCK LRX, LRY RX, RY SDI Serial Data Received in NRZI Format Light Level Signal Fiber or Copper Interface Am79865/Am79866A Data Loopback from Local PDT 15451D-6 ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. AM79865/ AM79866A J C TEMPERATURE RANGE C = Commercial (0°C to +70°C) PACKAGE TYPE J = 20-Pin Plastic Leaded Chip Carrier (PL 020) SPEED OPTION Not Applicable DEVICE NUMBER/DESCRIPTION Am79865 = Physical Data Transmitter Am79866A = Physical Data Receiver Valid Combinations AM79865 JC AM79866A Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am79865/Am79866A 5 Am79865 PDT PIN DESCRIPTION TDAT 4–0 TX, TY** Transmit Data (TTL Inputs) Transmit Data (PECL Differential Outputs) These five inputs accept data symbols from the Am79C864 PLC, latched by the rising edge of LSCLK. These transmit outputs carry differential NRZI data. They can be forced to logical 0 (TX LOW, TY HIGH) by asserting the FOTOFF input. LSCLK Local Symbol Clock (TTL Input) LTX, LTY** This pin supplies the frequency and phase reference to the internal PLL clock multiplier. It should be driven by an external 25 MHz crystal-controlled clock source. Loopback Outputs) FOTOFF Fiber Optic Transmitter Off (TTL Input, active LOW) When held LOW, the TX output is forced LOW and TY output is forced HIGH so that the Fiber Optic Transmitter will output logical 0. In test mode, FOTOFF is used as the test clock input and does not control TX/TY. LPBCK Loopback Control (TTL Input, active LOW) When asserted, the LTX/LTY outputs transmit the NRZI serial bit stream to the PDR to establish the loopback data path. When deasserted, the LTX output is forced LOW and LTY output is forced HIGH. TEST Test Mode Enable (TTL Input) When asserted, the PDT is in Test mode. For normal operation, TEST pin must be tied LOW. Transmit Data (PECL Differential These differential outputs carry the same signal as TX/ TY when the LPBCK input is asserted (LOW). LTX/LTY should be connected to the LRX/LRY pins of Am79866A PDR to perform loopback function. When LPBCK is deasserted (HIGH), LTX is forced LOW and LTY is forced HIGH. **All differential PECL outputs carry data at ECL voltage levels referenced to +5.0 V (PECL levels). The external terminations required are shown in the Interface Connection Diagram in the Appendix. VCC1, VCC2 Power Supply VCC1,VCC2 are +5.0 V nominal power supply pins. VCC1 powers all TTL and ECL I/O circuits. VCC2 powers all internal logic gates and analog circuits. They must be connected to a common external supply. GND1, GND2 Ground Pins GND1 is TTL and ECL I/O ground. GND2 is the internal logic and analog ground. They must be connected to a common external ground reference. 6 Am79865/Am79866A Am79866A PDR PIN DESCRIPTION LSCLK SDO Local Symbol Clock (TTL Input) Signal Detect Output (TTL Output) LSCLK is driven by an external frequency source at the 25 MHz symbol rate. This signal is used as a frequency reference for the PDR clock-recovery PLL. SDO is the SDI input synchronized by LSCLK. It has the same logical sense as SDI, i.e., HIGH indicates the received optical signal is above the detection threshold. LPBCK RX, RY* Loopback (TTL Input, active LOW) Received Data (PECL Differential Line Receiver Inputs) When active, LPBCK selects the serial data stream at LRX/LRY inputs as the received data. When HIGH, RX/ RY are selected. This function is used during system loopback test to bypass the transmission medium. TEST TEST Mode Enable (TTL Input) When asserted, the PDR is in Test mode. For normal operation, TEST pin must be tied LOW. RDAT 4–0 Received Data (TTL Outputs) These 5-bit parallel outputs are clocked by the falling edge of RSCLK and carry the NRZ data symbols to the PLC. RSCLK Recovered Symbol Clock (TTL Output) RSCLK is derived from the clock synchronization PLL circuit. It is synchronous to the received serial data, and is the recovered bit clock divided-by-five. This is a 25 MHz clock. SDI Signal Detect Input (PECL Single-Ended Input) SDI typically comes from the fiber optic receiver to indicate that the received optical signal is above the detection threshold. When asserted (HIGH), the data on RX/ RY are used for the input to the PDR. When deasserted (LOW), the RX/RY data stream is gated off and the PLL locks onto the LSCLK. These pins receive NRZI data. LRX, LRY* Loopback Received Data (PECL Differential Line Receiver Inputs) This input pair should be connected to the PDT LTX/ LTY outputs through properly terminated lines to establish the loopback data path. When LPBCK is asserted, LRX/LRY carry the data to be used as the input to the PDR. In Test mode, LRX/LRY become the test clock input. *RX/RY and LRX/LRY are differential line receivers which have high input sensitivity and wide common-mode range. They can also accept PECL voltage swings and shall be driven by properly terminated transmission lines. VCC1, VCC2 Power Supply VCC1,VCC2 are +5.0 V nominal power supply pins. VCC1 powers all TTL and ECL I/O circuits. VCC2 powers all internal logic gates and analog circuits. They must be connected to a common external supply. GND1, GND2 Ground Pins GND1 is TTL and ECL I/O ground. GND2 is the internal logic and analog ground. They must be connected to a common external ground reference. Am79865/Am79866A 7 FUNCTIONAL DESCRIPTION Normal Operation Mode The Am79865 PDT accepts encoded data symbols at TDAT 4–0 pins. The 5-bit symbol is latched into the PDT by the rising edge of LSCLK, serialized, converted to NRZI format and shifted to the outputs (TDAT4 bit is transmitted first). There are two pairs of serial data outputs capable of driving either Fiber Optic Interface hardware or wire transmission lines without external buffering. The TX/TY pair is connected to the serial link and the LTX/LTY pair is used in the loopback connection to the Am79866A PDR. The PDT uses LSCLK as the frequency reference to generate the serial link data rate. The external clock source must be crystal controlled and continuous. All of the internal logic of PDT runs on an internal clock that is PLL-multiplied from the external reference source. The PDT’s internal PLL is referenced to the rising edges of LSCLK only. The input clock frequency required to achieve 125 MBaud on the serial link is 25 MHz at LSCLK. In order to generate the serial output waveforms conforming to the FDDI specification, the external reference clock (LSCLK) must meet FDDI frequency and stability requirements. The PDT serial output typically contains less than 0.4 ns peak-to-peak jitter at 125 MBaud. The latency from the LSCLK to the serial output is typically 4 to 6 bits (8 ns/bit). The Am79866A PDR accepts encoded NRZI serial data on the RX/RY inputs and converts them to NRZ format. It then latches the unframed symbol (5 bits) to the RDAT 4-0 outputs on the falling edge of RSCLK. T h e h e a rt o f t h e A m 7 9 8 6 6 A P D R c h i p i s i t s clock-recovery PLL which extracts encoded clock information from the serial NRZI data stream and recovers the data. The PLL examines every data transition in the 8 received serial stream and aligns its internal bit clock with these data transitions. In order to guarantee the correct operation of the PLL, the encoding scheme (such as the FDDI 4B5B code) must insure adequate transition density of the encoded data stream. The PDR has input jitter tolerance characteristics that meet or exceed the recommendations of Physical Layer Medium Dependent (PMD) FDDI document. Typically, at 125 MBaud (8 ns/bit), the peak-to-peak Duty-Cycle Distortion (DCD) tolerance is 1.4 ns, the peak-to-peak Data-Dependent Jitter (DDJ) tolerance is 2.2 ns, and the peak-to-peak Random Jitter (RJ) tolerance is 2.27 ns. The total combined peak-to-peak jitter tolerance is typically 5 ns with bit error rate (BER) less than 2.5 x 10–10. The PDR’s PLL typically has an acquisition time of 100 µs or less when ‘Master’ symbols (one data transition within ten bits) are received. The acquisition time reduces with increasing transition density in the data stream. The SDI input qualifies the data at RX/RY. When SDI is LOW, the PDR uses LSCLK as the PLL input and forces LOW at the Output Register. The LPBCK input selects the data source between RX/RY and LRX/LRY. When LPBCK is LOW, the SDI input is ignored. When SDI is HIGH and the RX/RY input stream contains no data transition for PLL input, the PLL operating frequency range is limited by the LSCLK reference. The observed RSCLK output frequency is generally within 0.5% of the LSCLK frequency. Under normal conditions, the frequency of LSCLK multiplied by five must be within 0.25% of the expected received data for the PLL to operate correctly. (Note, FDDI specifies the two frequencies to be within 50 ppm or 0.005% of each other.) Am79865/Am79866A Am79865 PDT Functional Block Description accept the encoded NRZI serial data. LRX/LRY are also differential line receiver inputs which accept the loopback data stream from the local PDT LTX/LTY outputs. Clock Multiplier LSCLK supplies the reference frequency which is multiplied by five using an on-chip PLL. The transmission rate and all serialization logic are controlled by the internally generated bit clock. Input Register TDAT 4–0 are clocked into the Input Register by the rising edge of LSCLK. Shifter Parallel data are loaded from the Input Register into the Shifter at the internally generated symbol boundary, and serially shifted at the bit clock rate. NRZ-to-NRZI Converter The NRZ output of the Shifter is converted into NRZI data patterns for transmission. Output Control The differential outputs carry the encoded serial NRZI bit stream. The TX/TY pair can be forced to logical 0 (TX LOW, TY HIGH) by asserting FOTOFF input. The LTX/LTY pair can be forced to logical 0 (LTX LOW, LTY HIGH) by deasserting the LPBCK input. Am79866A PDR Functional Block Description Clock-Recovery PLL The clock-recovery PLL separates the input data stream into clock and data patterns. The PLL operating frequency is established by the reference at LSCLK. The PLL is capable of tracking data correctly within + 0.25% of LSCLK (exceeds the frequency range defined by the FDDI specification). Media Interface NRZI-TO-NRZ Converter Serial data are retimed and associated jitter is removed. Retimed data are converted into NRZ format prior to the Shifter input. Shifter The Shifter is serially loaded from the NRZI_TO_NRZ converter, using the recovered bit clock. Output Register The Output Register is clocked by RSCLK falling edges. RSCLK is the recovered bit clock divided-by-five and is synchronous to the received serial data. Test Mode Asserting PDT TEST input pin forces PDT into its test mode. This allows testing of the internal logic without the PLL clock multiplier. The internal clock source is replaced by the test clock provided at the FOTOFF input. An automatic test system can clock the PDT through functional test patterns at any rate, typically less than 25 MHz, or any sequence to facilitate logic verification. In PDT test mode, LSCLK strobes data into the Input Register and provides initialization to the internal counter. The PDR test mode allows testing of the internal logic without the PLL. When TEST is HIGH, the internal clock source is replaced by the test clock provided at the LRX/LRY inputs. Note: The loopback data path in the Am79866A PDR cannot be tested in test mode. An automatic test system can clock the PDR through functional test patterns at any rate, typically less than 25 MHz, or any sequence to facilitate logic verification. The RX/RY inputs are typically driven by differential PECL voltages, referenced to +5 V. These inputs Am79865/Am79866A 9 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature Under Bias . . . . . . 0°C to 70°C Ambient Temperature (TA). . . . . . . . . . . . .0°C to 70°C Supply Voltage (VCC) . . . . . . . . . . +4.75 V to +5.25 V Supply Voltage (VCC) to Ground Potential Continuous . . . . . . . –0.5 V to +7.0 V DC Voltage Applied to Outputs. . . . . .–0.5 to VCC Max Operating ranges define those limits between which the functionality of the device is guaranteed. DC Input Voltage . . . . . . . . . . . . . . . . –0.5 V to +5.5 V DC Output Current . . . . . . . . . . . . . . . . . . . . . . .±100 mA DC Input Current . . . . . . . . . . . . . –30 mA to +5.0 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Am79865 PDT Parameter Symbol Parameter Description Test Description Min Max TTL Inputs: TDAT 4–0, LSCLK, FOTOFF, LPBCK, TEST VIH Input HIGH Voltage VCC = Max (Note 2) 2.0 V VIL Input LOW Voltage VCC = Max (Note 2) 0.8 V VI Input Clamp Voltage VCC = Min, IIN = –18 mA –1.5 V IIH Input HIGH Current VCC = Max, VIN = 2.7 V 50 µA IIL Input LOW Current VCC = Max, VIN = 0.4 V –400 µA II Input Leakage Current VCC = Max, VIN = 5.5 V 50 µA PECL Outputs: TX, TX; LTX, LTY VOH Input HIGH Voltage PECL Load (Note 3) VCC – 1.025 V VCC – 0.88 V VOL Input LOW Voltage PECL Load (Note 3) VCC – 1.81 V 0.8VCC – 1.62 V Power Supplies 10 ICC1 VCC1 Supply Current VCC1 = VCC2 = Max (Note 4) 20 ICC2 VCC2 Supply Current VCC1 = VCC2 = Max 65 Am79865/Am79866A DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Am79866 PDT Parameter Symbol Parameter Description Test Description Min Max TTL Inputs: LSCLK, LPBCK, TEST VIH Input HIGH Voltage VCC = Max (Note 2) VIL Input LOW Voltage VCC = Max (Note 2) 0.8 V VI Input Clamp Voltage VCC = Min, IIN = –18 mA –1.5 V IIH Input HIGH Current VCC = Max, VIN = 2.7 V 50 µA IIL Input LOW Current VCC = Max, VIN = 0.4 V –400 µA II Input Leakage Current VCC = Max, VIN = 5.5 V 50 µA 2.0 V TTL Outputs: RDAT 4–0, SDO, RSCLK VOH Output HIGH Voltage VCC = Min, IOH = –1 mA 2.4 V VOL Output LOW Voltage VCC = Min, IOL = 4 mA ISC Output Short Circuit Current VCC = Max (Note 5) –15 mA V –85 mA 0.45 V Differential PECL Inputs: RX, RY; LRX, LRY VIN Input Voltage (Absolute High or Low) VCC = Max (Note 2) 2.5 V VCC Vdif Input Differential Voltage VCC = Max (Note 2, 6) 50 mV 1.1 V IIH Input HIGH Current VCC = Max, VIN = VCC – 0.88 V IIL Input LOW Current VCC = Max, VIN = VCC – 1.81 V 220 µA 0.5 µA Single-Ended PECL Input: SDI VIHS Input Single-Ended HIGH Voltage VCC = Max (Note 2, 7) VCC – 1.165 V VCC – 0.88 V VILS Input Single-Ended LOW Voltage VCC = Max (Note 2, 7) VCC – 1.81 V VCC – 1.475 V IIH Input HIGH Current VCC = Max, VIN = VCC – 0.88 V IIL Input LOW Current VCC = Max, VIN = VCC – 1.81 V 220 µA 0.5 µA Power Supplies ICC1 VCC1 Supply Current VCC1 = VCC2 = Max 25 ICC2 VCC2 Supply Current VCC1 = VCC2 = Max 145 Am79865/Am79866A 11 SWITCHING CHARACTERISTICS over operating range unless otherwise specified Am79865 PDT No. Parameter Symbol 1 tP 2 Parameter Description Test Conditions (Note 8) Min Max Unit LSCLK Period 40 40 ns tPW LSCLK Pulse Width HIGH 15 ns 3 tPW LSCLK Pulse Width LOW 15 ns 4 tS TDAT 4–0 to LSCLK Rise Setup Time 12 ns 5 tH TDAT 4–0 to LSCLK Rise Hold Time 2.5 ns 6 tR† TX, TY, LTX, LTY Rise Time PECL load 0.3 3 ns 7 tF† TX, TY, LTX, LTY Hold Time PECL load 0.3 3 ns 8 tSK† TX/TY, LTX/LTY Skew PECL load ±200 ps Max Unit ±0.25 % Am79866A PDR No. Parameter Symbol 21 fOS LSCLK to received data frequency offset 22 tPW LSCLK Pulse Width HIGH 15 ns 23 tPW LSCLK Pulse Width LOW 16 ns 24 tPW RSCLK Pulse Width HIGH TTL load (Note 10) 10 ns 25 tPW RSCLK Pulse Width LOW TTL load (Note 10) 20 ns 26 tPD RDAT4–0 Valid to RSCLK Rise TTL load (Note 11) 13 ns 27 tPD RSCLK Rise to RDAT4–0 Invalid TTL load (Note 11) 10 ns 28 tS SDI to LSCLK Rise Setup Time 5 ns 29 tH SDI to LSCLK Rise Hold Time 7 ns 30 tPD LSCLK Rise to SDO Delay Parameter Description Test Conditions (Note 8) Min (Note 9) TTL load 30 ns Notes: 1. For conditions shown as Min or Max, use the appropriate values specified under operating range. 2. Typically measured with device in Test mode while monitoring output logic states. 3. Tested for VCC = Min, shown limits are specified over entire VCC operating range. 4. PDT ICC1 is tested with all PECL outputs terminated to VCC (unloaded). The PECL outputs contribute 25 mA/pair nominally to ICC1 when they are loaded with PECL loads, 50 Ω to (VCC – 2). In calculating the chip power dissipation, the contribution by the output loads shall be multiplied by 1 V instead of by VCC. 5. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second. † 12 Not included in the production test. Am79865/Am79866A Notes (continued): 6. Vdif is tested with each input voltage within the VIN range. 7. Device thresholds on the SDI pin are verified during production test by ensuring that the input threshold is less than VIHS (min) and greater than VILS (Max). The figure below shows the acceptable range (shaded area) for the transition voltage. V (max) VCC – 0.88 V (min) VCC – 1.165 V VIHS input threshold transition voltage VCC – 1.475 V (max) VILS (min) VCC – 1.81 V 8. All timing references are made with respect to + 1.5 V for TTL-level signals or to the 50% point between VOH and VOL for PECL signals. PECL input rise and fall times must be 2 ns + 0.2 ns between 20% and 80% points. TTL input rise and fall times must be 2 ns between 1 V and 2 V. 9. Received data frequency is determined by serial data inputs. Multiply LSCLK frequency by 5 to convert the receive data bit rate. 10. Tested for 125 MBaud received data rate (1 bit-time is 8 ns). tPW (HIGH) is functionally 2 bit-time wide. tPW (LOW) is functionally 3 bit-time wide. 11. Tested for 125 MBaud received data rate (1 bit-time 8 ns). Am79865/Am79866A 13 SWITCHING WAVEFORMS Am79865 PDT 1 LSCLK 3 2 4 5 Symbol k Valid TDAT 4–0 Symbol k+1 Latency TX, TY LTX, LTY Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Symbol k Bit 4 corresponds to TDAT4 VOH 6 TX, TY LTX, LTY 7 80% 20% VOL TX 50% 8 TY 50% 15451D-7 Am79866A PDR RSCLK 24 25 27 RDAT 4–0 LSCLK 24 26 Parallel 5-Bit Symbol Valid 22 27 Parallel 5-Bit Symbol Valid Parallel 5-Bit Symbol Valid 23 28 29 SDI (PECL) 30 SDO 15451D-8 14 Am79865/Am79866A KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State KS000010-PAL SWITCHING TEST CIRCUITS VCC R1 VOUT VOUT 3 pF 50 Ω 30 pF 2.4 K VCC – 2 V TTL Output Load 15451D-9 PECL Output Load 15451D-10 Notes: 1. CL = 30 pF includes scope probe, wiring and stray capacitances without device in text fixture. Notes: 1. R1 = 1 KΩ for the IOL = 4 mA 2. All diodes IN916 or IN3064, or equivalent. 3. CL = 30 pF includes scope probe, wiring and stray capacitances without device in text fixture. 4. AMD uses constant current (A.T.E.) load configurations and forcing functions. This figure is for reference only. 2. AMD uses Automatic Test Equipment (A.T.E.) load configurations and forcing functions. This figure is for reference only. Am79865/Am79866A 15 SWITCHING TEST WAVEFORMS 3.0 V VCC – 0.9 V 80% 2.0 V 1.5 V 1.0 V 50% 20% VCC – 1.7 V 0.0V 2 ± 0.2 ns 2 ± 0.2 ns 2 ± 0.2 ns 2 ± 0.2 ns 15451D-11 15451D-10 TTL Input Waveform 16 ECL Input Waveform Am79865/Am79866A PHYSICAL DIMENSIONS Am79865/Am79866A Physical Data Transmitter/Data Receiver PL 020 20-Pin Plastic Leaded Chip Carrier (measured in inches) .385 .395 .042 .056 .350 .356 .062 .083 Pin 1 I.D. .385 .395 .350 .356 .200 .290 REF .330 .013 .021 .026 .032 .009 .015 .050 REF TOP VIEW .090 .120 .165 .180 SEATING PLANE SIDE VIEW 16-038-SQ PL 020 DF79 2-20-96 lv Trademarks Copyright © 1996 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Am79865/Am79866A 17