REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Added changes in accordance with NOR 5962-R116-94. 94-03-03 M. A. Frye B Added 03 device, removed CAGE number 01295, and made editorial changes throughout. 96-07-09 M. A. Frye C Added changes in accordance with NOR 5962-R059-97. 96-11-12 Raymond Monnin D Added changes in accordance with NOR 5962-R193-97. 97-03-03 Raymond Monnin E Corrected radiation circuit. Updated boilerplate. ksr 98-03-31 Raymond Monnin F Add 04 and 05 devices, change case outlines from CQCC2-F172 to figure 4. Page 3, section 1.3 changed TJ from 175°C to 150°C. Added appendix A for die. Added CQFP package option case U, and binning circuitry delay for 04 and 05 in Table IA. ksr 98-09-18 Raymond Monnin G Change the generic number for the 01 and 02 devices as well as the bin speed. Update the binning circuit delay on table IA. Update the bin speed for the 01 device in section 10.2.2. ksr 98-11-15 Raymond Monnin H Replaced figure 1, case outline Y with new graphic art work. ksr 00-04-28 Raymond Monnin REV SHEET REV H H H H H H H H H H H H H H H H H H H H SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV H H H H H H H H H H H H H H SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 REV STATUS OF SHEETS PMIC N/A STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A PREPARED BY Rajesh Pithadia DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 http://www.dscc.dla.mil CHECKED BY Jeff Bowling APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS, FIELD PROGRAMMABLE GATE ARRAY, 8000 GATES, MONOLITHIC SILICON DRAWING APPROVAL DATE 93-04-07 SIZE REVISION LEVEL A CAGE CODE 67268 5962-92156 H SHEET 1 DSCC FORM 2233 APR 97 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. OF 33 5962-E231-00 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 H 01 92156 Federal stock class designator RHA designator (see 1.2.1) \ V X X Device class designator (see 1.2.3) Case outline (see 1.2.4) Lead finish (see 1.2.5) Device type (see 1.2.2) / \/ Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows: Device type 01 02 03 04 05 Generic number Circuit function 1280A 1280A-1 RH1280 1280XL 1280XL-1 Bin speed 8000 gate field programmable gate array 8000 gate field programmable gate array 8000 gate field programmable gate array 8000 gate field programmable gate array 8000 gate field programmable gate array 200 ns 170 ns 160 ns 120 ns 102 ns 1.2.3 Device class designator. The device class designator shall be a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Outline letter X Y Z U Descriptive designator CMGA7 - P176 See figure 1 CMGA7 - P176 See figure 1 Terminals Package style 176 172 177 172 Pin grid array Quad flat pack Pin grid array with orientation pin Quad flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 2 1.3 Absolute maximum ratings. 1/ DC supply voltage range (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage range (VI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output voltage range (VO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input clamp current (IIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output clamp current (IOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous output current (IO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range (TSTG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . Thermal resistance, junction-to-case (JC) : Case X and Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Case Y and U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum junction temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V dc to +7.0 V dc -0.5 V dc to VCC + 0.5 V dc -0.5 V dc to VCC + 0.5 V dc ±20 mA ±20 mA ±25 mA -65°C to +150°C 300°C See MIL-STD-1835 10°C/W 2/ +150°C 1.4 Recommended operating conditions. Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5 V dc to +5.5 V dc Case operating temperature range (TC) . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Radiation: Total dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300K rads (maximum) 3/ 1.5 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) . . . . . . . . . . . . . . . . . . . . . . 100 percent 4/ 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-973 - Configuration Management. MIL-STD-1835 - Interface Standard For Microcircuit Case Outlines. 1/ 2/ 3/ 4/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. When the thermal resistance for this case is specified in MIL-STD-1835, that value shall supersede the value indicated herein. Device electrical characteristics are guaranteed for post irradiation levels at 25°C, in low dose rate environment (post 168 hours, 100°C, biased anneal). 100 percent test coverage of blank programmable logic devices. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 3 HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcircuit Drawings (SMD's). MIL-HDBK-780 - Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents which are DoD adopted are those listed in the issue of the DODISS cited in the solicitation. Unless otherwise specified, the issues of documents not listed in the DODISS are the issues of the documents cited in the solicitation. AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM Standard F1192M-95 - Standard Guide for the Measurement of Single Event Phenomena from Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publications should be addressed to the American Society for Testing and Materials, 1916 Race Street, Philadelphia, PA 19103.) ELECTRONICS INDUSTRIES ASSOCIATION (EIA) JEDEC Standard EIA/JESD 78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA 22201.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing shall take precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 and figure 1herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table(s). 3.2.3.1 Unprogrammed devices. The truth table or test vectors for unprogrammed devices for contracts involving no altered item drawing is not part of this drawing. When required in screening (see 4.2 herein) or quality conformance inspection group A, B, C, D, or E (see 4.4 herein), the devices shall be programmed by the manufacturer prior to test. A minimum of 50 percent of the total number of logic modules shall be utilized or at least 25 percent of the total logic modules shall be utilized for any altered item drawing pattern. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 4 3.2.3.2 Programmed devices. The truth table or test vectors for programmed devices shall be as specified by an attached altered item drawing. 3.2.4 Switching test circuit and waveforms . The switching test circuit and waveforms diagram shall be as specified on figure 3. 3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change as defined in MIL-STD-973. 3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 42 (see MIL-PRF-38535, appendix A). 3.11 Processing options. Since the device is capable of being programmed by either the manufacturer or the user to result in a wide variety of configurations; two processing options are provided for selection in the contract, using an altered item drawing. 3.11.1 Unprogrammed device delivered to the user. All testing shall be verified through group A testing as defined in 4.4.1 and table IIA. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program configuration. 3.11.2 Manufacturer-programmed device delivered to the user. All testing requirements and quality assurance provisions herein, including the requirements of the altered item drawing, shall be satisfied by the manufacturer prior to delivery. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 5 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additional criteria for device class M. a. Delete the sequence specified as initial (pre-burn-in) electrical parameters through interim (post-burn-in) electrical parameters of method 5004 and substitute lines 1 through 6 of table IIA herein. b. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. For device class M the test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015. (1) Dynamic burn-in for device classes M (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1b herein). c. Interim and final electrical test parameters shall be as specified in table IIA herein. 4.2.2 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table IIA herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MILPRF-38535, appendix B. 4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MILPRF-38535 including groups A, B, C, D, and E inspections and as specified herein except where option 2 of MIL-PRF-38535 permits alternate in-line control testing. Quality conformance inspection for device class M shall be in accordance with MILPRF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4.1 Group A inspection. a. Tests shall be as specified in table IIA herein. b. Subgroups 5 and 6 of table I of method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (CIN and COUT measurements) shall be measured only for initial qualification and after any process or design changes which may affect input or output capacitance. Capacitance shall be measured between the designated terminal and GND at a frequency of 1 MHz. Sample size is five devices with no failures on a minimum of ten worst case pins from each device. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 6 d. O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which may affect the performance of the device. For device class M procedures and circuits shall be maintained under document revision level control by the manufacturer and shall be made available to the preparing activity or acquiring activity upon request. For device classes Q and V, the procedures and circuits shall be under the control of the device manufacturer's technical review board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the preparing activity or acquiring activity upon request. Testing shall be on all pins, on 5 devices with zero failures. Latch-up test shall be considered destructive. Information contained in JEDEC Standard EIA/JESD 78 may be used for reference. e. Programmed device (see 3.2.3.2) - For device class M, subgroups 7, 8A, and 8B tests shall consist of verifying the functionality of the device. For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device. These tests shall have been fault graded in accordance with MIL-STD-883, test method 5012 (see 1.6 herein). f. Unprogrammed devices shall be tested for programmability and dc and ac performance compliance to the requirements of group A, subgroups 1 and 7. (1) A sample shall be selected from each wafer lot to satisfy programmability requirements. Eight devices shall be submitted to programming (see 3.2.3.1). If any device fails to program, the lot shall be rejected. At the manufacturer's option, the sample may be increased to 18 total devices with no more than two total device failures allowable. (2) These eight devices shall also be submitted to the requirements of the specified tests of group A, subgroups 1 and 7. If any device fails, the lot shall be rejected. At the manufacturer's option, the sample may be increased to 18 total devices with no more than two total device failures allowable. (3a) Eight devices from the programmability sample shall be submitted to the requirements of group A, subgroups 9 for binning circuit delay only. If any device fails, the lot shall be rejected. At the manufacturer's option, the sample may be increased to 18 total devices with no more than two total device failures allowable. (3b) If the binning circuit is tested on 100 percent of the products, then the above requirement (3A) is met. 4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein. 4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883: a. Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005. b. TA = +125°C, minimum. c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MILPRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB, in accordance with MIL-PRF-38535, and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883. 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein. 4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). a. End-point electrical parameters shall be as specified in table IIA herein. b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device classes must meet the postirradiation end-point electrical parameter limits as defined in table IA at TA = +25°C ±5°C, after exposure, to the subgroups specified in table IIA herein. c. When specified in the purchase order or contract, a copy of the RHA delta limits shall be supplied. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 7 4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883 method 1019 and as specified herein. 4.4.4.1.1 Accelerated aging test. Accelerated aging tests shall be performed on all devices requiring a RHA level greater than 5k rads(Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and shall be the pre-irradiation end-point electrical parameter limit at 25°C ± 5°C. Testing shall be performed at initial qualification and after any design or process changes which may affect the RHA response of the device. 4.4.4.2 Single event phenomena (SEP). SEP testing shall be required on class V devices. SEP testing shall be performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as approved by the qualifying activity at initial qualification and after any design or process changes which may affect the upset or latchup characteristics. Test four devices with zero failures. ASTM standard F1192 may be used as a guideline when performing SEP testing. The test conditions for SEP are as follows: a. The package lid of the DUT is removed so as to provide an unobstructed path to the die for the ion beam. b. The DUT is biased or exercised as appropriate to that IC being tested. c. The temperature that SEP tests are conducted at is 25°C +/- 10°C (ambient). d. Particle penetration range is > 20 microns (Si). e. The flux used is between 102 and 105 ions/cm2/s. f. The beam incidence angle(s) used are between 0° to 60° from normal. g. Supply current and voltage(s) as well as SEU, SEL and faults are monitored and recorded in-situ. h. For SEP test limits, see Table IB herein. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 8 TABLE IA. Electrical performance characteristics. Test Symbol Group A Subgroups Conditions 1/ 4.5 V < VCC < 5.5 V -55°C < TC < +125°C unless otherwise specified Device type Min High Level output voltage VOH Test one output at a time, VCC = 4.5 V, IOH = -3.2 mA 1, 2, 3 All Low level output voltage VOL Test one output at a time, VCC = 4.5 V, IOL = 4.0 mA 1, 2, 3 All Low level input voltage VIL 1, 2, 3 All High level input voltage VIH 1, 2, 3 V 01,02, 04,05 2.0 VCC +0.3 V 03 2.2 VCC +0.3 All Input leakage current IIL VCC = 5.5 V, VIN = VCC or GND 1, 2, 3 All Output leakage current IOZ VCC = 5.5 V, VO = VCC or GND 1, 2, 3 All I/O terminal capacitance CI/O See 4.4.1c, f= 1.0 Mhz, VOUT = 0 V 4 All FT 2/ See 4.4.1e, VO = 0 V, VCC = 4.5 V 7, 8A, 8B All 9, 10, 11 V 0.8 1, 2, 3 See figure 3, VIL = 0 V, VIH = 3.0 V, VCC = 4.5 V, VOUT = 1.5 V 3/ 3.7 -0.3 Outputs unloaded, VCC = 5.5 V, VIN = VCC or GND tPBLH, tPBHL Max V IDD Binning circuit delay Unit 0.4 Standby supply current Functional tests Limits 25 mA -10 10 A -10 10 A 20 pF 01 200 ns 02 170 03 160 04 120 05 102 See footnotes at end of table. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 9 TABLE IA. Electrical performance characteristics - Continued. 1/ All tests shall be performed under the worst case condition unless otherwise specified. Devices supplied to this drawing will meet levels M, D, L, R, and F, of irradiation. However, this device is only tested at the "F" level. Pre and post irradiation values are identical unless otherwise specified in Table IA. When performing post irradiation electriclal measurements for any RHA level, TA = +25°C. 2/ Devices are functionally tested using a serial scan test method. Data is shifted into the SDI pin and the DCLK pin is used as a clock. The data is used to drive the inputs of the internal logic and I/O modules, allowing a complete functional test to be performed. The outputs of the module can be read by shifting out the output response or by monitoring the PRA, PRB, or SDO pins. These tests form a part of the manufacturers's test tape and shall be maintained and available at the approved source(s) of supply upon request by DSCC or the OEM. 3/ Binning circuit delay is defined as the input-to-output delay of a special path called the "binning circuit". The binning circuit consists of one input buffer plus 16 combinatorial logic modules plus one output buffer. The logic modules are distributed along the left side of the device. These modules are configured as non-inverting buffers and are connected through programmed antifuses with typical capacitive loading. TABLE IB. SEP test limits. Symbol Characteristics Logic Modules Conditions 1/ Bias VCC = Effective LET no upset/latchup (MeV-cm2/mg) Maximum device cross section µm2/bit LET = 120 SEL Single event latchup All -55°CTcase125°C 5.5 V 177 N/A SEU Single event upset Combinatorial -55°CTcase125°C 4.5 V 17 110 Sequential -55°CTcase125°C 4.5 V 4 320 All -55°CTcase125°C 5.5 V >60 2/ N/A SEDR 2/ Single event dielectric (antifuse) rupture 1/ Verification test per TRB approved test plan. 2/ Tested at worst case that ions having perpendicular incidence, cross section < 0.002um2/antifuse at LET = 60 MeV-cm2/mg. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 10 Case Y NOTES: 1. Tie bar is for reference only, the vendor supplies the tie bar with the 4 small corner holes as oblong holes, contact vendor for other tie bar options. 2. All exposed metalized areas and leads are gold plated 100 micro inches (2.5 µm) minimum thickness over 80 to 350 micro inches (2.0 to 8.9 µm) thickness nickel. 3. Seal ring area is connected to GNDA. 4. Die attach pad is connected to GNDA. 5. GNDQ (4 PLS) is connected to GNDA. 6. Tolerances unless otherwise specified: ±1% N.L.T ±0.005 FIGURE 1. Case outlines. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 11 Case Y - Continued Dimension (unit: inch) Symbol Min. Norm. Max A 0.093 0.110 0.125 A1 0.060 0.070 0.080 A2 0.006 0.009 0.012 b 0.007 0.008 0.010 c 0.004 0.006 0.008 D1/E1 1.168 1.180 1.192 D2/E2 1.050 BSC e 0.025 BSC F1 0.860 0.870 0.880 L1 2.485 2.495 2.505 L2 2.320 BSC L3 1.485 1.500 H1 2.140 BSC Weight 8.8 gm (typical) 1.515 Metric conversion is for convenience only. Dimension (unit: mm) Symbol Min. Norm. Max. A 2.36 2.79 3.18 A1 1.52 1.78 2.03 A2 0.15 0.23 0.30 b 0.18 0.20 0.25 c 0.10 0.15 0.20 D1/E1 29.67 29.97 30.28 D2/E2 26.67 e 0.64 F1 21.84 22.10 22.35 L1 63.12 63.37 63.63 L2 58.93 L3 37.72 38.10 38.48 H1 54.36 Weight 8.8 gm (typical) FIGURE 1. Case outlines - Continued. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 12 Case U NOTES: 1. Tie bar is for reference only, vendor supplies tie bar with oblong holes, contact vendor for other tie bar options. 2. All exposed metalized areas and leads are gold plated 100 microinches (2.5 µ mm) minimum thickness over 80 to 350 microinches (2.0 to 8.9 µ mm) thickness nickel. 3. Seal ring area is connected to GNDA. 4. Die attach pad is connected to GNDA. 5. GNDQ (4 PLS) is connected to GNDA. 6. Tolerances unless otherwise specified: ±1% N.L.T ±0.005 FIGURE 1. Case outlines - Continued. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 13 Case U - Continued. Symbol Dimension (inches) Dimension (millimeters) Min Max Min Max A 0.116 0.146 2.95 3.71 b 0.007 0.013 0.17 0.33 c 0.004 0.008 0.10 0.20 D1 1.138 1.162 28.91 29.52 D2 1.050 BSC 26.67 BSC e 0.025 BSC 0.635 BSC F1 0.890 0.900 22.60 22.86 F4 0.881 0.890 22.38 22.60 L1 2.485 2.505 63.12 63.63 L2 1.690 1.710 42.93 43.43 A1 0.079 0.103 2.00 2.62 N (number of leads) 172 Weight 20 gm (Typical - with tie bar removed) FIGURE 1. Case outlines - Continued. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 14 Case outlines X and Z Device type All Device type All Device type All Device type All Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 I/O I/O I/O I/O I/O I/O I/O I/O CKA or I/O I/O I/O I/O I/O I/O I/O I/O I/O DCK or I/O I/O I/O I/O I/O CKB or I/O I/O I/O I/O I/O I/O SDI or I/O I/O I/O I/O MODE I/O I/O I/O I/O GND PRA or I/O I/O I/O I/O I/O I/O I/O D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 E1 E2 E3 E4 E5 E12 E13 E14 E15 F1 F2 F3 F4 F12 F13 F14 F15 G1 G2 G3 G4 G12 G13 G14 G15 I/O I/O I/O GND VCC GND PRB or I/O VCC I/O GND VCC GND I/O I/O I/O I/O I/O I/O GND GND 1/ GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O H1 H2 H3 H4 H12 H13 H14 H15 J1 J2 J3 J4 J12 J13 J14 J15 K1 K2 K3 K4 K12 K13 K14 K15 L1 L2 L3 L4 L12 L13 L14 L15 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SDO or I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VSV or VCC VCC GND GND VCC VSV or VCC I/O I/O I/O I/O VCC GND VKS or GND VPP or VCC I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O GND VCC GND I/O GND I/O GND VCC GND 1/ E5 is an orientation pin that is available on package Z only. FIGURE 2. Terminal connections. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 15 Case outline Y and U Device type All Device type All Device type All Device type All Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O SDO or I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 I/O I/O GND I/O I/O VKS VPP GND VCC VSV I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O SDI or I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O PRA or I/O I/O CKA or I/O 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 VCC GND I/O CKB or I/O I/O PRB or I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O DCK or I/O I/O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCC VSV I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC FIGURE 2. Terminal connections - Continued. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 16 FIGURE 3. Switching test circuit and waveforms. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 17 Note: Resistors are 1k6 resistors. FIGURE 4. Radiation exposure circuit. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 18 TABLE IIA. Electrical test requirements. 1/ 2/ 3/ 4/ 5/ 6/ 7/ Line no. Test requirements Subgroups (in accordance with MIL-PRF-38535, table III) Subgroups (in accordance with MIL-STD-883, TM 5005, table I) Device class M 1 Interim electrical parameters (see 4.2) 2 Static burn-in (method 1015) 3 Same as line 1 4 Dynamic burn-in (method 1015) 5 Same as line 1 6 Final electrical parameters (see 4.2) 7 Group A test requirements (see 4.4) 8 Device class Q Device class V 1, 7, 9 Not required Not required Required 1*, 7* Required Required Required 1*, 7* 1*, 2, 3, 7*, 8A,8B,910,11 1*, 2, 3, 7*, 8A,8B, 9, 10, 11 1*, 2, 3, 7*, 8A,8B, 9, 10, 11 1, 2, 3, 4**, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 4**, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 4**, 7, 8A, 8B, 9, 10, 11 Group C end-point electrical parameters (see 4.4) 2, 3, 7, 8A, 8B 2, 3, 7, 8A, 8B 1, 2, 3, 7, 8A, 8B, 9, 10, 11 9 Group D end-point electrical parameters (see 4.4) 2, 3, 8A, 8B 2, 3, 8A, 8B 2, 3, 8A, 8B 10 Group E end-point electrical parameters (see 4.4) 1, 7, 9 1, 7, 9 1, 7, 9 1/ 2/ 3/ 4/ 5/ 6/ 7/ Blank spaces indicate tests are not applicable. Any or all subgroups may be combined when using high-speed testers. Subgroups 7 and 8 functional tests shall verify the functionality for unprogrammed devices or that the altered item drawing pattern exists for programmed devices. * indicates PDA applies to subgroup 1 and 7. ** see 4.4.1c. indicates delta limit (see table IIB) shall be required where specified, and the delta values shall be computed with reference to the previous interim electrical parameters (see line 1). See 4.4.1d. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 19 TABLE IIB. Delta limits at +25°C. Parameter 1/ Device types All 1/ IDD ±10% of specified value of table IA IOZ ±10% of specified value of table IA tPBLH, tPBHL ±10 ns The above parameter shall be recorded before and after the required burn-in and life tests to determine the delta. 4.5 Delta measurements for device class V. Delta measurements, as specified in table IIA, shall be made and recorded before and after the required burn-in screens and steady-state life tests to determine delta compliance. The electrical parameters to be measured, with associated delta limits are listed in table IIB. The device manufacturer may, at his option, either perform delta measurements or within 24 hours after burn-in perform final electrical parameter tests, subgroups 1, 7, and 9. 4.6 Programming procedures. The programming procedures shall be as specified by the device manufacturer and shall be made available upon request. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-prepared specification or drawing. 6.1.2 Substitutability. Device class Q devices will replace device class M devices. 6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished in accordance with MIL-STD-973 using DD Form 1692, Engineering Change Proposal. 6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus when a system application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0525. 6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43216-5000, or telephone (614) 692-0674. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535 and MIL-STD-1331. 6.5.1 Timing limits. The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 20 6.5.2 Waveforms. Waveform symbol Input Output MUST BE VALID WILL BE VALID CHANGE FROM H TO L WILL CHANGE FROM H TO L CHANGE FROM L TO H WILL CHANGE FROM L TO H DON'T CARE ANY CHANGE PERMITTED CHANGING STATE UNKNOWN HIGH IMPEDANCE 6.6 Sources of supply. 6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to this drawing. 6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK103. The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 21 Appendix A Appendix A forms a part of SMD 5962-92156 10. Scope 10.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers approved QML plan for use in monolithic microcircuits, multichip modules (MCMs), hybrids, electronic modules, or devices using chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes consisting of military high reliability (device class Q) and space application (device Class V) are reflected in the Part or Identification Number (PIN). When available a choice of Radiation Hardiness Assurance (RHA) levels are reflected in the PIN. 10.2 PIN. The PIN is as shown in the following example: 01 F 92156 | | | | RHA Device designator type (10.2.1) (see 10.2.2) __________/ V Drawing number 5962 | | Federal stock class designator \___________ Q | | Device class (see 10.2.3) 9 | | X | | Die details (see 10.2.5) Die Code (see 10.2.4) 10.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 10.2.2 Device type(s). The device type(s) shall identify the circuit function as follows: Device type 01 03 04 Generic number 1280A RH1280 1280XL Circuit function Bin speed 8000 gate, field programmable gate array 8000 gate, field programmable gate array 8000 gate, field programmable gate array 200 ns 160 ns 120 ns 10.2.3 Device class designator. The device class designator shall be a single letter identifying the product assurance level as follows: Device class Q or V Device requirements documentation Certification and qualification to MIL-PRF-38535 10.2.4 Die code. The die code designator shall be a number 9 for all devices supplied as die only with no case outline. 10.2.5 Die details. The die details designation shall be a unique letter which designates the die’s physical dimensions, bonding pad location(s) and related electrical function(s), interface materials, and other assembly related information, for each product and variant supplied to this appendix. 10.2.5.1 Die physical dimensions. Device type 01 01 03 04 Die size 421mils X 437mils 421mils X 437mils 365 mils X 385 mils 286 mils X 299 mils Die thickness 15±1 mils 16±1 mils 25±1 mils 19±1 mils Die Detail A B C D Figure Number A-1 A-2 A-3 A-4 SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 22 10.2.5.2 Die bonding pad locations and electrical functions. Device type Die Detail Figure Number 01 A A-1 01 B A-2 03 C A-3 04 D A-4 10.2.5.3 Interface materials. Device type Top metalization 01 Ti-cap+Al/Cu/Si,9-12k 01 TiW+Al/Cu,9-12k 03 Ti-cap+Al/Cu/Si,9-12k 04 Ti-cap+Al/Cu/Si,9-12k Backside metalization None (backgrind) None (backgrind) None (backgrind) None (backgrind) 10.2.5.4 Assembly related information. Device type Glassivation Die Detail 01 Ox/Nitride A 01 Ox/Nitride B 03 Ox/Nitride C 04 Ox/Nitride D Die Detail A B C D Figure Number A-1 A-2 A-3 A-4 Figure Number A-1 A-2 A-3 A-4 10.2.5.5 Wafer fabrication source. Device type Source 01 Matsushita Electronics Corp. Japan 01 Texas Instrument, Texas 03 Lockheed Martin Federal System, VA 04 Chartered Semiconductor, Singapore 10.3 Absolute maximum ratings. See paragraph 1.3 within the body of this drawing for details. 10.4 Recommended operating conditions. See paragraph 1.4 within the body of this drawing for details. Die Detail A B C D Figure Number A-1 A-2 A-3 A-4 20. APPLICABLE DOCUMENTS. 20.1 Government specification, standards, and handbooks. Unless otherwise specified, the following specification, standard, and handbook of the issue listed in that issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, form a part of this drawing to the extent specified herein. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method Standard Microcircuits. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcircuit Drawings (SMD's). (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 23 20.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing shall take precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 30. REQUIREMENTS. 30.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-389535 and as specified herein or as modified in the device manufacturer’s Quality Management (QM) plan. The Modification in the QM plan shall not effect the form, fit or function as described herein. 30.2 Design, construction and physical dimensions. The design, construction and physical dimensions shall be as specified in MIL-PRF-38535 and the manufacturer’s QM plan, for device classes Q and V and herein. 30.2.1 Die physical dimensions. The die physical dimensions shall be specified in 10.2.5.1 and on figures A-1, A-2, A-3, and A-4. 30.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be as specified in 10.2.5.2 and on figures A-1, A-2, A-3, and A-4. 30.2.3 Interface materials. The interface materials for the die shall be as specified in 10.2.5.3 and on figures A-1, A-2, A-3, and A-4. 30.2.4 Assembly related information. The assembly related information shall be as specified in 10.2.5.4 and figures A-1, A-2, A-3, and A-4. 30.2.5 Truth table(s). Where technically applicable, (for die) the truth table(s) shall be as defined within paragraph 3.2.3 of the body of this document. 30.2.6 Radiation exposure circuit. The radiation exposure circuit will be as specified on figure 4 as shown within the body of this document. 30.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and post-irradiation parameter limits are as specified in table IA of the body of this document. 30.4 Electrical test requirements. The wafer probe test requirements shall include functional and parametric testing sufficient to make the packaged die capable of meeting the electrical performance requirements in table IA. 30.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a customer, shall be identified with the wafer lot number, the certification mark, the manufacturer’s identification and the PIN listed in 10.2 herein. The certification mark shall be "QML” or "Q” as required by MIL-PRF-38535. 30.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 60.4 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this appendix shall affirm that the manufacturer’s product meets, for device classes Q and V, the requirements of MIL-PRF-38535. 30.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF38535 shall be provided with each lot of microcircuit die delivered to this drawing. 30.8 Processing options. Since the device is capable of being programmed by either the manufacturer or the user to result in a wide variety of configurations; two processing options are provided for selection in the contract, using an altered item drawing. 30.8.1 Unprogrammed die delivered to the user. All testing shall be verified through wafer probe test as defined in 40.2. 30.8.2 Manufacturer-programmed die delivered to the user. The programming integrity test shall be performed during programming. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program configuration. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 24 40. QUALITY ASSURANCE PROVISIONS 40.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer’s Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 40.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the manufacturer’s QM plan. As a minimum it shall consist of: a) Wafer lot acceptance for Class V product using the criteria within MIL-STD-883 test method 5007. b) 100% wafer probe (see paragraph 30.4) c) 100% internal visual inspection to the applicable class Q or V criteria defined within MIL-STD-883 test method 2010 or the alternate procedures allowed within MIL-STD-883 test method 5004. 40.3 Conformance inspection. 40.3.1 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured (see 30.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End point electrical testing of packaged die shall be as specified in table IIA herein. Group E tests and conditions are as specified within paragraphs 4.4.4.1, 4.4.4.1.1, and 4.4.4.2 herein. 50. DIE CARRIER 50.1 Die carrier requirements. The requirements for the die carrier shall be accordance with the manufacturer’s QM plan or as specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical, mechanical and electrostatic protection. 60. NOTES 60.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit application (original equipment), design applications and logistics purposes. 60.2 Comments. Comments on this appendix should be directed to DSCC-VA, Columbus, Ohio, 43216-5000 or telephone (614)-692-0536. 60.3 Abbreviations, symbols and definitions. The abbreviations, symbols, and definitions used herein are defined within MIL-PRF-38535 and MIL-HDBK-1331. 60.4 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML38535. The vendors listed within QML-38535 have submitted a certificate of compliance (see 30.6 herein) to DSCC-VA and have agreed to this drawing. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 25 Pad# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name GND MODE I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCC VSV, VCC I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O X-Coord -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 -5075 Y-Coord 4932 4668 4495 4184 4009 3837 3662 3490 3318 3143 2974 2800 2560 2316 2141 1969 1794 1616 1428 1253 1081 906 377 133 -602 -848 -1022 -1276 -1528 -1702 -1875 -2053 -2373 -2626 -2800 -2973 -3148 -3402 -3658 -3833 -4005 -4180 -4389 -4928 Pad# 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Name GND I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O SDO, I/O I/O X-Coord -4706 -4073 -3793 -3613 -3444 -3269 -3100 -2859 -2619 -2450 -2275 -2106 -1945 -1782 -1613 -1438 -1269 -1095 -926 -751 -582 -407 -165 154 453 628 800 975 1147 1322 1495 1669 1912 2160 2335 2507 2682 2852 3013 3188 3360 3533 4151 4709 Y-Coord -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 -5284 See notes at end of table Figure A-1 and A-2. A1280A Bond Pad Locations and Functions SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 26 Pad# Name X-Coord Y-Coord 89 GND 5075 -4833 90 I/O 5075 -4375 91 I/O 5075 -4166 92 I/O 5075 -3991 93 I/O 5075 -3818 94 I/O 5075 -3644 95 I/O 5075 -3471 96 I/O 5075 -3297 97 I/O 5075 -3124 98 I/O 5075 -2950 99 I/O 5075 -2777 100 I/O 5075 -2602 101 GND 5075 -2429 102 I/O 5075 -2268 103 I/O 5075 -2094 104 I/O 5075 -1921 105 I/O 5075 -1746 106 GND 5075 -1574 107 I/O 5075 -1413 108 I/O 5075 -1238 109 VKS, GND 5075 -604 110 VPP, VCC 5075 63 111 GND 5075 428 112 VCC 5075 665 113 VSV, VCC 5075 989 114 I/O 5075 1232 115 I/O 5075 1406 116 VCC 5075 1579 117 I/O 5075 1751 118 I/O 5075 1925 119 I/O 5075 2098 120 I/O 5075 2272 121 GND 5075 2438 122 I/O 5075 2606 123 I/O 5075 2780 124 I/O 5075 2953 125 I/O 5075 3128 126 GND 5075 3289 127 I/O 5075 3461 128 I/O 5075 3636 129 I/O 5075 3808 130 I/O 5075 3983 131 I/O 5075 4394 132 I/O 5075 4952 Note: 1. All dimensions in micrometer 2. The die center is the coordinate origin (0,0). 3. VSV, VKS and Vpp pins are used for programming. to Vcc or GND as shown. Pad# 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Name GND I/O SDI, I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O PRA, I/O I/O CLKA, I/O VCC GND I/O CLKB, I/O I/O PRB, I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O DCLK, I/O I/O X-Coord 4620 4062 3882 3609 3436 3261 3089 2842 2629 2457 2282 2110 1876 1642 1470 1295 1122 948 775 595 350 176 3 -172 -393 -568 -743 -987 -1168 -1340 -1515 -1688 -2003 -2288 -2460 -2635 -2807 -2987 -3160 -3333 -3507 -3680 -4188 -4715 Y-Coord 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 5284 For normal operation, these pins should be connected Figure A-1 and A-2. A1280A Bond Pad Locations and Functions - Continued. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 27 Figure A-1 and A-2. A1280A Bond Pad Locations and Functions - Continued. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 28 Pad # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name GND MODE I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCC VSV, VCC I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O X Coords -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 -4301 Y Coords 4178 4019 3867 3723 3579 3436 3223 2976 2730 2518 2305 2093 1863 1695 1545 1395 1245 1076 915 771 627 483 13 -199 -726 -872 -1017 -1181 -1347 -1491 -1635 -1778 -1940 -2197 -2435 -2674 -2912 -3185 -3458 -3601 -3745 -3889 -4033 -4178 Pad # 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Name GND I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O SDO, I/O I/O X Coords -3963 -3811 -3652 -3508 -3364 -3220 -3077 -2869 -2662 -2491 -2318 -2145 -1938 -1731 -1558 -1385 -1212 -1039 -867 -694 -521 -348 -156 24 247 451 656 860 1064 1269 1473 1678 1917 2156 2360 2550 2739 2976 3222 3366 3509 3653 3819 3963 Y Coords -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 -4516 See notes at end of table. Figure A-3. RH1280 Bond Pad Locations and Functions SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 29 Pad # Name X Coords Y Coords 89 GND 4301 -4176 90 I/O 4301 -4016 91 I/O 4301 -3866 92 I/O 4301 -3717 93 I/O 4301 -3568 94 I/O 4301 -3418 95 I/O 4301 -3013 96 I/O 4301 -2869 97 I/O 4301 -2725 98 I/O 4301 -2581 99 I/O 4301 -2438 100 I/O 4301 -2294 101 GND 4301 -2116 102 I/O 4301 -1938 103 I/O 4301 -1794 104 I/O 4301 -1650 105 I/O 4301 -1507 106 GND 4301 -1342 107 I/O 4301 -1165 108 I/O 4301 -1007 109 VKS, GND 4301 -564 110 VPP, VCC 4301 -97 111 GND 4301 96 112 VCC 4301 323 113 VSV, VCC 4301 516 114 I/O 4301 675 115 I/O 4301 833 116 VCC 4301 1010 117 I/O 4301 1178 118 I/O 4301 1328 119 I/O 4301 1478 120 I/O 4301 1628 121 GND 4301 1796 122 I/O 4301 1977 123 I/O 4301 2140 124 I/O 4301 2303 125 I/O 4301 2466 126 GND 4301 2663 127 I/O 4301 2860 128 I/O 4301 3023 129 I/O 4301 3186 130 I/O 4301 3330 131 I/O 4301 3672 132 I/O 4301 4178 Note: 1. All dimensions in micrometer 2. The die center is the coordinate origin (0,0). 3. VSV, VKS and Vpp pins are used for programming. to Vcc or GND as shown. Pad # 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Name GND I/O SDO, I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O PRA, I/O I/O CLKA, I/O VCC GND I/O CLKB, I/O I/O PRB, I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O DCLK, I/O I/O X Coords 3963 3551 3407 3263 3120 2956 2794 2598 2401 2239 2077 1915 1719 1522 1360 1198 1036 874 712 550 372 210 48 -132 -356 -543 -729 -932 -1119 -1305 -1492 -1678 -1899 -2120 -2307 -2494 -2680 -2901 -3114 -3286 -3430 -3574 -3717 -3963 Y Coords 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 4516 For normal operation, these pins should be connected Figure A-3. RH1280 Bond Pad Locations and Functions - Continued. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 30 Figure A-3. RH1280 Bond Pad Locations and Functions - Continued. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 31 Pad # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name GND MODE I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCC VSV, VCC I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O X Coords -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 -3453 Y Coords 3354 3226 3104 2989 2874 2758 2587 2389 2191 2021 1851 1681 1496 1361 1240 1120 999 864 734 619 503 388 11 -160 -583 -700 -817 -948 -1082 -1197 -1312 -1428 -1558 -1764 -1955 -2146 -2338 -2557 -2776 -2891 -3007 -3122 -3237 -3354 Pad # 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Name GND I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O SDO, I/O I/O X Coords -3182 -3060 -2932 -2816 -2701 -2585 -2470 -2303 -2137 -2000 -1861 -1722 -1556 -1389 -1251 -1112 -973 -834 -696 -557 -418 -280 -125 19 198 362 526 690 855 1019 1183 1347 1539 1731 1895 2047 2199 2389 2587 2702 2817 2933 3066 3182 Y Coords -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 -3625 See notes at end of table. Figure A-4. A1280XL(0.6µm) Bond Pad Locations and Functions SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 32 Pad # 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 Name GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O VKS, GND VPP, VCC GND VCCI VSV, VCC I/O I/O VCCI I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O X Coords 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 3453 Y Coords -3352 -3224 -3104 -2984 -2864 -2744 -2419 -2303 -2188 -2072 -1957 -1842 -1699 -1556 -1440 -1325 -1210 -1077 -936 -808 -453 -78 77 260 414 542 669 811 946 1066 1186 1307 1442 1587 1718 1849 1980 2138 2296 2427 2558 2673 2948 3354 Pad # 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Name GND I/O SDI, I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O PRA, I/O I/O CLKA, I/O VCC GND I/O CLKB, I/O I/O PRB, I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O DCLK, I/O I/O X Coords 3182 2851 2735 2620 2505 2373 2243 2086 1928 1798 1668 1538 1380 1222 1092 962 832 702 572 442 299 169 39 -106 -286 -436 -586 -748 -898 -1048 -1198 -1347 -1525 -1702 -1852 -2002 -2152 -2329 -2500 -2638 -2754 -2869 -2984 -3182 Y Coords 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 3625 Note: 1. All dimensions in micrometer 2. The die center is the coordinate origin (0,0). 3. VSV, VKS and Vpp pins are used for programming. For normal operation, these pins should be connected to Vcc or GND as shown. Figure A-4. A1280XL(0.6µm) Bond Pad Locations and Functions - Continued. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 33 Figure A-4. A1280XL(0.6µm) Bond Pad Locations and Functions - Continued. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 DSCC FORM 2234 APR 97 5962-92156 A REVISION LEVEL H SHEET 34 STANDARD MICROCIRCUIT DRAWING SOURCE APPROVAL BULLETIN DATE: 00-04-28 Approved sources of supply for SMD 5962-92156 are listed below for immediate acquisition only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. 1/ 2/ 3/ Standard microcircuit 1/ drawing PIN Vendor CAGE number Vendor similar 3/ PIN 5962-9215601MXC 0J4Z0 2/ A1280A-PG176B TPC1280MGB176B 5962-9215601MYC 0J4Z0 2/ A1280A-CQ172B TPC1280MHFG172B 5962-9215601MXA 0J4Z0 A1280A-PG176B 5962-9215601MYA 0J4Z0 A1280A-CQ172B 5962-9215601MZC 2/ 2/ A1280A-PG177B TPC1280MGB177B 5962-9215601MUC 2/ RP1280A-CQ172B 5962-9215602MXC 0J4Z0 2/ A1280A-1PG176B TPC1280MGB176B-1 5962-9215602MYC 0J4Z0 2/ A1280A-1CQ172B TPC1280MHFG172B-1 5962-9215602MXA 0J4Z0 A1280A-1PG176B 5962-9215602MYA 0J4Z0 A1280A-1CQ172B 5962-9215602MZC 2/ 2/ A1280A-1PG177B TPC1280MGB177B-1 5962-9215602MUC 2/ RP1280A-1CQ172B 5962F9215603QYC 0J4Z0 RH1280-CQ172V 5962-9215604QXC 0J4Z0 A1280XL-PG176B 5962-9215604QYC 0J4Z0 A1280XL-CQ172B 5962-9215605QXC 0J4Z0 A1280XL-1PG176B 5962-9215605QYC 0J4Z0 A1280XL-1CQ172B The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed, contact the vendor to determine its availability. No longer available from an approved source. Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Vendor CAGE number 0J4Z0 Vendor name and address Actel Corporation 955 East Arques Ave. Sunnyvale, CA 94086 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in this information bulletin. STANDARD MICROCIRCUIT DRAWING SOURCE APPROVAL BULLETIN - Continued. The following table lists the SMD part numbers for die. 1/ Vendor similar 1/ PIN Standard microcircuit drawing PIN Vendor CAGE number 5962-9215601Q9A 0J4Z0 A1280A-DIE 5962-9215601Q9B 0J4Z0 A1280A-DIE 5962F9215603Q9C 0J4Z0 RH1280-DIE 5962-9215604Q9D 0J4Z0 A1280XL-DIE Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Vendor CAGE number 0J4Z0 Vendor name and address Actel Corporation 955 East Arques Ave. Sunnyvale, CA 94086 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in this information bulletin.