NSC DS90CF561

DS90CF561/DS90CF562
LVDS 18-Bit Color Flat Panel Display (FPD) Link
General Description
The DS90CF561 transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. The DS90CF562 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL data. At
a transmit clock frequency of 40 MHz, 18 bits of RGB data
and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 280 Mbps per
LVDS data channel. Using a 40 MHz clock, the data throughput is 105 Megabytes per second. These devices are offered
with falling edge data strobes for convenient interface with a
variety of graphics and LCD panel controllers.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n
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Up to 105 Megabyte/sec bandwidth
Narrow bus reduces cable size and cost
290 mV swing LVDS devices for low EMI
Low power CMOS design
Power down mode
PLL requires no external components
Low profile 48-lead TSSOP package
Falling edge data strobe
Compatible with TIA/EIA-644 LVDS standard
Block Diagrams
DS90CF561
DS90CF562
DS012485-26
Order Number DS90CF561MTD
See NS Package Number MTD48
DS012485-1
Order Number DS90CF562MTD
See NS Package Number MTD48
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS012485
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DS90CF561/DS90CF562 LVDS 18-Bit Color Flat Panel Display (FPD) Link
July 1997
Block Diagrams
(Continued)
Application
DS012485-2
Connection Diagrams
DS90CF561
DS012485-3
DS90CF562
DS012485-4
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2
Absolute Maximum Ratings (Note 1)
DS90CF561
1.98W
DS90CF562
1.89W
Package Derating:
DS90CF561
16 mW/˚C above +25˚C
DS90CF562
15 mW/˚C above +25˚C
This device does not meet 2000V ESD rating (Note 4).
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
−0.3V to +6V
CMOS/TTL Input Voltage
−0.3V to (VCC + 0.3V)
CMOS/TTL Ouput Voltage
−0.3V to (VCC + 0.3V)
LVDS Receiver Input Voltage
−0.3V to (VCC + 0.3V)
LVDS Driver Output Voltage
−0.3V to (VCC + 0.3V)
LVDS Output
Short Circuit Duration
continuous
Junction Temperature
+150˚C
Storage Temperature Range
−65˚C to +150˚C
Lead Temperature
(Soldering, 4 sec.)
+260˚C
Maximum Power Dissipation @ +25˚C
MTD48 (TSSOP) Package:
Recommended Operating
Conditions
Supply Voltage (VCC)
Operating Free Air
Temperature (TA)
Receiver Input Range
Supply Noise Voltage (VCC)
Min
4.5
Nom Max
5.0
5.5
Units
V
−10
0
+25
˚C
V
mVP-P
+70
2.4
100
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
CMOS/TTL DC SPECIFICATIONS
VIH
High Level Input Voltage
2.0
VCC
VIL
Low Level Input Voltage
GND
0.8
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
VCL
Input Clamp Voltage
IIN
Input Current
IOS
Output Short Circuit Current
IOH = −0.4 mA
IOL = 2 mA
3.8
ICL = −18 mA
VIN = VCC, GND, 2.5V or 0.4V
VOUT = 0V
4.9
V
V
0.1
0.3
V
−0.79
−1.5
V
± 5.1
± 10
µA
−120
mA
450
mV
35
mV
LVDS DRIVER DC SPEClFlCATIONS
VOD
Differential Output Voltage
∆VOD
Change in VOD between
RL = 100Ω
250
290
Complimentary Output States
VCM
Common Mode Voltage
∆VCM
Change in VCM between
1.1
1.25
1.375
V
35
mV
1.6
V
−2.9
−5
mA
±1
± 10
µA
+100
mV
Complimentary Output States
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
IOS
Output Short Circuit Current
IOZ
Output TRI-STATE ® Current
1.3
0.9
VOUT = 0V, RL = 100Ω
Power Down = 0V, VOUT = 0V or VCC
1.01
V
LVDS RECEIVER DC SPECIFlCATIONS
VTH
Differential Input High Threshold
VTL
Differential Input Low Threshold
IIN
Input Current
VCM = +1.2V
−100
mV
± 10
± 10
µA
34
51
mA
f = 37.5 MHz
f = 32.5 MHz
36
53
mA
27
47
mA
f = 37.5 MHz
28
48
mA
VIN = +2.4V
VIN = 0V
VCC = 5.5V
f = 32.5 MHz
µA
TRANSMITTER SUPPLY CURRENT
ICCTW
Transmitter Supply Current,
Worst Case
RL = 100Ω, CL = 5 pF,
Worst Case Pattern
(Figure 1, Figure 3)
ICCTG
Transmitter Supply Current,
16 Grayscale
RL = 100Ω, CL = 5 pF,
Grayscale Pattern
(Figure 2, Figure 3)
3
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Electrical Characteristics
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
1
25
µA
f = 32.5 MHz
55
75
mA
f = 37.5 MHz
f = 32.5 MHz
60
80
mA
35
55
mA
f = 37.5 MHz
37
58
mA
1
10
µA
TRANSMITTER SUPPLY CURRENT
ICCTZ
Transmitter Supply Current,
Power Down
Power Down = Low
RECEIVER SUPPLY CURRENT
ICCRW
Receiver Supply Current,
Worst Case
CL = 8 pF,
Worst Case Pattern
(Figure 1, Figure 4)
ICCRG
Receiver Supply Current,
16 Grayscale
CL = 8 pF,
16 Grayscale Pattern
(Figure 2, Figure 4)
ICCRZ
Receiver Supply Current,
Power Down
Power Down = Low
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for VCC = 5.0V and TA = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and ∆VOD).
Note 4: ESD Rating:
HBM (1.5 kΩ, 100 pF)
PLL V CC ≥ 1000V
All other pins ≥ 2000V
EIAJ (0Ω, 200 pF) ≥ 150V
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Typ
Max
Units
LLHT
Symbol
LVDS Low-to-High Transition Time (Figure 3)
Parameter
0.75
1.5
ns
LHLT
LVDS High-to-Low Transition Time (Figure 3)
0.75
1.5
ns
TCIT
TxCLK IN Transition Time (Figure 5)
TCCS
TxOUT Channel-to-Channel Skew (Note 5) (Figure 6)
TPPos0
Transmitter Output Pulse Position for Bit 0 (Figure 17)
−200
150
350
ps
TPPos1
Transmitter Output Pulse Position for Bit 1
6.3
7.2
7.5
ns
TPPos2
Transmitter Output Pulse Position for Bit 2
12.8
13.6
14.6
ns
TPPos3
Transmitter Output Pulse Position for Bit 3
20
20.8
21.5
ns
TPPos4
Transmitter Output Pulse Position for Bit 4
27.2
28
28.5
ns
TPPos5
Transmitter Output Pulse Position for Bit 5
34.5
35.2
35.6
ns
TPPos6
Transmitter Output Pulse Position for Bit 6
42.2
42.6
42.9
ns
TPPos0
Transmitter Output Pulse Position for Bit 0 (Figure 16)
−100
100
300
ps
TPPos1
Transmitter Output Pulse Position for Bit 1
2.9
3.3
3.9
ns
TPPos2
Transmitter Output Pulse Position for Bit 2
6.1
6.6
7.1
ns
TPPos3
Transmitter Output Pulse Position for Bit 3
9.7
10.2
10.7
ns
TPPos4
Transmitter Output Pulse Position for Bit 4
13
13.5
14.1
ns
TPPos5
Transmitter Output Pulse Position for Bit 5
17
17.4
17.8
ns
TPPos6
Transmitter Output Pulse Position for Bit 6
20.3
20.8
21.4
ns
TCIP
TxCLK IN Period (Figure 7)
25
T
50
ns
TCIH
TxCLK IN High Time (Figure 7)
0.35T
0.5T
0.65T
ns
0.35T
0.5T
0.65T
TCIL
TxCLK IN Low Time (Figure 7)
TSTC
TxIN Setup to TxCLK IN (Figure 7)
THTC
TxIN Hold to TxCLK IN (Figure 7)
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Min
f = 20 MHz
f = 40 MHz
f = 20 MHz
f = 40 MHz
14
4
ns
350
ps
ns
ns
8
2.5
8
ns
2
ns
Transmitter Switching Characteristics
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
TCCD
Parameter
Min
TxCLK IN to TxCLK OUT Delay @ 25˚C,
VCC = 5.0V (Figure 9)
Typ
5
Max
Units
9.7
ns
TPLLS
Transmitter Phase Lock Loop Set (Figure 11)
10
ms
TPDD
Transmitter Powerdown Delay (Figure 15)
100
ns
Note 5: This limit based on bench characterization.
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Typ
Max
Units
CLHT
Symbol
CMOS/TTL Low-to-High Transition Time (Figure 4)
3.5
6.5
ns
CHLT
CMOS/TTL High-to-Low Transition Time (Figure 4)
2.7
6.5
ns
RCOP
RxCLK OUT Period (Figure 8)
T
50
RSKM
Receiver Skew Margin (Note 6). VCC = 5V, TA = 25˚C (Figure 18)
RCOH
RxCLK OUT High Time (Figure 8)
RCOL
Parameter
Min
25
RxCLK OUT Low Time (Figure 8)
RSRC
RxOUT Setup to RxCLK OUT (Figure 8)
RHRC
RxOUT Hold to RxCLK OUT (Figure 8)
RCCD
RxCLK IN to RxCLK OUT Delay @ 25˚C,
VCC = 5.0V (Figure 10)
f = 20 MHz
f = 40 MHz
f = 20 MHz
ns
1.1
ns
700
ps
21.5
ns
f = 40 MHz
f = 20 MHz
f = 40 MHz
10.5
ns
19
ns
6
ns
f = 20 MHz
f = 40 MHz
f = 20 MHz
14
ns
f = 40 MHz
4.5
ns
16
ns
6.5
7.6
ns
11.9
ns
RPLLS
Receiver Phase Lock Loop Set (Figure 12)
10
ms
RPDD
Receiver Powerdown Delay (Figure 16)
1
µs
Note 6: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account for transmitter output skew(TCCS)
and the setup and hold time (internal data sampling window), allowing LVDS cable skew dependent on type/length and source clock(TxCLK IN) jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle)
AC Timing Diagrams
DS012485-5
FIGURE 1. “Worst Case” Test Pattern
5
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AC Timing Diagrams
(Continued)
DS012485-6
FIGURE 2. “16 Grayscale” Test Pattern (Notes 7, 8, 9, 10)
Note 7: The worst case test pattern produces a maximum toggling of device digital circuitry, LVDS I/O and TTL I/O.
Note 8: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 9: Figure 1 and Figure 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Note 10: Recommended pin to signal mapping. Customer may choose to define differently.
DS012485-8
DS012485-9
FIGURE 3. DS90CF561 (Transmitter) LVDS Output Load and Transition Timing
DS012485-10
DS012485-11
FIGURE 4. DS90CF562 (Receiver) CMOS/TTL Output Load and Transition Timing
DS012485-15
FIGURE 5. DS90CF561 (Transmitter) Input Clock Transition Time
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AC Timing Diagrams
(Continued)
DS012485-16
Measurements at Vdiff = 0V
TCCS measured between earliest and latest initial LVDS edges.
TxCLK OUT Differential High→Low Edge for DS90CF561
TxCLK OUT Differential Low→High Edge for DS90CR561
FIGURE 6. DS90CF561 (Transmitter) Channel-to-Channel Skew and Pulse Width
DS012485-12
FIGURE 7. DS90CF561 (Transmitter) Setup/Hold and High/Low Times
DS012485-13
FIGURE 8. DS90CF562 (Receiver) Setup/Hold and High/Low Times
DS012485-17
FIGURE 9. DS90CF561 (Transmitter) Clock In to Clock Out Delay
7
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AC Timing Diagrams
(Continued)
DS012485-18
FIGURE 10. DS90CF562 (Receiver) Clock In to Clock Out Delay
DS012485-14
FIGURE 11. DS90CF561 (Transmitter) Phase Lock Loop Set Time
DS012485-19
FIGURE 12. DS90CF562 (Receiver) Phase Lock Loop Set Time
DS012485-20
FIGURE 13. Seven Bits of LVDS in One Clock Cycle
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AC Timing Diagrams
(Continued)
DS012485-21
FIGURE 14. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CF561)
DS012485-22
FIGURE 15. Transmitter Powerdown Delay
DS012485-23
FIGURE 16. Receiver Powerdown Delay
9
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AC Timing Diagrams
(Continued)
DS012485-24
FIGURE 17. Transmitter LVDS Output Pulse Position Measurement
DS012485-25
SW — Setup and Hold Time (Internal Data Sampling Window)
TCCS — Transmitter Output Skew
RSKM ≥ Cable Skew (Type, Length) + Source Clock Jitter (Cycle to Cycle)
Cable Skew — Typically 10 ps–40 ps per foot
FIGURE 18. Receiver LVDS Input Skew Margin
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DS90CF561 Pin Description — FPD Link Transmitter
I/O
No.
TxIN
Pin Name
I
21
TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines (FPLINE, FPFRAME,
DRDY). (Also referred to as HSYNC, VSYNC and DATA ENABLE.)
Description
TxOUT+
O
3
Positive LVDS differential data output
TxOUT−
O
3
Negative LVDS differential data output
FPSHIFT IN
I
1
TTL level clock input. The falling edge acts as data strobe.
TxCLK OUT+
O
1
Positive LVDS differential clock output
TxCLK OUT−
O
1
Negative LVDS differential clock output
PWR DOWN
I
1
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power
down.
VCC
I
4
Power supply pins for TTL inputs
GND
I
5
Ground pins for TTL inputs
PLL VCC
I
1
Power supply pin for PLL
PLL GND
I
2
Ground pins for PLL
LVDS VCC
I
1
Power supply pin for LVDS outputs
LVDS GND
I
3
Ground pins for LVDS outputs
DS90CF562 Pin Description — FPD Link Receiver
Pin Name
RxIN+
I/O
No.
I
3
Positive LVDS differential data inputs
Description
RxIN−
I
3
Negative LVDS differential data inputs
RxOUT
O
21
TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines (FPLINE,
FPFRAME, DRDY). (Also referred to as HSYNC, VSYNC and DATA ENABLE.)
RxCLK IN+
I
1
Positive LVDS differential clock input
RxCLK IN−
I
1
Negative LVDS differential clock input
FPSHIFT OUT
O
1
TTL level clock output. The falling edge acts as data strobe.
PWR DOWN
I
1
TTL level input. Assertion (low input) maintains the receiver outputs in the previous state
VCC
I
4
Power supply pins for TTL outputs
GND
I
5
Ground pins for TTL outputs
PLL VCC
I
1
Power supply for PLL
PLL GND
I
2
Ground pin for PLL
LVDS VCC
I
1
Power supply pin for LVDS inputs
LVDS GND
I
3
Ground pins for LVDS inputs
11
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DS90CF561/DS90CF562 LVDS 18-Bit Color Flat Panel Display (FPD) Link
Physical Dimensions
inches (millimeters) unless otherwise noted
48-Lead Molded Thin Shrink Small Outline Package, JEDEC
NS Package Number MTD48
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be reasonably expected to result in a significant injury
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