HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO 74OL6000 74OL6001 74OL6010 74OL6011 SYMBOL 6 1 6 BUFFER 1 PIN CONFIGURATION 6 1 1-VCCI (Input VCC) 6-VCCO (Output VCC) 2-VIN (Data In) 5-VO (Data Out) 3-GND, (Input GND) 4-GNDO (Output GND) INVERTER DEVICE CONFIGURATION Logic Compatibility Part Number Logic Function Output Configuration TTL BUFFER TOTEM POLE LSTTL TTL INVERTER TOTEM POLE LSTTL CMOS BUFFER OPEN COLLECTOR LSTTL CMOS INVERTER OPEN COLLECTOR INPUT OUTPUT 74OL 6000 LSTTL 74OL 6001 74OL 6010 74OL 6011 SCHEMATIC 74OL6000 74OL6001 74OL6010 74OL6011 NOISE SHIELD NOISE SHIELD NOISE SHIELD NOISE SHIELD 1 6 1 6 1 6 1 6 2 5 2 5 2 5 2 5 3 4 3 4 3 4 3 4 LSTLL to TTL Buffer LSTLL to TTL Inverter 2001 Fairchild Semiconductor Corporation DS300204 2/27/01 LSTLL to CMOS Buffer 1 OF 13 LSTLL to CMOS Inverter www.fairchildsemi.com HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO 74OL6000 74OL6001 74OL6010 74OL6011 DESCRIPTION OPTOLOGICTM is the first family of truly AlGaAs LED emitter. This novel integration to any CMOS logic between 4.5 and 15 volts. logic compatible optically coupled logic scheme eliminates CTR degradation over time The 74OL6010/11 may also by used to interface gates. and temperature. drive power MOSFETS or transistors up to The family consists of four device types The emitter is optically coupled to an inte- offering LSTTL to TTL and LSTTL to grated photodetector/high-gain, high-speed The Optologic coupler family typically offers CMOS interfacing. Each of these interfac- propagation of delays of 60 ns and can ing functions is available as a buffer (A=B), output amplifier IC. The superior 15kV/µS common-mode noise rejection is ensured or as an inverter (A=B). through the use of an optically transparent 15 volts. noise shield. support 15 MBaud data communication. The two input chips and the output chip are assembled in a 6-pin DIP high insula- The LSTTL input compatibility is provided by an input integrated circuit, with industry The TTL compatible output has a totem- tion voltage plastic package. It provides a standard logic levels. This input amplifier IC pole with a fan-out of 10. The CMOS com- withstand test voltage of 5300 VRMS switches a temperature compensated cur- patible output has an open collector (1 minute). rent source driving a high speed 850 nm Schottky-clamped transistor that interfaces Vcc Vcc 22 kΩ TYP. Vcc 150 Ω TYP. RL INPUT OUTPUT GND LSTTL INPUT CIRCUIT OUTPUT GND CMOS OUTPUT CIRCUIT GND TTL OUTPUT CIRCUIT All Inputs FEATURES 74OL6000/01 Output Industry first LSTTL to TTL and LSTTL to CMOS complete logic-to-logic optocoupler Incorporates LED drive circuitry use as logic gate Very high speed Choice of buffer or inverter Choice of TTL or CMOS compatible output up to 15 volts Fan-out of 10 TTL loads, fan-in 1 LSTTL load Internal noise shield very high CMR of ±15 kV/µS UL recognized (File #E90700) Same noise immunity as LSTTL/TTL. www.fairchildsemi.com 74OL6010/11 Output APPLICATIONS Transmission line interface receiver and driver Excellent as bridged receiver in fast LAN highways Bus interface Logic family interface with ground loop noise elimination High speed AC/DC voltage sensing Driver for power semiconductor devices Level shifting Replaces fast pulse transformers 2 OF 13 2/27/01 DS300204 HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO ELECTRICAL CHARACTERISTICS Parameter Symbol Min 74OL6000 74OL6001 74OL6010 74OL6011 (TA = 0°C to 70°C Unless otherwise specified) Typ* Max Units Test Conditions 74OL6000 74OL6001 Fig. Notes 74OL6000/01 TTL OUTPUT 74OL6000/01 Input Supply Voltage VCCI 4.5 5.0 5.5 V 1 Output Supply Voltage VCCO 4.5 5.0 5.5 V 1 VIH 2.0 V 1 High-Level Input Voltage Low-Level Input Voltage VIL 0.8 V Input Clamp Voltage VIK -1.2 V VCCI = 4.5 V, II = -18 mA 1 High-Level Input Current IIH 40.0 µA VCCI = 5.5 V, VIH = 4.5 V 1 Low-Level Input Current IIL µA VCCI = 5.5 V, VIL = 0.4 V 1 1.0 -200.0 -400.0 1 Input Supply Current (high) ICCIH 10.0 14.0 mA VCCI = 5.5 V, VIN = VIH 1 Input Supply Current (low) ICCIL 10.0 14.0 mA VCCI = 5.5 V, VIN = VIL 1 High-Level Output Voltage VOH 2.4 3.0 V VIN = 2.0 V VIN = 0.8 V 0.3 VOL V VIN = 0.8V VIN = 2.0V 0.5 High-Level Output Current IOH -8.0 Low-Level Output Current IOL 16.0 Short-Circuit Output Current IOS -5.0 -25.0 -10.0 -40.0 1 IOH = -400 µA VCCI = 4.5 V, VCCO = 4.5 V, 0.6 Low-Level Output Voltage VCCI = 4.5 V, VCCO = 4.5 V, IOL = 16 mA 1 VCCI = 4.5 V, VCCO = 4.5 V, IOL = 4 mA mA VIN = VIH VIN = VIL mA VIN = 0.8 V VIN = 2.0V mA VIN = VIH VIN = VIL Output Supply Current (high) ICCOH 9.0 15.0 mA VIN = VIH VIN = VIL Output Supply Current (low) ICCOL 8.0 12.0 mA VIN = VIL VIN = VIH VCCI = 4.5 V, VCCO = 4.5 V, 1 VOH = 2.4 V VCCI = 4.5 V, VCCO = 4.5 V, 1 VOL = 0.6 V VCCI = 5.5 V, VCCO = 5.5 V, 1 VCCI = 5.5 V, VO = VOH, 1 VCCO = 5.5 V VCCI = 5.5 V, VO = VOL, 1 VCCO = 5.5 V * All typical values are at TA=25°C SWITCHING CHARACTERISTCS (TA = 25°C Unless otherwise specified) Parameter Symbol Min Typ Max Units Test Conditions Fig. Notes TTL OUTPUT 74OL6000/01 Propagation Delay Time For Output Low Level tPHL 60 100 ns 15, 17 1 Propagation Delay Time For Output High Level tPLH 70 100 ns 15, 17 1 Output Rise Time For Output High Level tr 45 n Output Fall Time For Output Low Level tf 5 ns DS300204 2/27/01 3 OF 13 VCCI = 5 V, VCCO = 5 V 15, 17 1 15, 17 1 www.fairchildsemi.com HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO ELECTRICAL CHARACTERISTICS Parameter 74OL6000 74OL6001 74OL6010 74OL6011 (TA = 0°C to 70°C Unless otherwise specified) Symbol Min Typ* Max Units Test Conditions 74OL6010 74OL6011 Fig. Notes 74OL6010/11 CMOS OUTPUT 74OL6010/11 Input Supply Voltage VCCI 4.5 Output Supply Voltage VCCO 4.5 VIH 2.0 High-Level Input Voltage 5.0 5.5 V 1 15.0 V 1,3 V 1 Low-Level Input Voltage VIL 0.8 V Input Clamp Voltage VIK -1.2 V High-Level Input Current IIH 40.0 Low-Level Input Current IIL 1.0 -200.0 -400.0 1 VCCI = 4.5 V, II = -18 mA 1 µA VCCI = 5.5 V, VIH = 4.5 V 1 µA VCCI = 5.5 V, VIL = -0.4 V 1 Input Supply Current (high) ICCIH 10.0 14.0 mA VCCI = 5.5 V, VIN = VIH 1 Input Supply Current (low) ICCIL 10.0 14.0 mA VCCI = 5.5 V, VIN = VIL 1 VCCI = 4.5 V, VCCO = 4.5 V, 0.6 Low-Level Output Voltage VOL 0.4 V VIN = 0.8V VIN = 2.0V 0.5 High-Level Output Current IOH Low-Level Output Current IOL 1.0 100.0 16.0 9.0 Output Supply Current (high) Output Supply Current (low) 18.0 8.0 12.0 ICCOL VIN = VIH VIN = VIL mA VIN = 0.8 V VIN = 2.0V 1 VCCO = 4.5 - 15 V VCCI = 4.5 V, VOL = 0.6V, 1 VCCO = 4.5 - 15 V VCCI = 5.5 V, VO = VOH, VIN = VIH VIN = VIL VCCO = 4.5 V 1 VCCI = 5.5 V, VO = VOL, VCCO = 15 V VCCI = 5.5 V, VO = VOL, mA 11.0 VCCI = 4.5 V, VOH = 15 V, µA mA 11.0 1 VCCI = 4.5 V, VCCO = 4.5 V, IOL = 4 mA 12.0 ICCOH IOL = 16 mA VIN = VIL VIN = VIH 18.0 VCCO = 4.5 V 1 VCCI = 5.5 V, VO = VOL, VCCO = 15 V * All typical values are at TA=25°C SWITCHING CHARACTERISTCS (TA = 25°C Unless otherwise specified) Parameter Symbol Min Typ Max Units Test Conditions Fig. Notes 15, 18 1 TTL OUTPUT 74OL6010/11 Propagation Delay Time For Output Low Level tPHL 60 120 Propagation Delay Time For Output High Level 180 ns tPLH 100 Output Rise Time For Output High Level tr 50 ns Output Fail Time For Output Low Level tf 5 ns www.fairchildsemi.com 4 OF 13 ns VCCI = 5 V, VCCO = 5 V, RL = 470 Ω 15, 18 1 15, 18 1 15, 18 1 2/27/01 DS300204 HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS LSTTL TO ABSOLUTE MAXIMUM RATINGS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER 74OL6000 74OL6001 74OL6010 74OL6011 (TA = 25°C unless otherwise specified) Parameter Symbol Device Value Units TSTG All -55 to +125 °C Operating Temperature TOPR All 0 to +70 °C Lead Solder Temperature TSOL All 260 for 10 sec °C PD All 350 mW TOTAL DEVICE Storage Temperature Power Dissipation EMITTER Input Supply Voltage Input Voltage DETECTOR Average Output Current VCCI VIN All All 7 7 V V IO (avg) VCCO 40 7 18 7 18 mA Output Supply Voltage All 74OL6000/01 74OL6010/11 74OL6000/01 74OL6010/11 Output Voltage ELECTRICAL CHARACERISTICS Parameter VO V V (TA = 0°C to 70°C Unless otherwise specified) Symbol Min Typ Max Units CMH 5000 15000 V/µS CML -5000 -15000 V/µS Common Mode Coupling Capacitance CCM 0.005 pF Capacitance (input-output) CI-O 0.7 pF Withstand Insulation Test Voltage VISO Insulation Resistance RISO Test Conditions Fig. Notes 74OL6000/01/10/11 Common Mode Transient Immunity at Logic High Level Output Common Mode Transient Immunity at Logic Low Level Output DS300204 2/27/01 5300 VRMS 10 5 OF 13 Ω VCCI = 5 V, VCCO = 5 V, VCM = 50 Vp-p 16, 19 VI-O = 0, f = 1 MHz TA = 25°C, t = 1 min, II-Ο ≤ 1µA VI-O = 500 VDC 16, 19 2 2 2 www.fairchildsemi.com HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO Figure 1. Input Current vs. Ambient Temperature 74OL6000 74OL6001 74OL6010 74OL6011 Figure 2. Input Supply Current vs. Ambient Temperature 15 100 IIH II - INPUT CURRENT (µA) 0 -100 ICCI - INPUT SUPPLY CURRENT (mA) 14 VCCI = 5.5V VIH = 4.5V VIL = 0.4V IIL -200 13 12 ICCIH - 74OL6000-6010 ICCIL - 74OL6001-6011 11 10 9 8 ICCIH - 74OL6001-6011 ICCIL - 74OL6000-6010 7 6 -300 -40 -20 0 20 40 60 80 5 -40 100 Figure 3. Output Supply Current vs. Ambient Temperature IO - OUTPUT SUPPLY CURRENT (mA) ICCO - OUTPUT SUPPLY CURRENT (mA) ICCOH ICCOL ICCOH ICCOL ICCOH ICCOL 9 74OL6010/6011 VCCI = 5.5V VCCO = 15V 74OL6010/6011 74OL6000/6001 VCCI = 5.5V VCCO = 5.5V -20 0 20 40 60 80 80 100 IOL 40 VCCI = 4.5V VCCO = 4.5V VOL = 0.6V VOH = 2.4V 30 20 10 0 IOH -10 -30 -40 100 (74OL6000/6001) -20 0 20 40 60 80 100 TA - AMBIENT TEMPERATURE (˚C) Figure 6. Low-Level Output Voltage vs. Ambient Temperature 0.5 VOL - LOW-LEVEL OUTPUT VOLTAGE (V) 5 VOH - HIGH-LEVEL OUTPUT VOLTAGE (V) 60 -20 VCCI = 5.5V VCCO = 5.5V Figure 5. High-Level Output Voltage vs. Ambient Temperature VCCI = 4.5V VCCO = 4.5V IOH = -400µA 4 3 2 1 -20 0 20 40 60 80 0.4 @ IOL = 16mA 0.3 @ IOL = 4mA 0.2 VCCI = 4.5V VCCO = 4.5V 0.1 -40 100 -20 0 20 40 60 80 100 TA - AMBIENT TEMPERATURE (˚C) TA - AMBIENT TEMPERATURE (˚C) www.fairchildsemi.com 40 50 TA - AMBIENT TEMPERATURE (˚C) 0 -40 20 60 12 0 -40 0 Figure 4. Output Current vs. Ambient Temperature 15 3 -20 TA - AMBIENT TEMPERATURE (˚C) TA - AMBIENT TEMPERATURE (˚C) 6 VCCI = 5.5V 6 OF 13 2/27/01 DS300204 HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO 74OL6000 74OL6001 74OL6010 74OL6011 Figure 8. 74OL6000/01 Switching Times vs. Ambient Temperature Figure 7. 74OL6010/11 Leakage Current vs. Ambient Temperature VCCIN = 4.5V VCCO = 15V VOUT = 15V 4 VCCI = 5.0V VCCO = 5.0V P.W = 200ns PERIOD = 1µS 200 SWITCHING TIME (ns) IOH - LEAKAGE CURRENT (µA) 5 3 2 tPLH tPHL tr 100 50 10 tf 5 1 0 -40 -20 0 20 40 60 80 1 -40 100 -20 TA - AMBIENT TEMPERATURE (˚C) RL = 470Ω P.W = 200ns PERIOD = 1µS tPLH SWITCHING TIME (ns) 200 tPLH tr tPHL tr 100 50 10 tf tf 5 1 -40 -20 0 20 40 60 80 60 80 100 100 10 9 8 VCCO = 5V VCCO = 5V VOH = 2V VOL = 0.8V RL = 470Ω (74OL6010/6011) 7 6 5 4 3 2 1 0 500 1000 15000 2000 2500 Figure 11. Supply Current vs. Supply Voltage Figure 12. Power Dissipation vs. Ambient Temperature PT - TOTAL PACKAGE POWER DISSIPATION (mW) VCM - COMMON MODE TRANSIENT 12 ICCO ICC 10 ICC - SUPPLY CURRENT (mA) 40 11 TA - AMBIENT TEMPERATURE (˚C) 8 6 VCCO RANGE FOR 74OL6000/6001 4 2 0 4 5 6 7 8 9 10 11 12 13 2/27/01 MAXIMUM ALLOWABLE POWER DISSIPATION @ TA = 25˚C 300 @TA = 55˚C 200 VCCI = 5.5V @TA = 70˚C @TA = 85˚C 100 VCCI = 4.5V 0 4 14 15 5 6 7 8 9 10 11 12 13 14 15 VCCO - OUTPUT SUPPLY VOLTAGE (V) VCC - SUPPLY VOLTAGE (V) DS300204 20 Figure 10. Common Mode Rejection vs. Common Mode Voltage CM - COMMON MODE TRANSIENT IMMUNITY (KV/µS) Figure 9. 74OL6010/11 Switching Times vs. Ambient Temperature VCCO = 5V VCCO = 15V VCCI = 5V 0 TA - AMBIENT TEMPERATURE (˚C) 7 OF 13 www.fairchildsemi.com HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO Figure 14. Input Current vs. Input Voltage Figure 13. Input Threshold Voltage vs. Ambient Temperature 1.6 100 1.5 IIN - INPUT CURRENT (µA) VINTH - INPUT THRESHOLD VOLTAGE (V) 74OL6000 74OL6001 74OL6010 74OL6011 1.4 1.3 1.2 1.1 -100 -200 VCCI = 5.0V VCCO = 5.0V 1.0 0 VCCI = 4.5V 0.0 -40 -300 -20 0 20 40 60 80 0 100 1 2 3 4 5 6 VIN - INPUT VOLTAGE (V) TA - AMBIENT TEMPERATURE (˚C) Figure 15. Switching Time Test Circuit Figure 16. Common Mode Rejection Test Circuit VCCO +5 V VCCI +5 V 1 .1µF .1µF PULSE GEN PW =200ns PERIOD = 1µS tr = 5ns Zo = 50Ω VCCO +5 V 6 .1µF 470Ω (74OL6010/11) 2 6 .1µF 470Ω (74OL6010/11) 1kΩ 2 5 3 6 L/H 5 CL* 3 H/L 1 VO 4 *CL = 15pF STRAY CAPACITANCE INCLUDING PROBE - + VCM www.fairchildsemi.com 8 OF 13 2/27/01 DS300204 HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO 74OL6000 74OL6001 74OL6010 74OL6011 Figure 18. Switching Parameters 74OL6010/11 Figure 17. 74OL6000/01 Switching Times vs. Ambient Temperature INPUT, VI 3.2V INPUT, VI 3.2V 1.3V 1.3V tPLH tPLH tPHL tPHL 90% 90% OUTPUT, VO (74OL6000) OUTPUT, VO (74OL6010) 1.3V 10% tr tf tf tr 50% 10% tr tf tf tr 90% 90% OUTPUT, VO (74OL6001) 1.3V 10% tPHL Figure 20. Suggested PCB Lay-Out 50V dVCM dt 0V VOH = 10% tPLH tPHL tPLH Figure 19. Common Mode Rejection Waveforms VCM 50% OUTPUT, VO (74OL6011) INPUT VCC BUS VCM tr INPUT GND BUS OUTPUT VCC BUS OUTPUT GND BUS CMH 1 6 2 5 3 4 VO = 2.0V (MIN.) DATA IN .1µF .1µF DATA OUT VO = 0.8V (MAX.) VOL CML NOTE 1. The VCCO and VCCI supply voltages to the device must each be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic or solid tantalum capacitor with good high frequency characteristics. Its purpose is to stabilize the operation of the high-gain amplifiers. Failure to provide the bypass will impair the DC and switching properties. The total lead length between capacitor and optocoupler should not exceed 1.5mm. See Fig. 20. 2. Device considered a two-terminal device. Pins 1, 2 and 3 shorted together, and Pins 4, 5 and 6 shorted together. 3. For example, assuming a VCCI of 5.0V, and an ambient temperature of 70°C, the maximum allowable VCCO is 12.1V. DS300204 2/27/01 9 OF 13 www.fairchildsemi.com HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO Package Dimensions (Through Hole) 74OL6000 74OL6001 74OL6010 74OL6011 Package Dimensions (Surface Mount) P IN 1 0.350 (8.89) 0.330 (8.38) ID . 3 0 .2 7 0 ( 6 .8 6 ) 2 PIN 1 ID. 1 0 .2 4 0 ( 6 .1 0 ) 0.270 (6.86) 0.240 (6.10) 0 .3 5 0 ( 8 .8 9 ) 0 .3 3 0 ( 8 .3 8 ) 5 4 6 0 .0 7 0 ( 1 .7 8 ) 0 .0 4 5 ( 1 .1 4 ) 0.300 (7.62) TYP 0.070 (1.78) 0.045 (1.14) S E A T IN G P L A N E 0 .2 0 0 ( 5 .0 8 ) 0 .1 3 5 ( 3 .4 3 ) 0.200 (5.08) 0.165 (4.18) 0.016 (0.41) 0.008 (0.20) 0 .0 2 0 ( 0 .5 1 ) 0 .1 5 4 ( 3 .9 0 ) 0.020 (0.51) MIN M IN 0 .1 0 0 ( 2 .5 4 ) 0.022 (0.56) 0.016 (0.41) 0 .0 1 6 ( 0 .4 0 ) 0 .0 0 8 ( 0 .2 0 ) 0.100 (2.54) TYP 0 .3 0 0 ( 7 .6 2 ) 0 .0 2 2 ( 0 .5 6 ) 0 ° to 1 5 ° 0.016 (0.40) MIN 0.315 (8.00) MIN 0.405 (10.30) MAX TYP 0 .0 1 6 ( 0 .4 1 ) 0 .1 0 0 ( 2 .5 4 ) Lead Coplanarity : 0.004 (0.10) MAX TYP Package Dimensions (0.4”Lead Spacing) Recommended Pad Layout for Surface Mount Leadform 0.070 (1.78) 0 .2 7 0 ( 6 .8 6 ) 0 .2 4 0 ( 6 .1 0 ) 0.060 (1.52) 0 .3 5 0 ( 8 .8 9 ) 0 .3 3 0 ( 8 .3 8 ) 0.415 (10.54) 0 .0 7 0 ( 1 .7 8 ) 0 .0 4 5 ( 1 .1 4 ) 0.100 (2.54) 0.295 (7.49) 0 .2 0 0 ( 5 .0 8 ) 0.030 (0.76) 0 .1 3 5 ( 3 .4 3 ) S E A T IN G P L A N E 0 .1 5 4 ( 3 .9 0 ) 0 .0 1 6 ( 0 .4 0 ) 0 .0 0 4 ( 0 .1 0 ) 0 .1 0 0 ( 2 .5 4 ) 0 .0 0 8 ( 0 .2 0 ) M IN 0 ° to 1 5 ° 0 .0 2 2 ( 0 .5 6 ) 0 .0 1 6 ( 0 .4 1 ) 0 .4 0 0 ( 1 0 .1 6 ) 0 .1 0 0 ( 2 .5 4 ) T Y P TYP NOTE All dimensions are in inches (millimeters) www.fairchildsemi.com 10 OF 13 2/27/01 DS300204 HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS LSTTL TO TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER 74OL6000 74OL6001 74OL6010 74OL6011 ORDERING INFORMATION Order Entry Identifier Option Description S .S Surface Mount Lead Bend SD .SD Surface Mount; Tape and reel W .W 0.4 Lead Spacing 300 .300 VDE 0884 300W .300W VDE 0884, 0.4 Lead Spacing 3S .3S VDE 0884, Surface Mount 3SD .3SD VDE 0884, Surface Mount, Tape & Reel QT Carrier Tape Specifications (D Taping Orientation) 12.0 ± 0.1 4.85 ± 0.20 0.30 ± 0.05 4.0 ± 0.1 4.0 ± 0.1 Ø1.55 ± 0.05 1.75 ± 0.10 7.5 ± 0.1 13.2 ± 0.2 9.55 ± 0.20 0.1 MAX 10.30 ± 0.20 16.0 ± 0.3 Ø1.6 ± 0.1 User Direction of Feed NOTE All dimensions are millimeters DS300204 2/27/01 11 OF 13 www.fairchildsemi.com HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO 74OL6000 74OL6001 74OL6010 74OL6011 APPLICATION Local area data communication systems sion 75Ω CATV coax cable with data taps nations. Traces 8-11 in Figure C illustrate can greately improve their noise immunity at 250 ft. intervals. The 74OL6001s func- Eye Pattern as seen at the output of a by including OPOTOLOGIC gates in the tion as bridged receivers, and as many as 74LS04 logic gate. The data quality is well design. 30 receivers could be placed along the line preserved in that only a 30% Eye closure is with minimal signal degradation. The com- seen at the receiver located 1000 ft. from The Optologic input amplifier offers the fea- munication cable is terminated with a single the transmitter. ture of very high input impedance that per- 75Ω load at the far end of the line. mits their use as bridged line receivers. The The data communication system is com- system show above illustrates an optically Signal quality Eye Pattern is shown in pletely optically isolated from all of the ter- isolated transmitter and multidrop receiver Figures A, B and C with a 10MBaud NRZ minal equipments. Power for the transmit- system. The network uses a 74OL6000 Psuedo-Random Sequence (PRS). Traces ter (VCCO) and receiver (VCCI) is taken from and buffer (Figure D) to isolate the trans- 1-3 in Figure A describes the transmitter an isolated power supply and distributed mitter and drive the 75Ω coax cable. This section. Traces 4-7 in Figure B show the through a drain or messenger wire. application uses a 1000 ft. aerial suspen- output of the four Optologic bridged termi- Figure. C Figure. B Figure. A HORIZONTAL = 20 ns/DIV VERTICAL = 2 V/DIV HORIZONTAL = 20 ns/DIV VERTICAL = 2 V/DIV 42-11 HORIZONTAL = 20 ns/DIV VERTICAL = 2 V/DIV 42-12,02 42-13/03 1 0 0 0 F T . 3 2 1 P R S G 7 5 0 .1 m W 1 0 0 n s B IT F T E R M IN A IO N 10 W IN T E R V A L 1 .1 K W 2 5 0 F T . 7 4 O L 6 0 0 0 2 5 0 F T . 2 5 0 F T . 2 5 0 F T . B U F F E R 2N 4252 100 m F 7 4 4 O L 6 0 0 1 7 4 O L 6 0 0 1 7 4 5 O L 6 0 0 1 7 4 6 O L 6 0 0 1 7 2N 4252 L S 0 4 1 .1 K L S 0 4 L S 0 4 L S 0 4 W 8 9 1 0 1 1 2N 2222 1 K W A L L D IO D E S 1N 6263 Figure. D Buffer www.fairchildsemi.com 12 OF 13 2/27/01 DS300204 HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS LSTTL TO TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER 74OL6000 74OL6001 74OL6010 74OL6011 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body,or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in labeling, can be reasonably expected to result in a significant injury of the user. DS300204 2/27/01 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 13 OF 13 www.fairchildsemi.com