Genesys Logic, Inc. GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution Datasheet Revision 1.00 Aug. 16, 2006 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution Copyright: Copyright © 2006 Genesys Logic Incorporated. All rights reserved. No part of the materials may be reproduced in any form or by any means without prior written consent of Genesys Logic Inc.. Disclaimer: ALL MATERIALS ARE PROVIDED “AS IS” WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF GENESYS LOGIC INC.. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR EXPRESS, OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY, INCLUDING, WITHOUT LIMITATION, THE X-D PICTURE CARDTM LICENSE. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING FROM LOSS OF INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS MAY CONTAIN ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE MATERIALS OR TO THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE. Trademarks: is a registered trademark of Genesys Logic, Inc. All trademarks are the properties of their respective owners. Office: Genesys Logic, Inc. 12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel: (886-2) 8913-1888 Fax: (886-2) 6629-6168 http ://www.genesyslogic.com ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 2 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution Revision History Revision Date Description 0.95 09/02/2005 First formal release 0.96 1.Modify Block Diagram,Ch1 2.Add “56-Pin QFN Package” 3.Add “USB CONTROLLER STRUCTURE”,Ch3 10/18/2005 4.Add QFN-56 Package Diagram,Ch4.2 5.Modify “PAD/PIN Descruption”,Ch4.6 6.Add “D.C.Characteristics”, Ch5.3 1.00 08/16/2006 1. Remove 54-Pin LGA Package 2. Add 54-Pin VFBGA Package ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 3 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution TABLE OF CONTENTS CHAPTER 1 GENERAL DESCRIPTION................................................. 7 1.1 USB INTERFACE...................................................................................... 8 1.2 CARD INTERFACE .................................................................................. 8 1.3 FLASH ACCESS INTERFACE ..................................................................... 8 1.4 CONTROL LOGIC..................................................................................... 8 1.5 EMBEDDED CPU ..................................................................................... 8 CHAPTER 2 FEATURES ........................................................................... 9 2.1 USB 2.0 INTERFACE ................................................................................ 9 2.2 SD HOST INTERFACE .............................................................................. 9 2.3 MMC HOST INTERFACE ......................................................................... 9 2.4 FLASH MEMORY INTERFACE ................................................................ 10 2.5 MICRO CONTROLLER AND ANALOG SYSTEM........................................ 10 2.6 PRODUCT PACKAGES ............................................................................ 10 2.7 TECHNOLOGY ....................................................................................... 10 2.8 MANUFACTURE ..................................................................................... 10 CHAPTER 3 PIN ASSIGNMENT ............................................................ 11 3.1 FUNCTION DESCRIPTION ....................................................................... 11 3.1.1 USB specification compliance ...................................................... 11 3.1.2 Integrated USB building blocks................................................... 11 3.1.3 Embedded 8051 micro-controller ................................................ 11 3.1.4 3.3V power source ........................................................................ 11 3.1.5 Memory Stick TM interface......................................................... 11 3.1.6 Secure Digital (SD) and Multi Media Card (MMC)................... 11 3.1.7 High efficient hardware engine.................................................... 12 3.1.8 Inter-Media transfer capability ................................................... 12 3.2 BLOCK DIAGRAM................................................................................... 12 3.2.1 UTM .............................................................................................. 12 3.2.2 SIE................................................................................................. 12 3.2.3 EPFIFO......................................................................................... 13 3.2.4 MHE.............................................................................................. 13 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 4 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution CHAPTER 4 COMBO STRUCTURE ...................................................... 14 4.1 DIE DIAGRAM........................................................................................ 14 4.2 DIE TO QFN -56 PACKAGE DIAGRAM ................................................... 15 4.3 QFN -56 PACKAGE TOP VIEW .............................................................. 16 4.4 DIE TO VFBGA -54 PACKAGE DIAGRAM.............................................. 17 4.5 VFBGA -54 PACKAGE TOP VIEW......................................................... 18 4.6 PAD/PIN DESCRIPTON ......................................................................... 19 4.6.1 USB Interface ............................................................................... 19 4.6.2 Regulator Interface ...................................................................... 21 4.6.3 Card Interface .............................................................................. 22 4.6.4 Flash Interface .............................................................................. 24 4.6.5 System Interface ........................................................................... 25 4.6.6 Test Interface ................................................................................ 26 4.6.7 Use Flash Interface as USB Test Interface.................................. 27 4.6.8 Use Card Interface as USB Test Interface .................................. 28 CHAPTER 5 ELECTRICAL CHARACTERISTICS.............................. 29 5.1 ABSOLUTE MAXIMUM RATINGS ............................................................ 29 5.2 BUS OPERATING CONDITIONS ............................................................... 29 5.3 D.C. CHARACTERISTICS........................................................................ 29 CHAPTER 6 PACKAGE DIMENSION................................................... 31 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 5 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution LIST OF FIGURES FIGURE 1.1 - GL422/GL423 BLOCK DIAGRAM ................................................................7 FIGURE 3.1 - USB CONTROLLER DIAGRAM ....................................................................12 FIGURE 4.1 - GL422/GL423 DIE DIAGRAM ...................................................................14 FIGURE 4.2 - GL422/GL423 DIE TO QFN-56 PACKAGE DIAGRAM................................15 FIGURE 4.3 - GL422/GL423 QFN 56 PACKAGE TOP VIEW ...........................................16 FIGURE 4.4 - GL422/GL423 VFBGA54 PACKAGE DIAGRAM .......................................17 FIGURE 4.5 - GL422/GL423 VFBGA 54 PACKAGE TOP VIEW ......................................18 FIGURE 6.1 – GL422/GL423 56 PIN QFN PACKAGE......................................................31 FIGURE 6.2 – GL422/GL423 54 PIN VFBGA PACKAGE ................................................32 LIST OF TABLES TABLE 4.1- USB INTERFACE ..........................................................................................19 TABLE 4.2 – REGULATOR INTERFACE ............................................................................21 TABLE 4.3 – CARD INTERFAC .........................................................................................22 TABLE 4.4 – FLASH INTERFACE .....................................................................................24 TABLE 4.5 – SYSTEM INTERFACE ...................................................................................25 TABLE 4.6 – TEST INTERFACE ........................................................................................26 TABLE 4.7 –USE FLASH INTERFACE AS USB TEST INTERFACE ......................................27 TABLE 4.8 – USE CARD INTERFACE AS USB TEST INTERFACE.......................................28 TABLE 5.1 – ABSOLUTE MAXIMUM RATINGS .................................................................29 TABLE 5.2 – BUS OPERATING CONDITIONS ....................................................................29 TABLE 5.3 – D.C. CHARACTERISTICS.............................................................................29 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 6 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution CHAPTER 1 GENERAL DESCRIPTION Genesys Logic’s GL422/GL423 controller is an single-chip controllers support both USB2.0 and MMC4.0/SD1.1 specifications. While USB controller and SD/MMC card controller are integrated as a combo-function single chip, this chip provides an enhanced combo solution of USB2.0 and SD/MMC card. GL422/GL423 is designed based on USB2.0 and MMC4.0/SD1.1 specification. Its unique RAM based firmware strategy provides flexibility for fast compatibility and performance improvement, therefore, give customers strong support to win in today’s fast-changing market. GL422/GL423 manages interface protocol, data storage and retrieval, error detection and correction, defect handling and diagnostic, as well as power management. With a built-in flash management algorithm, GL422/GL423 is applicable for most types of flash in the market: SAMSUNG, MICRON, ST, TOSHIBA, HYNIX and RENESAS. GL422/GL423 is packaged QFN-56 and VFBGA-54. Both die and QFN/VFBGA package are available and completely meet SD and MMC memory card mechanical thickness requirement. The pin assignment that fits to card sockets provides easy PCB layout. GL422/GL423 die has a dual channel flash access interface, which remarkably speed up read/write performance. QFN-56 packaged GL422/GL423 supports SD1.1 only. VFBGA-54 packaged GL422/GL423 supports both SD1.1 and MMC4.0. Figure 1.1 is the block diagram of VFBGA422/GL423. USB Interface USB PHY USB Controller Flash1 Interface Control Logic CARD Controller Flash Access IF Flash2 Interface CARD Interface GL422/GL423 Figure 1.1 - GL422/GL423 Block Diagram ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 7 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 1.1 USB Interface The USB controller, complied with USB2.0 and USB1.1 specification, explains commands from USB host and transfers data as a USB application. 1.2 CARD Interface The card controller, complied with SD1.1/MMC4.0 specification, explains commands from SD/MMC host and transfers data between SD/MMC host and flash. 1.3 Flash Access Interface The flash access interface communicates with CPU. It also manages two channels of flash, based on flash commands. Moreover, it implements defect processing, ECC, and address mapping, etc. 1.4 Control Logic The control logic module switches the command and data between the USB host and SD/MMC host. By this module, the chip operates in different mode. 1.5 Embedded CPU Embedded CPU performs arithmetic and logical operations. In addition, it extracts instruction from ROM and SRAM, decodes and executes them. It also manages control and status signals between flash access interface and itself. ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 8 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution CHAPTER 2 FEATURES 2.1 USB 2.0 Interface • Complies with Universal Serial Bus Specification Version 2.0 • Complies with USB Mass Storage Class Specification Version 1.0 • Integrated USB 2.0 Transceiver Macro-cell (UTM), Serial Interface Engine (SIE), Build-in power-on reset (POR) and low-voltage detector (LVD) • Supports one USB device address and up to 5 endpoints, including one control, one interrupt and 2 bulk IN/OUT endpoint pairs • Embedded 8051 micro-controller operates at 60MHz clock • 64 / 512 bytes Data Payload for full / high speed Bulk Endpoint • Supports USB 2.0 TEST mode features 2.2 SD Host Interface • Complies with SD Specification Version 1.1 • Backward compatible with SD Specification, Version 1.0 • Supports SPI mode and CPRM functions • Supports clock rate up to 25 MHZ for SD1.0 • Supports clock rate up to 52MHz for SD1.1 • Buffers for multi-block flash memory programming • DMA operation between buffers and flash memory • Supports automatic CRC16 generation and verification on DATA 3-0 2.3 MMC Host Interface • Complies with MultiMediaCard System Specification, Version 4.0 • Backward compatible with MultiMediaCard System Specification, Version 3.3 • Supports SPI mode and CPRM functions • Supports clock rate up to 25 MHZ for MMC 3.3 • Supports clock rate up to 52MHz for MMC 4.0 • Buffers for multi-block flash memory programming • DMA operation between buffers and flash memory • Supports automatic CRC16 generation and verification on DATA 7-0 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 9 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 2.4 Flash Memory Interface • Direct interface to NAND/AND flash chips (SAMSUNG / TOSHIBA / HITACHI / RENESAS / MICRON / ST / HYNIX) • Direct interface to NOR/OR Flash chips (die only) • Supports dual-channel, 16 bits flash (die only) • Drives up to 4 flash memory chips, respectively (die only) • Supports 64 Mb / 128 Mb / 256 Mb / 512 Mb /1Gb / 2Gb / 4Gb / 8Gb flash chips • Embedded firmware support for flash file system (FTL) • Built-in flash management algorithm • Powerful ECC for error detection and correction up to 6 bytes per 512 bytes 2.5 Micro Controller and Analog System • RISC core with fast speed and less code size • Flexibility to update system code • Ability to add customers’ own feature 2.6 Product Packages • 56-pin QFN package • 54-pin VFBGA package 2.7 Technology • 0.18um process 2.8 Manufacture • Easy firmware development environment • Supports firmware upgrade tool via PC ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 10 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution CHAPTER 3 PIN ASSIGNMENT 3.1 Function description 3.1.1 USB specification compliance • Confirms to USB 480Mbps Specification, version 2.0. • Backward compatible with USB 12Mbps Specification, version 1.1. • Support one USB device address and up to 5 endpoints, including one control, one interrupt and 2 bulk IN / OUT endpoint pairs 3.1.2 Integrated USB building blocks • USB2.0 transceiver macro (UTM), Serial Interface Engine (SIE), Build-in power-on reset (POR) and low-voltage detector (LVD) 3.1.3 Embedded 8051 micro-controller • Operates at 60 MHz clock, 12 clocks per instruction cycle • Embedded 48K Byte mask ROM and internal 256 byte SRAM • Embedded 4K Byte external SRAM 3.1.4 3.3V power source 3.1.5 Memory Stick TM interface • Compliant with Memory Stick interface specification • Hardware support BS/SDIO/SCLK signals • Support INS signal • Support automatic CRC16 generation and verification 3.1.6 Secure Digital (SD) and Multi Media Card (MMC) • Compliant with Secure Digital / MMC interface specification • Support both SD / MMC mode access CLK/CMD/DAT0/DAT1/DAT2/DAT3 • Command transmit and response receive can be enabled separately • Automatic CRC7 generation for command and CRC7 verification for response on CMD • Support automatic CRC16 generation and verification on DAT3-0 • In addition to full packet transaction, optional single byte / bit operation on both CMD and DAT line / lines • Process data in block or byte ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 11 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 3.1.7 High efficient hardware engine • Automatic data read / write with card by hardware engine • Easier firmware development • Media interface signals output low automatically when suspend 3.1.8 Inter-Media transfer capability • Support copy data between flash cards or within same flash card 3.2 Block diagram MHE EPFIFO MHE control EP0 FIFO (64B) SIE MCFIFO (32B) MS MIF EP3 FIFO (64B) BULK FIFO (512B*2) MSP MIF SD MIF Register SIE/ FIFO/ MHE control 8051 core SRAM 256B LUT Mask ROM (48KB) UTM LUT 4KB Figure 3.1 - USB Controller diagram 3.2.1 UTM USB2.0 Transceiver Macro 3.2.2 SIE Serial Interface Engine ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 12 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 3.2.3 EPFIFO Endpoint FIFO: it includes Control FIFO (FIFO0), interrupt FIFO (FIFO3), Bulk In/Out FIFO (BULKFIFO) 3.2.3.1 Control FIFO FIFO of control endpoint 0. It is 64-byte FIFO, and it is used for endpoint 0 data transfer. 3.2.3.2 Interrupt FIFO 64-byte-depth FIFO of endpoint 3 for status interrupt. 3.2.3.3 Bulk In/Out FIFO It can be in the TX mode or RX mode: • It contains ping-pong FIFO (512 bytes each bank) for transmit/receive data continuously. • It can be directly accessed by micro controller • Support SIE won’t transmit data filled before micro controller check data integrity complete. • It can be used to copy data block from source to destination in the same card or from one card to other card. 3.2.4 MHE It contains 3 MIF (Media Interface), control and MCFIFO 3.2.4.1 MIFs • SD / MMC MIF • Memory Stick MIF • Memory Stick-PRO MIF 3.2.4.2 MCFIFO 32-byte FIFO shared by Memory Stick, Memory Stick-PRO, SD/MMC MIF. • Memory Stick and Memory Stick-PRO MIF can use MCFIFO as command FIFO. • SD/MMC MIF use MCFIFO for command and response. ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 13 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution CHAPTER 4 COMBO STRUCTURE 73 72 71 70 69 68 67 66 65 64 63 62 61 60 CGND PGND PAD_W P_ B CVDD18 PAD_W E_ B PAD_AL E PAD_CL E PAD_CE1 _B PAD_CE0 _B PAD_RE_ B PAD_BUS Y_B PAD_DA7 PAD_DA6 PAD_A2 3 DA6 74 PAD_OSC _E DA7 75 PAD_rst_o RE_ 76 PAD_rst_B BUSY_ 77 VCC33 CE0_ 78 PAD_A0 ALE 79 PAD_A1 CLE 80 PAD_A2 CE1_ 81 PAD_A3 W E_ 82 PAD_A4 W P_ 83 PAD_A5 CVDD18 84 PAD_A6 GND Rst_ 85 PAD_A7 OSC_E 86 PAD_A1 3 VCC33 4.1 Die Diagram Digital Power Ring(1.8V/3.3V/GND) REXT2 87 REXT2 REXT1 88 REXT1 89 OUT2 90 OUT2 91 OUT1 92 VIN PAD_A22 59 93 VIN PAD_A21 58 94 VIN PAD_A20 57 95 GND PAD_A19 56 PAD_A18 55 V18OUT AVDD GND REGULATOR PAD_A17 54 AVDD1 PAD_A16 53 98 RREF CGND 52 99 AGND2 PGND 51 100 AGND1 PAD_DA5 50 DA5 DM 101 DM VCC33 49 VCC33 DP 102 DP PAD_DA4 48 DA4 AVDD 103 AVDD3 PAD_DA3 47 DA3 PAD_DA2 46 DA2 PAD_DA1 45 DA1 PAD_DA0 44 DA0 PAD_T3 43 T3 PAD_T2 42 T2 T1 RREF AGND 104 AGND AGND3 Digita l Powe r Ring(1.8V/3.3V/GN D) AVDD2 97 Digital Po wer Ring(1.8V/3.3V/GND) 96 AVDD SD/MMC CONTROLLER GND 105 VBUS 106 DGND2 107 DGND1 108 DVDD1 AGND 109 AVSS2 PAD_T1 41 XI 110 XI PAD_T0 40 XO 111 XO PAD_HDATA1 39 AVDD 112 AVDD2 PAD_UDATA1 38 CUTCELL PAD_HDATA7 37 VDD 113 AVDD2 PAD_UDATA7 36 114 AVSS2 PAD_HDATA6 35 115 AVSS1 PAD_UDATA6 34 116 AVDD1 PAD_T5 33 PAD_T4 32 T4 117 CVDD18 CVDD18 31 CVDD18 118 PAD_SCLK 119 PAD_SDATA 120 PAD_A15 121 PAD_A14 GND AGND USB CVDD18 T0 HDATA1 HDATA7 HDATA6 T5 PAD_U DATA0 PAD_H DATA0 29 30 HDATA0 VCC33 PAD _HCLK 28 26 27 CGND PAD _UCLK 25 VCC33 PGND 24 HCLK PAD_H DATA5 GND P AD_HCMDy PAD_U DATA5 23 P AD_HCMDx 20 22 PAD_UCMD 19 21 PAD_H DATA4 18 HDATA5 PAD_U DATA4 17 HCMD PAD_H DATA3 16 UCMD PAD_U DATA3 15 HDATA4 PAD_H DATA2 14 HDATA3 PAD_U DATA2 13 HDATA2 PAD_OSCO 12 OSCO PAD_MCLK 11 MCLK VCC33 PAD_USB _ACTV 9 10 VCC33 PAD_ Prt_B 8 USB_ACT PA D_T6 7 PA D_A8 5 T6 PA D_A9 4 PA D_T7 PAD_ A10 3 6 PAD_ A11 2 T7 PAD_ A12 1 Digital Power Ring(1.8V/3.3V/GND) Figure 4.1 - GL422/GL423 Die Diagram ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 14 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 29 30 31 32 33 34 35 36 37 38 39 40 41 42 4.2 Die to QFN -56 Package Diagram 28 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 PAD_rst_o PAD_OSC_E CGND PGND PAD_WP_B CVDD18 PAD_WE_B PAD_ALE PAD_CLE PAD_CE1_B PAD_CE0_B PAD_RE_B PAD_BUSY_B PAD_DA7 PAD_DA6 PAD_A23 80 PAD_A2 PAD_rst_B 81 PAD_A3 78 82 PAD_A4 VCC33 83 PAD_A5 79 84 PAD_A6 PAD_A0 85 PAD_A7 PAD_A1 86 PAD_A13 27 Digital Power Ring(1.8V/3.3V/GND) 43 44 45 87 REXT2 88 REXT1 89 OUT2 90 OUT2 91 OUT1 92 VIN PAD_A22 59 93 VIN PAD_A21 58 94 VIN PAD_A20 57 95 GND PAD_A19 56 PAD_A18 55 REGULATOR PAD_A17 54 97 AVDD1 PAD_A16 53 98 RREF CGND 52 99 AGND2 PGND 51 100 AGND1 PAD_DA5 50 25 49 101 DM VCC33 49 24 50 102 DP PAD_DA4 48 23 51 103 AVDD3 PAD_DA3 47 22 PAD_DA2 46 21 PAD_DA1 45 20 PAD_DA0 44 19 PAD_T3 43 18 17 47 48 52 Digital Power Ring(1.8V/3.3V/GND) AVDD2 Digital Power Ring(1.8V/3.3V/GND) 96 46 SD/MMC CONTROLLER 104 AGND3 105 VBUS 106 DGND2 107 DGND1 108 DVDD1 PAD_T2 42 109 AVSS2 PAD_T1 41 54 110 XI PAD_T0 40 55 111 XO PAD_HDATA1 39 112 AVDD2 PAD_UDATA1 38 CUTCELL PAD_HDATA7 37 113 AVDD2 PAD_UDATA7 36 114 AVSS2 PAD_HDATA6 35 115 AVSS1 PAD_UDATA6 34 116 AVDD1 PAD_T5 33 PAD_T4 32 CVDD18 31 53 56 117 CVDD18 118 PAD_SCLK 119 PAD_SDATA 120 PAD_A15 121 PAD_A14 USB 26 16 15 PAD_HDATA0 29 30 14 VCC33 PAD_UDATA0 28 13 PAD_HCLK 27 12 PAD_UCLK 26 CGND 25 11 PGND 24 10 PAD_HDATA5 PAD_HCMDx 20 23 PAD_UCMD 19 PAD_UDATA5 PAD_HDATA4 18 22 PAD_UDATA4 17 PAD_HCMDy PAD_HDATA3 16 21 PAD_UDATA3 15 9 PAD_HDATA2 14 8 PAD_UDATA2 13 7 PAD_OSCO 12 6 PAD_MCLK 8 11 PAD_T6 PAD_Prt_B 7 4 5 PAD_T7 6 VCC33 PAD_A8 5 10 PAD_A9 4 4 PAD_A10 3 PAD_USB_ACTV PAD_A11 2 9 PAD_A12 1 3 2 1 Digital Power Ring(1.8V/3.3V/GND) Figure 4.2 - GL422/GL423 Die to QFN-56 Package Diagram ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 15 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 56 55 54 53 52 51 50 49 48 47 46 45 44 43 AVDD XO XI AGND AGND AVDD DP DM AGND RREF AVDD GND AVDD V18OUT 4.3 QFN -56 Package Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 GL422/GL423 56-Pin Package (Top View) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 REXT1 REXT2 VCC33 rst_ OSC_E GND CVDD18 WE_ ALE CLE CE1_ CE0_ RE_ BUSY_ CVDD18 HDATA1 T2 T3 DA0 DA1 DA2 DA3 DA4 VCC33 DA5 GND DA6 DA7 15 16 17 18 19 20 21 22 23 24 25 26 27 28 AGND CVDD18 USB_ACT VCC33 MCLK HDATA2 HDATA3 UCMD HCMD GND UCLK HCLK VCC33 HDATA0 Figure 4.3 - GL422/GL423 QFN 56 Package Top View ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 16 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 64 63 62 61 60 PAD_RE_B PAD_BUSY_B PAD_DA7 PAD_DA6 PAD_A23 B6 32 65 PAD_CE0_B A6 51 66 PAD_CE1_B B5 67 PAD_CLE C5 32 68 PAD_ALE B4 69 PAD_WE_B C4 70 CVDD18 A5 71 PAD_WP_B F3 72 PGND A4 73 CGND 66 B3 74 PAD_OSC_E D4 75 PAD_rst_o E4 76 A3 77 80 PAD_A2 PAD_rst_B 81 PAD_A3 78 82 PAD_A4 VCC33 83 PAD_A5 79 84 PAD_A6 PAD_A0 85 PAD_A7 PAD_A1 86 PAD_A13 66 F2 A2 4.4 Die to VFBGA -54 Package Diagram Digital Power Ring(1.8V/3.3V/GND) A1 87 REXT2 B1 88 REXT1 89 OUT2 90 OUT2 91 OUT1 92 VIN PAD_A22 59 93 VIN PAD_A21 58 94 VIN PAD_A20 57 95 GND PAD_A19 56 PAD_A18 55 E4 C2 C3 96 AVDD2 PAD_A17 54 97 AVDD1 PAD_A16 53 CGND 52 PGND 51 PAD_DA5 50 C6 VCC33 49 G3 PAD_DA4 48 D5 PAD_DA3 47 E5 PAD_DA2 46 D6 PAD_DA1 45 F4 PAD_DA0 44 G4 PAD_T3 43 F5 PAD_T2 42 E6 98 RREF 99 AGND2 100 AGND1 D1 101 DM D2 102 DP D3 103 AVDD3 E3 104 AGND3 105 VBUS 106 DGND2 107 DGND1 108 DVDD1 E3 E3 Digital Power Ring(1.8V/3.3V/GND) C1 REGULATOR Digital Power Ring(1.8V/3.3V/GND) B2 SD/MMC CONTROLLER 109 AVSS2 PAD_T1 41 E1 110 XI PAD_T0 40 E2 111 XO PAD_HDATA1 39 112 AVDD2 PAD_UDATA1 38 CUTCELL PAD_HDATA7 37 113 AVDD2 PAD_UDATA7 36 114 AVSS2 PAD_HDATA6 35 115 AVSS1 PAD_UDATA6 34 116 AVDD1 PAD_T5 33 PAD_T4 32 117 CVDD18 CVDD18 31 118 PAD_SCLK 119 PAD_SDATA 120 PAD_A15 121 PAD_A14 F1 E3 USB H1 E4 F6 G5 G6 H6 VCC33 PAD_UDATA0 PAD_HDATA0 28 29 30 J6 G3 PAD_HCLK 27 J5 PAD_UCLK 26 H5 PGND 24 CGND PAD_HDATA5 23 25 E4 PAD_UDATA5 22 H4 PAD_HCMDx 20 PAD_HCMDy PAD_UCMD 19 21 PAD_HDATA4 18 J4 H3 PAD_UDATA4 17 J3 PAD_UDATA3 15 PAD_HDATA3 PAD_HDATA2 14 16 PAD_UDATA2 13 G2 PAD_OSCO 12 H2 PAD_MCLK 11 PAD_Prt_B 8 J2 PAD_T6 7 VCC33 PAD_T7 6 10 PAD_A8 5 G1 PAD_A9 4 PAD_USB_ACTV PAD_A10 3 9 PAD_A11 2 J1 PAD_A12 1 Digital Power Ring(1.8V/3.3V/GND) Figure 4.4 - GL422/GL423 VFBGA54 Package Diagram ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 17 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 4.5 VFBGA -54 Package Top View 1 A 6 REXT2 RST_B OSC_E WE_B CLE DA7 B REXT1 OUT2 WP_B CE1_B RE_B DA6 C VIN AVDD1 RREF CE0_B BUSY_B DA5 D DM DP AVDD CVDD18 DA4 DA2 E X1 X2 AGND DGND AVSS VSS VSSD GND DA3 T2 F VDDX VDD33 VDD33 ALE DA1 T3 HDATA1 G VDD33 HDATA3 VCC33 DA0 HDATA7 HDATA6 H CVDD18 HDATA2 HCMDY HDATA5 UCLK CVDD18 J USB_AC TV MCLK DATA4 HCMDX HCLK HDATA0 Figure 4.5 - GL422/GL423 VFBGA 54 Package Top View ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 18 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 4.6 PAD/PIN Descripton 4.6.1 USB Interface Table 4.1- USB Interface QFN56 Pin# 46 VFBG A54 Pin# C2 Pin Name Pad# Pad Name Type 96 AVDD2 P Description Analog 3.3V power (Double Bonding) AVDD Analog 3.3V power 47 C3 RREF 97 AVDD1 P 98 RREF A (Double Bonding) Reference resistor, normal 680ohm (1%) between RREF and GND 99 48 E3 AGND2 P Analog ground (Double Bonding) AGND 100 AGND1 P Analog ground (Double Bonding) 49 D1 DM 101 DM B USB D- 50 D2 DP 102 DP B USB D+ 51 D3 AVDD 103 AVDD3 P Analog 3.3V power 52 E3 AGND 104 AGND3 P Analog ground NC NC 105 VBUS P (No Bonding) 53 E3 AGND 106 DGND2 P Digital ground. (Tri-bonding) 53 E3 AGND 107 DGND1 P Digital ground. (Tri-bonding) NC NC 108 DVDD1 P Digital power (No Bonding) Analog ground 53 E3 AGND 109 AVSS2 P 54 E1 XI 110 XI I Crystal driver input 55 E2 XO 111 XO O Crystal driver output 56 F1 AVDD 112 AVDD2 P (Tri-bonding) Analog 3.3V power (Double Bonding) - - - - CUTCELL ©2000-2006 Genesys Logic Inc. - All rights reserved. - (No Bonding) Page 19 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 56 F1 VDD 113 AVDD2 P Analog 3.3V power (Double Bonding) Analog ground 1 E3 114 AVSS2 P 115 AVSS1 P (Double Bonding) AGND Analog ground (Double Bonding) 116 2 H1 AVDD1 P 1.8V power supply (Double Bonding) CVDD18 117 CVDD18 P 1.8V power supply (Double Bonding) ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 20 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 4.6.2 Regulator Interface Table 4.2 – Regulator Interface QFN56 Pin# VFBG A54 Pin# Pin Name Pad# Pad Name Type NC NC 91 OUT1 O B2 1.8V output (Max.40mA) (No Bonding) 89 43 Description OUT2 O 1.8V output (Max.100mA) (Double Bonding) V18OUT 90 OUT2 O Regulator 1.8V output (Double Bonding) 92 VIN P Analog 3.3V power (Tri-bonding ) 44 C1 AVDD 93 VIN P Analog 3.3V power (Tri-bonding ) 94 VIN P Analog 3.3V power (Tri-bonding ) 45 E4 GND 95 GND P Analog ground 42 B1 REXT1 88 REXT1 A External Resistor pad 41 A1 REXT2 87 REXT2 A External Resistor pad ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 21 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 4.6.3 Card Interface Table 4.3 – Card Interface QFN56 Pin# VFBGA 54 Pin# Pin Name Pad# Pad Name Type 11 H5 UCLK 26 PAD_UCLK B Description Controller clock signal from USB reader to card (rising edge) 12 J5 HCLK 27 PAD_HCLK B Controller clock signal from HOST Only to card (rising edge) SD/MMC mode: HCMD from/to 19 PAD_UCMD B USB reader SPI mode: Data-in signal from USB reader(Double Bonding) 8 J4 UCMD SD/MMC mode: HCMD from/to HOST 20 PAD_HCMDx B SPI mode: Data-in signal from HOST (Double Bonding) SD/MMC mode: HCMD from/to 9 H3 HCMD 21 PAD_HCMDy B HOST SPI mode: Data-in signal from HOST SD/MMC mode: HDATA0 from/to USB reader 29 PAD_UDATA0 B SPI mode: Data-out signal to USB reader 14 J6 (Double Bonding) HDATA0 SD/MMC mode: HDATA0 from/to 30 PAD_HDATA0 B HOST. SPI mode: Data-out signal to HOST (Double Bonding) SD/MMC mode: HDATA1 from/to 16 F6 HDATA1 38 PAD_UDATA1 B USB reader. SPI mode: not connected (Double Bonding) ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 22 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution SD/MMC mode: HDATA1 from/to 39 PAD_HDATA1 B HOST. SPI mode: not connected (Double Bonding) SD/MMC mode: HDATA2 from/to USB reader. 13 PAD_UDATA2 B SPI mode: not connected (Double Bonding) 6 H2 HDATA2 SD/MMC mode: HDATA2 from/to 14 PAD_HDATA2 B HOST. SPI mode: not connected (Double Bonding) SD/MMC mode: HDATA3 from/to 15 PAD_UDATA3 B USB reader. SPI mode: CS signal 7 G2 (Double Bonding) HDATA3 SD/MMC mode: HDATA3 from/to 16 PAD_HDATA3 B HOST. SPI mode: CS signal (Double Bonding) MMC mode: HDATA4 from/to USB 17 NC PAD_UDATA4 B reader. (Double Bonding) J3 MMC mode: HDATA4 from/to 18 PAD_HDATA4 B HOST. (Double Bonding) MMC mode: HDATA5 from/to USB 22 PAD_UDATA5 B reader. (Double Bonding) NC H4 MMC mode: HDATA5 from/to 23 PAD_HDATA5 B HOST. (Double Bonding) MMC mode: HDATA6 from/to USB NC G6 34 PAD_UDATA6 B reader. (Double Bonding) ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 23 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution MMC mode: HDATA6 from/to 35 PAD_HDATA6 B HOST. (Double Bonding) MMC mode: HDATA7 from/to USB 36 PAD_UDATA7 B reader. (Double Bonding) NC G5 MMC mode: HDATA7 from/to 37 PAD_HDATA7 B HOST. (Double Bonding) 4.6.4 Flash Interface The flash interface is used to access AND/NAND flash, defined as Table 4.4. It is also shared with USB test interface, refers to Table 4.7. Table 4.4 – Flash Interface QFN56 Pin# VFBGA 54 Pin# Pin Name Pad# Pad Name Type 31 C4 CE0_ 65 PAD_CE0_B B Description ‘0’ for FLASH chip 0 to select active (low-active). 32 B4 CE1_ 66 PAD_CE1_B B ‘0’ for FLASH chip 1 to select active (low-active). 33 A5 CLE 67 PAD_CLE B FLASH command latch enable 34 F3 ALE 68 PAD_ALE B FLASH address latch enable 30 B5 RE_ 64 PAD_RE_B B FLASH read enable (low active) 35 A4 WE_ 69 PAD_WE_B B FLASH write enable (low active) 29 C5 BUSY_ 63 PAD_BUSY_B B FLASH ready when high, busy when low. NC B3 WP_ 71 PAD_WP_B B FLASH write protect (low active) 19 G4 DA0 44 PAD_DA0 B FLASH bus bit0 20 F4 DA1 45 PAD_DA1 B FLASH bus bit1 21 D6 DA2 46 PAD_DA2 B FLASH bus bit2 22 E5 DA3 47 PAD_DA3 B FLASH bus bit3 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 24 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 23 D5 DA4 48 PAD_DA4 B FLASH bus bit4 25 C6 DA5 50 PAD_DA5 B FLASH bus bit5 27 B6 DA6 61 PAD_DA6 B FLASH bus bit6 28 A6 DA7 62 PAD_DA7 B FLASH bus bit7 4.6.5 System Interface Table 4.5 – System Interface QFN56 Pin# 39 VFBGA 54 Pin# A2 Pin Name Pad# Pad Name Type 76 PAD_rst_B I Description Power-on reset input, low active (Double Bonding) rst_ 75 PAD_rst_o O Power-on reset output (Double Bonding) 3 J1 USB_ACT 9 PAD_USB_A B USB active CTV NC NC NC NC NC NC 8 118 119 PAD_Prt_B B Protect (No Bonding) PAD_SCLK B Test port CLK. (No Bonding) PAD_SDATA B Test port Data. (No Bonding) NC NC 12 PAD_OSCO O 5 J2 MCLK 11 PAD_MCLK I Clock output for test Main clock input. (No Bonding) 38 A3 OSC_E 74 PAD_OSC_E I Oscillator enable 40 F2 VCC33 77 VCC33 P Digital 3.3V power supply 24 G3 VCC33 49 VCC33 P Digital 3.3V power supply 13 G3 VCC33 28 VCC33 P Digital 3.3V power supply 4 G1 VCC33 10 VCC33 P Digital 3.3V power supply 36 D4 CVDD18 70 CVDD18 P Digital 1.8V power supply 15 H6 CVDD18 31 CVDD18 P Digital 1.8V power supply ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 25 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 73 37 E4 CGND P Digital Ground (Double Bonding) GND 72 PGND P Digital Ground (Double Bonding) 52 26 E4 CGND P PGND P (Double Bonding) GND 51 Digital Ground Digital Ground (Double Bonding) 25 10 E4 CGND P PGND P (Double Bonding) GND 24 Digital Ground Digital Ground (Double Bonding) 4.6.6 Test Interface Table 4.6 – Test Interface QFN56 Pin# VFBGA 54 Pin# Pin Name Pad# Pad Name Type Description NC NC 40 PAD_T0 B Dual channel flash2 bus bit0 to NC NC 41 PAD_T1 B bit7. (on-chip pulled-up). 17 E6 T2 42 PAD_T2 B When power-on or hardware reset, 18 F5 T3 43 PAD_T3 B T[3:0] is: NC NC 32 PAD_T4 B 4’b0000: USB CPU Test NC NC 33 PAD_T5 B NC NC 7 PAD_T6 B (CPUTST = 1) 4’b0001: USB UTM Scan Mode (UTMSCANM = 1 ) 4’b0010: USB Scan Mode (SCANMOD = 1) NC NC 6 PAD_T7 B 4’b0011: USB UTM Test (UTMTEST = 1) others: SD Controller Test Mode (T[7:4],T[1:0] no bonding) ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 26 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 4.6.7 Use Flash Interface as USB Test Interface This interface is shared with Flash Interface. This is only for testing. In test mode, the flash interface will be used for USB test patterns: Table 4.7 –Use Flash Interface as USB Test Interface Pin Name Pad# Pad Name Type SCAN MOD UTM TEST CE0_ 65 PAD_CE0_B B DO4 TERM DO4 CE1_ 66 PAD_CE1_B B DO7 SUSP DO7 CLE 67 PAD_CLE B OP1 ALE 68 PAD_ALE B OP0 RE_ 64 PAD_RE_B B DO6 RXERR DO6 WE_ 69 PAD_WE_B B DO1 RXV DO1 BUSY_ 63 PAD_BUSY_B B TXVH SCANTEST SCANTE UTM SCANM CPU TEST ST WP_ 71 PAD_WP_B B DA0 44 PAD_DA0 B VMI DA1 45 PAD_DA1 B VPI DA2 46 PAD_DA2 B RXACT DA3 47 PAD_DA3 B TXV DA4 48 PAD_DA4 B DA5 50 PAD_DA5 B DA6 61 PAD_DA6 B DA7 62 PAD_DA7 B ©2000-2006 Genesys Logic Inc. - All rights reserved. DO2 PLLDIS DO2 DataO_Sel DO0 TXRDY DO0 Page 27 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 4.6.8 Use Card Interface as USB Test Interface This interface is shared with card interface. This is only for testing. In test mode, the card interface will be also used for USB test patterns: Table 4.8 – Use Card Interface as USB Test Interface Pin Name Pad# Pad Name Type SCAN MOD UTM TEST UTM SCANM UCLK 26 PAD_UCLK B SCAN_EN UCMD 19 PAD_UCMD B HDATA0 29 PAD_UDATA0 HDATA1 38 HDATA2 DO5 SPEED DO5 B DI0 D0 DI0 P1.0 PAD_UDATA1 B DI1 D1 DI1 P1.1 13 PAD_UDATA2 B DI2 D2 DI2 P1.2 HDATA3 15 PAD_UDATA3 B DI3 D3 DI3 P1.3 HDATA4 17 PAD_UDATA4 B DI4 D4 DI4 P1.4 HDATA5 22 PAD_UDATA5 B DI5 D5 DI5 P1.5 HDATA6 34 PAD_UDATA6 B DI6 D6 DI6 P1.6 HDATA7 36 PAD_UDATA7 B DI7 D7 DI7 P1.7 ©2000-2006 Genesys Logic Inc. - All rights reserved. CPU TEST Page 28 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution CHAPTER 5 ELECTRICAL CHARACTERISTICS 5.1 Absolute Maximum Ratings Table 5.1 – Absolute Maximum Ratings Parameter Symbol Min Max. Unit Remark VDD 2.0 3.6 V CMD0, 15,55, ACMD41 Supply Voltage Differentials (Vss1, Vss2) -0.3 0.3 V Storage Temperature -40 85 o C 95 o C Supply Voltage Junction Temperature 5.2 Bus Operating Conditions Table 5.2 – Bus Operating Conditions Parameter Symbol Min Max. Unit VDD 2.6 3.6 V 85 o Peak Voltage on all Lines Ground Voltage 0 Operation Temperature -25 Operation Moisture and Corrosion Remark V C 95% Rel. humidity 5.3 D.C. Characteristics Table 5.3 – D.C. Characteristics Parameter Supply voltage Symbol Condition VCC Min Type Max Unit 2.0 3.3 3.6 V Input Leakage Current (HCLK, HCMD and HDATA2-0 to II 0< VIN < VCC 0.2 - 0.3 µA II 0< VIN < VCC 0.2 - 0.3 µA Ground) Input Leakage Current (HCLK, HCMD and HDATA2-0 to VDD) ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 29 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution Input Leakage Current at HDATA3 to II 0< VIN < VCC - - 0.43 µA Output High Voltage at HCMD VOH Clock = 20MHZ - - 3588 mV Output High Voltage at HDATA VOH Clock = 20MHZ - - 3586 mV Output Low Voltage at HCMD VOL Clock = 20MHZ 39 - - mV Output Low Voltage at HDATA VOL Clock = 20MHZ 39 - - mV Read/Write Current ICC - - Ground ©2000-2006 Genesys Logic Inc. - All rights reserved. mA Page 30 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution CHAPTER 6 PACKAGE DIMENSION Figure 6.1 – GL422/GL423 56 Pin QFN Package ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 31 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution Figure 6.2 – GL422/GL423 54 Pin VFBGA Package ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 32