a Dual Precision JFET-Input Operational Amplifier OP215 FEATURES High Slew Rate: 10 V/s Min Fast Settling Time: 0.9 s to 0.1% Type Low Input Offset Voltage Drift: 10 V/C Max Wide Bandwidth: 3.5 MHz Min Temperature-Compensated Input Bias Currents Guaranteed Input Bias Current: 18 nA Max (125C) Bias Current Specified Warmed Up over Temperature Low Input Noise Current: 0.01 pA/÷Hz Type High Common-Mode Rejection Ratio 86 dB Min Pin Compatible with Standard Dual Pinouts Models with MIL-STD-883 Class B Processing Available GENERAL DESCRIPTION The OP215 offers the proven JFET-input performance advantages of high speed and low input bias current with the tracking and convenience advantages of a dual op amp configuration. Low input offset voltages, low input currents, and low drift are featured in these high-speed amplifiers. On-chip zener-zap trimming is used to achieve low VOS, while a bias-current compensation scheme gives a low input bias current V+ J5 Q5 Q6 R8 J8 J7 NULL R7 at elevated temperature. Thus, the OP215 features an input bias current of 1.4 nA at 70∞C ambient (not junction) temperature which greatly extends the application usefulness of this device. Applications include high-speed amplifiers for current output DACs, active filters, sample-and-hold buffers, and photocell amplifiers. For additional precision JFET op amps, see the OP249 and AD712 data sheets. NOTE R7, R8 ARE ELECTRONICALLY ADJUSTED ON-CHIP FOR MINIMUM OFFSET VOLTAGE Q10 NULL Q9 Q7 R3 Q19 J6 R1 Q24 Q8 NOMINV INPUT+ J2 J1 R2 –INV J11 INPUT C2 Q17 Q1 Q3 Q4 J3 OUTPUT Q18 Q11 J4 7.4 pF Q22 Q2 Q12 C1 R13 7.4pF R9 R4 R5 3.6 k Q16 R6 3.6k R10 J10 Q23 Q14 Q13 Q25 J9 Q15 Q21 Q20 R11 R12 V– Figure 1. Simplified Schematic (1/2 OP215) REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 OP215–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (at V = ±15 V, T = 25C, unless otherwise noted.) S Parameter A Min OP215E Type Max Min OP215G Type Max Symbol Conditions Input Offset Voltage VOS RS = 50 W ‘G’ Grade 0.2 1.0 2.0 2.5 4.0 6.0 mV mV Input Offset Current1 IOS Tj = 25∞C Device Operating 3 5 50 100 3 5 100 200 pA pA Input Bias Current1 IB Tj = 25∞C Device Operating ± 15 ± 18 ± 100 ± 300 ± 15 ± 18 ± 300 ± 600 pA pA Input Resistance RIN Large-Signal Voltage Gain AVO RL ⱖ 2 kW, VO = ± 10 V 150 500 Output Voltage Swing VO RL = 10 kW RL = 2 kW ± 12 ± 11 ± 13 ± 12.7 Supply Current ISY 101,2 W 50 200 V/mV ± 12 ± 11 ± 13 ± 12.7 V V 101,2 6.0 8.5 7.0 7.0 ‘G’ Grade Slew Rate SR Gain Bandwidth Product3 GBW AVCL = 1 Unit 10.0 12.0 mA mA 10 18 5 15 V/s 3.5 5.7 3.0 5.4 MHz Closed-Loop Bandwidth CLBW AVCL = 1 13 12 MHz Setting Time tS To 0.01% To 0.05%2 To 0.10% 2.3 1.1 0.9 2.4 1.2 1.0 s s s Input Voltage Range IVR Common-Mode Rejection Ratio CMRR VCM = ± IVR E, G Grades Power Supply Rejection Ratio PSRR VS = ± 10 V to ± 16 V VS = ± 10 V to ± 15 V 10 Input Noise Voltage Density n fO = 100 Hz fO = 1,000 Hz 20 15 20 15 nV/÷Hz nV/÷Hz Input Noise Current Density In fO = 100 Hz fO = 1,000 Hz 0.01 0.01 0.01 0.01 pA/÷Hz pA/÷Hz Input Capacitance CIN 3 3 pF 10.2 –10.2 14.8 –11.5 10.1 –10.1 14.8 –11.5 V V 82 100 80 96 dB 51 16 100 V/V V/V NOTES 1 Input bias current is specified for two different conditions. The T j = 25∞C specification is with the junction at ambient temperature; the device operating specification is with the device operating in a warmed up condition at 25∞C ambient. The warmed up bias-current value is correlated to the junction temperature value via the curves of IS versus Tj and IS versus TA. PMI has a bias-current compensation circuit that gives improved bias current and bias current over temperature versus standard JFET input op amps. I S and IOS are measured at V CM = 0. 2 Setting time is defined here for a unity gain inverter connection using 2 kW resistors. It is the time required for the error voltage (the voltage at the inverting input pin on the amplifier) to settle to within a specified percent of its final value from the time a 10 V step input is applied to the inverter. See setting time test circuit. 3 Sample tested. Specifications are subject to change without notice. –2– REV. A OP215 SPECIFICATIONS (at VS = ±15 V, 0C ⱕ TA ⱕ 70C for E Grade, –40C ⱕ TA ⱕ +85C for G Grade, unless ELECTRICAL CHARACTERISTICS otherwise noted.) Parameter OP215E Type Max RS = 50 W 0.4 1.65 3.5 3 3 15 RP = 100 kW 6 4 Tj = 70∞C TA = 70∞C Device Operating 0.06 0.08 0.45 0.80 0.08 0.10 0.65 1.2 nA nA Tj = 70∞C TA = 70∞C Device Operating ± 0.12 ± 0.16 ± 0.70 ± 1.40 ± 0.14 ± 0.19 ± 0.9 ± 1.8 nA nA Min Min OP215G Type Max Symbol Conditions Input Offset Voltage VOS Average Input Offset Voltage Drift Without External Trim1 With External Trim TCVOS TCVOSn Input Offset Current2 IOS Input Bias Current2 IS Input Voltage Range IVR Common-Mode Rejection Ratio CMRR VCM = ± IVR Power Supply Rejection Ratio PSRR VS = ± 10 V to ± 16 V VS = ± 10 V to ± 15 V Large-Signal Voltage Gain AVO RL ⱖ 2 kW VO = ± 10 V 50 180 35 130 V/mV Output Voltage Swing VO RL ⱖ 10 kW ± 12 ± 13 ± 12 ± 13 V 8.0 Unit mV V/∞C V/∞C 10.2 –10.2 14.7 –11.4 10.1 –10.1 14.7 –11.3 V V 80 98 76 94 dB 13 100 20 159 V/V NOTES 1 Sample tested. 2 Input bias current is specified for two different conditions. The T j = 25∞C specification is with the junction at ambient temperature; the Device Operating specification is with the device operating in a warmed up condition at 25∞C ambient. The warmed up bias-current value is correlated to the junction temperature value via the curves of IS versus Tj and IS versus TA. PMI has a bias-current compensation circuit that gives improved bias current and bias current over temperature versus standard JFET input op amps. I S and IOS are measured at V CM = 0. Specifications are subject to change without notice. REV. A –3– OP215 ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage OP215E, OP215G . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Operating Temperature Range OP215E . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0∞C to +70∞C OP215G . . . . . . . . . . . . . . . . . . . . . . . . . . . –40∞C to +85∞C Maximum Junction Temperature (Tj) . . . . . . . . . . . . . . 150∞C Differential Input Voltage OP215E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 40 V OP215G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 30 V Input Voltage2 OP215E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 V OP215G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 16 V Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . 300∞C Junction Temperature (Tj) . . . . . . . . . . . . . –65∞C to +150∞C Package Type JA * JC Unit 8-Lead Hermetic DIP (Z) 8-Lead Plastic DIP (P) 134 96 12 37 ∞C/W ∞C/W *JA is specified for worst-case mounting conditions, i.e., JA is specified for device in socket for CerDIP and P-DIP packages. PIN CONFIGURATION OUT A 1 –IN A 2 +IN A 3 6 –IN B V– 4 5 +IN B A B – + + – 8 V+ 7 OUT B NOTES 1 Absolute maximum ratings apply to packaged parts, unless otherwise noted. 2 Unless otherwise specified, the absolute maximum negative input voltage is equal to one volt more positive than the negative power supply voltage. ORDERING INFORMATION 1 Model Package Type Temperature Range TA = 25∞C, VOS Max (mV) OP215EZ2 8-Lead CerDIP COM 1.0 OP215GP2 8-Lead Plastic DIP XIND 6.0 For military processed devices, please refer to the standard microcircuit drawing (SMD) available at www.dscc.dla.mil/programs/milspec/default.asp SMD Part Number 5962-8853801GA 5962-8853801PA 5962-8838032A2 2 ADI Equivalent OP215AJMDA OP215AZMDA OP215BRCMDA NOTES 1 Burn-in is available on commercial and industrial temperature range parts in CerDIP and plastic DIP packages. 2 Not for new design, obsolete April 2002. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP215 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. A Typical Performance Characteristics–OP215 500ns OUTPUT VOLTAGE SWING FROM 0V – V 10 100ns 100 100 90 90 10 10 0% 0% 5V 20mV VS = 15V TA = 25C AV = –1 5 –5 100 8 6 140 150 AV > 10 4 2 0 –2 –4 –6 VS = 15V –8 TA = 25C –10 1M 160 170 180 190 AV = 1 10M FREQUENCY – Hz 24 BANDWIDTH – MHz 120 130 200 12 8 TPC 7. Maximum Output Swing vs. Frequency 100 1.0 1.5 2.0 SETTLING TIME – s 0 –50 2.5 VS = 15V TA = 25C 100 80 60 40 20 0 -20 125 NEGATIVE 30 10 REV. A 0.5 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY – Hz TPC 6. Open-Loop Frequency Response 100 40 4 10M 0 25 50 75 TEMPERATURE – C 50 20 1M FREQUENCY – Hz –25 AV = 1 60 VS = 15V 8 0 100K GAIN BANDWIDTH PRODUCT 70 SLEW RATE – V/s 12 CLOSED-LOOP BANDWIDTH AV = 1 TPC 5. Bandwidth vs. Temperature VS = 15V TA = 25C AV = 1 16 BANDWIDTH VARIATION FROM 5 < VS < 20V IS < 5% 16 0 –50 28 20 20 4 100M TPC 4. Closed-Loop Bandwidth and Phase Shift vs. Frequency 24 1mV VS = 15V 110 12 10 PEAK-TO-PEAK AMPLITUDE – V GAIN – dB 14 5mV 120 28 PHASE SHIFT – Degrees PHASE MARGIN = 66 10mV TPC 3. Settling Time OPEN-LOOP VOLTAGE GAIN – dB 90 1mV 0 TPC 2. Small-Signal Transient Response COMMON-MODE REJECTION RATIO – dB 18 16 5mV 0 –10 TPC 1. Large-Signal Transient Response 10mV POSITIVE –25 0 25 50 75 100 AMBIENT TEMPERATURE – C 125 TPC 8. Slew Rate vs. Temperature –5– VS = 15V TA = 25C 80 60 40 20 0 1 10 100 1k 10k 100k 1M FREQUENCY– Hz 10M 100M TPC 9. Common-Mode Rejection Ratio vs. Frequency OP215 120 VS = 15V TA = 25C 100 90 POSITIVE SUPPLY 80 70 NEGATIVE SUPPLY 60 50 40 30 100 AV = 100 10 AV = 10 1 20 AV = 1 10 0 10 VS = 15V 120 TS = 25C VOLTAGE NOISE DENSITY – nV/ Hz TA = 25C OUTPUT IMPEDANCE – POWER SUPPLY REJECTION – dB 140 100 110 100 1k 10k 100k FREQUENCY – Hz 1M 10k 100k FREQUENCY – Hz 1k TPC 10. Power Supply Rejection vs. Frequency 60 40 1M 10M TPC 11. Output Impedance vs. Frequency 1/f CORNER FREQUENCY 20 0 0.1 10M 80 1 10 100 1k FREQUENCY – Hz 10k TPC 12. Voltage Noise Density vs. Frequency BASIC CONNECTIONS V+ 2k 0.1% +15V 2k 0.1% 5k 0.1% 10V 0 2 8 OP215 A 3 –IN 1 2N4416 SUMMING MODE 3k OUT A +IN VOUT V– 5k 0.1% SCOPE OP215 A 100pF 4 –15V Rp 100k AV = –1 2N4416 NOTE VOS CAN BE TRIMMED WITH POTENTIOMETERS RANGING FROM 10 k TO 1 M. FOR MOST UNITS TCVOS WILL BE MINIMUM WHEN VOS IS ADJUSTED WITH A 100k POTENTIOMETER. +15V 2k Figure 4. Input Offset Voltage Nulling Figure 2. Settling Time Test Circuit +15V +5V 2 8 0V –5V VIN 3 1 OP215 A 4 2k VOUT 100pF –15V Figure 3. Slew Rate Test Circuit –6– REV. A OP215 BASIC CONNECTIONS APPLICATIONS INFORMATION Dynamic Operating Considerations +15V As with most amplifiers, care should be taken with lead dress, component placement, and supply de-coupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize “pick up” and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. 100k 6 200 A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to ac ground sets the frequency of the pole. In many instances, the frequency of this pole is much greater than the expected 3 dB frequency of the closed-loop gain and, consequently, there is negligible effect on stability margin. However, if the feedback pole is less than approximately six times the expected 3 dB frequency, a lead capacitor should be placed from the output to the negative input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than, or equal to, the original feedback pole time constant. 8 7 OP215 B 5 100k 2 3 1 OP215 A 4 –15V NOTES 1. TA = 125C TO 150C 2. RESISTORS ARE TYPE RN55D, 1% Figure 5. Burn-In Circuit OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead CERDIP (Z-Suffix) 0.005 (0.13) MIN 8 8-Lead Plastic DIP (P-Suffix) 0.430 (10.92) 0.348 (8.84) 0.055 (1.4) MAX 5 8 0.310 (7.87) 0.220 (5.59) PIN 1 1 1 PIN 1 0.320 (8.13) 0.290 (7.37) 0.405 (10.29) MAX 0.200 (5.08) 0.125 (3.18) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.150 (3.81) MIN SEATING 0.023 (0.58) 0.070 (1.78) PLANE 0.014 (0.36) 0.030 (0.76) REV. A 0.280 (7.11) 0.240 (6.10) 4 4 0.100 (2.54) BSC 0.200 (5.08) MAX 5 15° 0° 0.100 (2.54) BSC 0.325 (8.25) 0.300 (7.62) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN 0.022 (0.558) 0.070 (1.77) SEATING 0.014 (0.356) 0.045 (1.15) PLANE 0.015 (0.38) 0.008 (0.20) –7– 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) OP215 Revision History Location Page Data Sheet changed from REV. 0 to REV. A. Edits to ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3 Edits to ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edits to PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edits to PACKAGE TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 C02683–0–4/02(A) Edits to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Deleted WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Deleted DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Deleted TYPICAL ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 PRINTED IN U.S.A. Edits to BURN-IN CIRCUIT figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 –8– REV. A