CY74FCT191T 4-BIT UP/DOWN BINARY COUNTER SCCS016A – MAY 1994 – REVISED SEPTEMBER 2001 D D D D D D D Q OR SO PACKAGE (TOP VIEW) Function, Pinout, and Drive Compatible With FCT and F Logic Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics Ioff Supports Partial-Power-Down Mode Operation ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Matched Rise and Fall Times 64-mA Output Sink Current 32-mA Output Source Current P1 Q1 Q0 CE U/D Q2 Q3 GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC P0 CP RC TC PL P2 P3 description The CY74FCT191T is a reversible modulo-16 binary counter, featuring synchronous counting and asynchronous presetting. The preset allows the CY74FCT191T to be used in programmable dividers. The count enable input, terminal count output, and ripple-clock output make possible a variety of methods of implementing multiusage counters. In the counting modes, state changes are initiated by the rising edge of the clock. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. PIN DESCRIPTION NAME DESCRIPTION CE Count enable input (active low) CP Clock pulse input (active rising edge) P Parallel data inputs PL Asynchronous parallel load input (active low) U/D Up/down count control input Q Flip-flop outputs RC Ripple clock output (active low) TC Terminal count output Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CY74FCT191T 4-BIT UP/DOWN BINARY COUNTER SCCS016A – MAY 1994 – REVISED SEPTEMBER 2001 ORDERING INFORMATION QSOP – Q –40°C to 85°C SPEED (ns) PACKAGE† TA SOIC – SO SOIC – SO ORDERABLE PART NUMBER Tape and reel 6.2 CY74FCT191CTQCT Tube 6.2 CY74FCT191CTSOC Tape and reel 6.2 CY74FCT191CTSOCT Tube 7.8 CY74FCT191ATSOC TOP-SIDE MARKING FT191-3 FCT191C FCT191A Tape and reel 7.8 CY74FCT191ATSOCT † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Function Tables RC FUNCTION INPUTS CE OUTPUTS TC† RC CP L H H X X H X X L H H = High logic level, L = Low logic level, X = Don’t care, = Low pulse † TC is generated internally. MODE SELECT INPUTS MODE PL CE U/D CP H L L ↑ Count up H L H ↑ Count down L X X X Preset (asynchronous) H H X X No change (hold) H = High logic level, L = Low logic level, X = Don’t care, ↑ = Low-to-high clock transition 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CY74FCT191T 4-BIT UP/DOWN BINARY COUNTER SCCS016A – MAY 1994 – REVISED SEPTEMBER 2001 logic diagram (positive logic) 12 CE U/D CP PL P0 TC 4 13 RC 5 14 11 15 3 S Q0 C1 1D R P1 1 2 S Q1 C1 1D R P2 10 6 S C1 Q2 1D R P3 9 7 S Q3 C1 1D R POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CY74FCT191T 4-BIT UP/DOWN BINARY COUNTER SCCS016A – MAY 1994 – REVISED SEPTEMBER 2001 absolute maximum rating over operating free-air temperature range (unless otherwise noted)† Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA Package thermal impedance, qJA (see Note 1): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W Ambient temperature range with power applied, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65_C to 135_C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65_C to 150_C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 2) VCC VIH Supply voltage VIL IOH Low-level input voltage IOL TA High-level input voltage NOM MAX UNIT 4.75 5 5.25 V 2 V 0.8 V High-level output current – 32 mA Low-level output current 64 mA 85 °C Operating free-air temperature –40 NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. 4 MIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CY74FCT191T 4-BIT UP/DOWN BINARY COUNTER SCCS016A – MAY 1994 – REVISED SEPTEMBER 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL VH TEST CONDITIONS VCC = 4.75 V, VCC = 4.75 V, IIN = –18 mA IOH = –32 mA VCC = 4.75 V, VCC = 4.75 V, IOH = –15 mA IOL = 64 mA MIN TYP† MAX –0.7 –1.2 2 2.4 All inputs 0.55 V 5 µA ±1 µA 0.2 II IIH VCC = 5.25 V, VCC = 5.25 V, VIN = VCC VIN = 2.7 V IIL IOS‡ VCC = 5.25 V, VCC = 5.25 V, VIN = 0.5 V VOUT = 0 V Ioff VCC = 0 V, VOUT = 4.5 V ICC ∆ICC VCC = 5.25 V, VIN < 0.2 V, VIN > VCC – 0.2 V VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open ICCD¶ VCC = 5.25 V, One bit switching at 50% duty cycle, Preset mode, Outputs open, MR = VCC = SR, PL = CE = U/D = CP = GND, VIN < 0.2 V or VIN > VCC – 0.2 V IC# VCC = 5.25 V, Preset mode,, Outputs open, PL = CE = U/D = CP = GND –60 V V 3.3 0.3 UNIT V ±1 µA –120 –225 mA ±1 µA 0.1 0.2 mA 0.5 2 mA 0.06 0.12 mA/ MHz One bit switching at f1 = 5 MHz at 50% duty cycle VIN = VCC or GND 0.4 0.8 mA VIN = 3.4 V or GND 0.7 1.8 mA Four bits switching at f1 = 5 MHz at 50% duty cycle VIN = VCC or GND 1.3 2.6|| mA VIN = 3.4 V or GND 2.3 6.6|| mA 5 10 pF Ci Co 9 12 pF † Typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. § Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND ¶ This parameter is derived for use in total power-supply calculations. # IC = ICC + ∆ICC × DH × NT + ICCD (f0/2 + f1 × N1) Where: IC = Total supply current ICC = Power-supply current with CMOS input levels ∆ICC = Power-supply current for a TTL high input (VIN = 3.4 V) DH = Duty cycle for TTL inputs high NT = Number of TTL inputs at DH ICCD = Dynamic current caused by an input transition pair (HLH or LHL) f0 = Clock frequency for registered devices, otherwise zero f1 = Input signal frequency N1 = Number of inputs changing at f1 All currents are in milliamperes and all frequencies are in megahertz. || Values for these conditions are examples of the ICC formula. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CY74FCT191T 4-BIT UP/DOWN BINARY COUNTER SCCS016A – MAY 1994 – REVISED SEPTEMBER 2001 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) CY74FCT191AT PARAMETER tw tsu th trec CP Pulse duration MIN High or Low PL low Setup time Hold time Recovery time Data before PL↓ High or Low MAX CY74FCT191CT MIN 4 4 5.5 5 4 3.5 CE before CP↑ Low 9 7.2 U/D before CP↑ High or Low 10 8 Data after PL↓ High or Low 1.5 1 CE after CP↑ Low 0 0 U/D after CP↑ High or Low 0 0 5 4.5 PL after CP↑ MAX UNIT ns ns ns ns switching characteristics over operating free-air temperature range (see Figure 1) FROM (INPUT) TO (OUTPUT) tPLH tPHL CP Qn tPLH tPHL CP TC tPLH tPHL CP RC tPLH tPHL CE RC tPLH tPHL U/D RC tPLH tPHL U/D TC tPLH tPHL Pn Qn tPLH tPHL PL Qn PARAMETER 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CY74FCT191AT CY74FCT191CT MIN MAX MIN MAX 1.5 7.8 1.5 6.2 1.5 7.8 1.5 6.2 1.5 11.8 1.5 9.4 1.5 11.8 1.5 9.4 1.5 8.5 1.5 6.8 1.5 8.5 1.5 6.8 1.5 7.2 1.5 6 1.5 7.2 1.5 6 1.5 13 1.5 11 1.5 13 1.5 11 1.5 7.2 1.5 6.1 1.5 7.2 1.5 6.1 1.5 9.1 1.5 7.7 1.5 9.1 1.5 7.7 2 8.5 2 7.2 2 8.5 2 7.2 UNIT ns ns ns ns ns ns ns ns CY74FCT191T 4-BIT UP/DOWN BINARY COUNTER SCCS016A – MAY 1994 – REVISED SEPTEMBER 2001 PARAMETER MEASUREMENT INFORMATION 7V From Output Under Test From Output Under Test Test Point CL = 50 pF (see Note A) Open TEST GND CL = 50 pF (see Note A) 500 Ω S1 500 Ω S1 Open 7V Open tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω LOAD CIRCUIT FOR 3-STATE OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw tsu 3V 1.5 V Input 1.5 V th 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH tPHL 1.5 V 1.5 V VOL tPHL Out-of-Phase Output tPLZ ≈3.5 V 1.5 V tPZH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V Output Waveform 1 (see Note B) tPLH 1.5 V 1.5 V tPZL VOH In-Phase Output 3V Output Control Output Waveform 2 (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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